NCP1615 High Voltage High Efficiency Power Factor Correction Controller The NCP1615 is a high voltage PFC controller designed to drive PFC boost stages based on an innovative Current Controlled Frequency Foldback (CCFF) method. In this mode, the circuit operates in critical conduction mode (CrM) when the inductor current exceeds a programmable value. When the current is below this preset level, the NCP1615 linearly decays the frequency down to a minimum of about 26 kHz at the sinusoidal zero−crossing. CCFF maximizes the efficiency at both nominal and light load. In particular, the standby losses are reduced to a minimum. Innovative circuitry allows near− unity power factor even when the switching frequency is reduced. The integrated high voltage start−up circuit eliminates the need for external start−up components and consumes negligible power during normal operation. Housed in a SOIC−14 or SOIC−16 package, the NCP1615 incorporates the features necessary for robust and compact PFC stages, with few external components. http://onsemi.com • 16 14 1 1 NCP1615X X A WL Y WW G HV • • • • • November, 2013 − Rev. 1 Open Pin Protection for FB and FOVP/BUV Pins Internal Thermal Shutdown Bi−Level Latch Input for OVP and OTP Bypass/Boost Diode Short Circuit Protection Open Ground Pin Protection Typical Applications • • • • PC Power Supplies Off Line Appliances Requiring Power Factor Correction LED Drivers Flat TVs PIN CONNECTIONS FB HV Restart VCC DRV GND CS/ZCD PFCOK PSTimer NCP1615 16 Pins (Top View) © Semiconductor Components Industries, LLC, 2013 = Specific Device Code = A, B, C or D = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Adjustable Bulk Undervoltage Detection (BUV) Soft Overvoltage Protection Line Overvoltage Protection Overcurrent Protection HVFB FB Restart FOVP/BUV VControl FFControl Fault STDBY NCP1615XG AWLYWW NCP1615XG AWLYWW See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Safety Features • • • • SOIC−14 NB CASE 751AN MARKING DIAGRAMS • High Voltage Start−Up Circuit with Integrated Brownout Detection • Input to Force Controller into Standby Mode • Restart Pin Allows Adjustment of Bulk Voltage Hysteresis in • • • • • • • • 1 1 SOIC−16 NB CASE 752AC General Features Standby Mode Skip Mode Near the Line Zero Crossing Fast Line / Load Transient Compensation Valley Switching for Improved Efficiency High Drive Capability: −500 mA/+800 mA Wide VCC Range: from 9.5 V to 28 V Input Voltage Range Detection Input X2 Capacitor Discharge Circuitry Power Saving Mode (PSM) Enables < 30 mW No−load Power Consumption This is a Pb and Halogen Free Device 14 16 FOVP/BUV VCC VControl DRV FFControl GND Fault CS/ZCD STDBY PFCOK NCP1615 14 Pins (Top View) 1 Publication Order Number: NCP1615/D NCP1615 Dbypass Lin F1 Dboost Lboost Mboost Vaux L Cbulk Rdrv BD1 L1 Rgs Daux Lcm RV1 BD2 CX1 BD3 Cin1 Rhv1 Raux Rsense Cin2 N1 DRV Rzcd Rhv2 Dhv1 BD4 U1 HVFB FB Restart PFCok CS/ZCD FOVP/BUV STDBY Fault VCC Control FFcontrol DRV PStimer GND Ccomp2 Rff Rfault Ccomp1 Rrestart1 HV PFCok Rcomp1 Rfb2 Dhv2 Rcs N Rfb1 L1 N1 PSM_Control NCP1615C/D Rfovp/buv1 Standby Rrestart2 DRV Rfovp/buv2 Cvcc Ext. Vcc Cpsm Rpsm Vaux Figure 1. NCP1615C/D Typical Application Circuit Dbypass Lin Dboost Lboost F1 L Vaux BD1 RX1 BD2 Rhv1 Cin1 Raux RX2 Rsense Cin2 N1 Rzcd Dhv1 Rcs BD4 PFCok Rcomp1 Rfault Cbulk DRV Rhv2 Rfb2 Dhv2 U1 Rrestart1 FB Restart PFCok FOVP/BUV CS/ZCD STDBY Fault VCC DRV Control GND FFcontrol HV NCP1615A/B Ccomp2 Rff Ccomp1 Rfb1 L1 N1 Rgs Daux BD3 CX1 N Rdrv L1 Lcm RV1 Mboost Standby DRV Cvcc Rfovp/buv1 Rrestart2 Rfovp/buv2 Ext. Vcc Vaux Figure 2. NCP1615A/B Typical Application Circuit http://onsemi.com 2 NCP1615 Enable PFC VCC(on)/VCC(off) OFF VFOVP VUVP2 IFOVP/UVP(bias) VUVP3 Vrestart PWM PWM Comparator R VDD In PSM In PSM PFC_OK IFault Fault PFC_OK Clear OVP Comparator + − − + VDD R Power Saving Mode (PSM) Detector tdelay(OVP) VFault(OVP) OCP Detection of excessive current OverStress RFault(clamp) OTP Comparator Blanking Delay VFault(clamp) t delay(OTP) + Enable PFC VFault(OTP) Delay − tblank(OTP) Version C/D Version A/C ZCD Comparator Auto−Recovery Version B/D Figure 3. NCP1615 Functional Block Diagram http://onsemi.com 3 toff1 LEB VOCP ZCD Auto−Recovery Control VDD In PSM PStimer tOCP(LEB) Latch + − Version A/B Current Limit Comparator DRV STDBY Vstandby VDD VPS_in/ VPS_out DRV Blanking Delay − + Standby VDD DRV LEB tOVS(LEB) VZCD(rising)/ VZCD(falling) ICS/ZCD1 ZCD PWM STOP ICS/ZCD2 SKIP DRV Q IPSTimer1 CLK In_Regulation Restart GND VPSTimer2 S S CLK DT PFCok Driver FOVP/ BUV Clamp In PSM OverStress DRV Q VCC IRestart(bias) Restart_OK PFC_OK Current Information Generator and dead−time control PFCok Istart1 VCC(reset) Auto−Recovery Internal Timing Ramp LLline CENTRAL LOGIC UVP1 Latch Vton OFF DRV VREGUL ISENSE VCC ICC(discharge) VBUV Vton Processing Circuitry LLine FFcontrol BO VREGUL DT Restart_OK SKIP Standby softOVP Regulator Upper Clamp Lower Clamp StaticOVP Level Shift VDD HV IPSTimer2 VREF Error Amplifier VREF VDD IREF OCP staticOVP OverStress Line_OVP Standby Enable PFC STDWN PFC_OK Clear Vton OFF OFF BO STOP Control IFB(bias) DRE VDD Iboost(DRE) VDD Iboost(startup) UVP1 SoftOVP DRE In_Regulation FB Logic FB Line Removal Line Removal Detector BO_NOK Brownout Detector LLine Thermal Line Sense Shutdown Detector ISENSE Line_OVP Istart2 Line OVP Blank Delay IControl(BO) FBHV CS/ZCD NCP1615 Table 1. PIN FUNCTION DESCRIPTION Pin Number NCP1615C/D NCP1615A/B Name Function 1 N/A FBHV High voltage PFC feedback input. An external resistor divider is used to sense the PFC bulk voltage. The divider high side resistor chain from the PFC bulk voltage connects to this pin. An internal high−voltage switch disconnects the high side resistor chain from the low side resistor when the PFC is latched or in PSM in order to reduce input power. 2 1 FB This pin receives a portion of the PFC output voltage for the regulation and the dynamic response enhancer (DRE) that speeds up the loop response when the output voltage drops below 95.5% of the regulation level. VFB is also the input signal for the Soft−Overvoltage Comparators as well as the Undervoltage (UVP) Comparator. The UVP Comparator prevents operation as long as VFB is lower than 12% of the reference voltage (VREF). The Soft−Overvoltage Comparator (Soft−OVP) gradually reduces the duty ratio to zero when VFB exceeds 105% of VREF. A 250 nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is accidentally open. A dedicated comparator monitors the bulk voltage and disables the controller if a line overvoltage fault is detected. 3 2 Restart 4 3 FOVP/BUV Input terminal for the Fast Overvoltage (Fast−OVP) and Bulk Undervoltage (BUV) Comparators. The circuit disables the driver if the VFOVP/BUV exceeds the VFOVP threshold which is set 2% higher than the reference for the Soft−OVP comparator monitoring the FB pin. This allows the both pins to receive the same portion of the output voltage. The BUV Comparator trips when VFOVP/BUV falls below 76% of the reference voltage. A BUV fault disables the driver and grounds the PFCOK pin. The BUV function has no action whenever the PFCOK pin is in low state. Once the downstream converter is enabled the BUV Comparator monitors the output voltage to ensure it is high enough for proper operation of the downstream converter. A 250 nA current pulls down the pin and disable the controller if the pin is accidentally open. 5 4 Control The error amplifier output is available on this pin. The network connected between this pin and ground sets the regulation loop bandwidth. It is typically set below 20 Hz to achieve high power factor ratios. This pin is grounded when the controller is disabled. The voltage on this pin gradually increases during power up to achieve a soft−start. 6 5 FFcontrol This pin sources a current representative to the line current. Connect a resistor between this pin and GND to generate a voltage representative of the line current. When this voltage exceeds the internal 2.5 V reference, the circuit operates in critical conduction mode. If the pin voltage is below 2.5 V, a dead−time is generated that approximately equates [83 ms • (1 − (VFFcontrol/VREF))]. By this means, the circuit increases the deadtime when the current is smaller and decreases the deadtime as the current increases. The circuit skips cycles whenever VFFcontrol is below 0.65 V to prevent the PFC stage from operating near the line zero crossing where the power transfer is particularly inefficient. This does result in a slightly increased distortion of the current. If superior power factor is required, offset the voltage on this pin by more than 0.75 V to inhibit skip operation. 7 6 Fault The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a latch or auto−recovery depending on device version. 8 7 STDBY This pin is used to force the controller into standby mode. 9 N/A PSTimer Power saving mode (PSM) timer adjust. A capacitor between this pin and GND, CPSTimer, sets the delay time before the controller enters power saving mode. Once the controller enters power saving mode the IC is disabled and the current consumption is reduced to a maximum of 100 mA. The input filter capacitor discharge function is available while in power saving mode. The device enters PSM if the voltage on this pin exceeds the PSM threshold, VPS_in. A secondary side controller optocoupler pulls down on the pin to prevent the controller from entering PSM when the load is connected to the power supply. The controller is enabled once VPSTimer drops below VPS_out. 10 8 PFCOK This pin is grounded until the PFC output has reached its nominal level. It is also grounded if the controller detects a fault. The voltage on this pin is 5 V once the controller reaches regulation. This pin receives a portion of the PFC output voltage for determining the restart level after entering standby mode. http://onsemi.com 4 NCP1615 Table 1. PIN FUNCTION DESCRIPTION Pin Number NCP1615C/D NCP1615A/B Name Function 11 9 CS/ZCD This pin monitors the MOSFET current to limit its maximum current. This pin is also connected to an internal comparator for zero current detection (ZCD). This comparator is designed to monitor a signal from an auxiliary winding and to detect the core reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a diode to avoid altering the current sense information for the on time (see application schematic). 12 10 GND Ground reference. 13 11 DRV MOSFET driver. The high current capability of the totem pole gate drive (−0.5/ +0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 14 12 VCC Supply input. This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds VCC(on). After start−up, the operating range is 9.5 V up to 28 V. 15 13 16 14 Removed for creepage distance. HV This pin is the input for the line removal detection, line level detection, and brownout detection circuits. For versions C and D, this pin is also the input for the high voltage start−up circuit. Table 2. ORDERING INFORMATION Part Number Device Marking VCC HV Start−Up OTP Fault PSM X2 Discharge Brownout Package Shipping† NCP1615ADR2G NCP1615A 10.5 V No Latch No No 100 Vdc 3000 / Tape & Reel NCP1615BDR2G NCP1615B 10.5 V No Auto−Recovery No No 100 Vdc SOIC−14 NB, LESS PIN 13 (Pb−Free) NCP1615CDR2G NCP1615C 17 V Yes Latch Yes Yes 100 Vdc NCP1615C2DR2G NCP1615C2 17 V Yes Latch Yes Yes 87 Vdc 3000 / Tape & Reel NCP1615DDR2G NCP1615D 17 V Yes Auto−Recovery Yes Yes 100 Vdc SOIC−16 NB, LESS PIN 15 (Pb−Free) NCP1615D2DR2G NCP1615D2 17 V Yes Auto−Recovery Yes Yes 87 Vdc †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NCP1615 Table 3. MAXIMUM RATINGS (Notes 3 and 4) Pin Symbol Value Unit HV VHV −0.3 to 700 V High Voltage Feedback Input Voltage FBHV VFBHV −0.3 to 700 V High Voltage Feedback Input Current FBHV IFBHV 0.5 mA Zero Current Detection and Current Sense Input Voltage (Note 5) CS/ZCD VCS/ZCD −0.3 to VCS/ZCD(MAX) V Zero Current Detection and Current Sense Input Current CS/ZCD ICS/ZCD +5 mA Control Input Voltage (Note 6) Control VControl −0.3 to VControl(MAX) V Supply Input Voltage VCC VCC(MAX) −0.3 to 28 V Fault Input Voltage Fault VFault −0.3 to (VCC + 0.6) V PSTimer VPSTimer −0.3 to (VCC + 0.6) V Rating High Voltage Start−Up Circuit Input Voltage PSTimer Input Voltage Driver Maximum Voltage (Note 7) DRV VDRV −0.3 to VDRV V Driver Maximum Current DRV IDRV(SRC) IDRV(SNK) 500 800 mA Other Pins VMAX −0.3 to 7 V TJ −40 to 150 °C TSTG –60 to 150 °C TL(MAX) 300 °C MSL 1 − Maximum Input Voltage (Note 8) Maximum Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Moisture Sensitivity Level Power Dissipation (TA = 70°C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper Clad) Plastic Package SOIC−14NB/SOIC−16NB Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad) Plastic Package SOIC−14NB/SOIC−16NB PD 465 RqJA RqJC ESD Capability (Note 9) Human Body Model per JEDEC Standard JESD22−A114E. Machine Model per JEDEC Standard JESD22−A114E. Charge Device Model per JEDEC Standard JESD22−C101E. mW 172 68 > 2000 > 200 > 500 °C/W V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. All references to Version C include Versions C/C2, unless otherwise noted. 2. All references to Version D include Versions D/D2, unless otherwise noted. 3. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78. 4. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow. 5. VCS/ZCD(MAX) is the CS/ZCD pin positive clamp voltage. 6. VControl(MAX) is the Control pin positive clamp voltage. 7. When VCC exceeds the driver clamp voltage (VDRV(high)), VDRV is equal to VDRV(high). Otherwise, VDRV is equal to VCC. 8. When the voltage applied to these pins exceeds 5.5 V, they sink a current about equal to (Vpin − 5.5 V) / (4 kW). An applied voltage of 7 V generates a sink current of approximately 0.375 mA. 9. Pins HV, PFBHV are rated to the maximum voltage of the part, or 700 V. http://onsemi.com 6 NCP1615 Table 4. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl = 10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open, VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Start−Up Threshold A/B Version C/D Version VCC increasing VCC(on) Minimum Operating Voltage VCC decreasing VCC(off) VCC(on) − VCC(off) VCC(HYS) Min Typ Max 9.75 16.0 10.50 17.0 11.25 18.0 8.5 9.0 9.5 1.0 7.0 1.5 8.0 – – Unit START−UP AND SUPPLY CIRCUITS VCC Hysteresis A/B Version C/D Version Internal Latch / Logic Reset Level V V V VCC decreasing VCC(reset) 7.3 7.8 8.3 V VCC(off) − VCC(reset) DVCC(reset) 0.5 – – V Version C/D VCC(PS_on) – 11 – V Transition from Istart1 to Istart2 (C/D Version) VCC increasing, IHV = 650 mA VCC(inhibit) – 0.8 – V Start−Up Time (C/D Version) CVCC = 0.47 mF, VCC = 0 V to VCC(on) tstart−up – – 2.5 ms Inhibit Current Sourced from VCC Pin (C/D Version) VCC = 0 V, VHV = 100 V Istart1 0.375 0.5 0.87 mA Start−Up Current Sourced from VCC Pin (C/D Version) VCC = VCC(on) – 0.5 V, VHV = 100 V Istart2 6.5 12 16.5 mA VHV = 400 V VHV = 700 V IHV(off1) IHV(off2) – – – – 30 50 mA Istart2 = 6.5 mA, VCC = VCC(on) – 0.5 V Istart2 = 6.5 mA, VCC = VCC(PS_on) – 0.5 V VHV(MIN) – – 38 VHV(MIN_PSM) – – 30 ICC1 ICC2 ICC2b ICC3 ICC4 ICC5 − – – – – − − 0.6 0.6 – – 2.0 0.1 1.0 1.0 1.0 2.8 3.5 tline(removal) 60 100 165 ms tline(discharge) 21 32 60 ms ICC(discharge) 20 10 25 16.5 30 30 mA HV Discharge Level (C/D Version) VHV(discharge) – – 40 V VCC Discharge Level (C/D Version) VCC(discharge) 3.8 4.5 5.4 V 102 86 111 95 118 102 92 78 100 87 108 94 Difference Between VCC(off) and VCC(reset) Regulation Level in Power Saving Mode Start−Up Circuit Off−State Leakage Current Minimum Voltage for Start−Up Circuit Start−Up (C/D Version) During PSM (C/D Version) Supply Current In Power Saving Mode (C/D Version) Latch Before Start−Up (A/B Version) Standby Mode No Switching Operating Current V mA VCC = VCC(PS_on) VFault = 4 V VCC = VCC(on) – 0.5 V Vstandby = 0 V, VRestart = 3 V VFB = 2.55 V f = 50 kHz, CDRV = open, VControl = 2.5 V, VFB = 2.45 V LINE REMOVAL Line Voltage Removal Detection Timer Discharge Timer Duration Discharge Current (C/D Version) VCC = VCC(off) + 200 mV VCC = VCC(discharge) + 200 mV BROWNOUT DETECTION System Start−Up Threshold A/B/C/D Version C2/D2 Version VHV increasing VBO(start) System Shutdown Threshold A/B/C/D Version C2/D2 Version VHV decreasing VBO(stop) http://onsemi.com 7 V V NCP1615 Table 4. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl = 10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open, VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max VHV increasing VBO(HYS) VHV decreasing, delay from VBO(stop) to drive disable Unit 7 5 11 8 – − tBO(stop) 43 54 65 ms tBO(stop) expires IControl(BO) 40 50 60 mA High Line Level Detection Threshold VHV increasing Vlineselect(HL) 232 250 267 V Low Line Level Detection Threshold VHV decreasing Vlineselect(LL) 220 236 252 V Line Select Hysteresis VHV increasing Vlineselect(HYS) 10 – – V High to Low Line Mode Selector Timer VHV decreasing tline 43 54 65 ms Low to High Line Mode Selector Timer VHV increasing tdelay(line) 200 300 400 ms After thigh to low line expires nLL – 8 – PSM Enable Threshold VPSTimer increasing VPS_in 3.325 3.500 3.675 PSM Disable Threshold BROWNOUT DETECTION Hysteresis A/B/C/D Version C2/D2 Version Brownout Detection Blanking Time Control Pin Sink Current in Brownout V LINE DETECTION Line Valley Lockout Counter POWER SAVING MODE (C/D VERSION) V VPSTimer decreasing VPS_out 0.45 0.50 0.55 V PSTimer Pull Up Current Source VPSTimer = 0.9 V IPSTimer1 4.5 5.9 7.3 mA PSTimer Fast Pull Up Current Source VPSTimer = 3.4 V IPSTimer2 800 1000 1200 mA VPSTimer = 4 V IPSTimer(bias) – – 100 nA VPSTimer2 0.95 1.00 1.05 V PSTimer Leakage Current IPSTimer2 Enable Threshold Filter Delay Before Entering PSM VPSTimer > VPS_in tdelay(PS_in) – 40 − ms Detection Delay Before Exiting PSM and Turning On Start−Up Circuit VPSTimer < VPS_out tdelay(PS_out) – – 100 ms VPSTimer = VPSTimer(off) + 10 mV IPSTimer(DIS) 160 – – mA VPSTimer decreasing VPSTimer(off) 0.05 0.10 0.15 V PFC Off−State Leakage Current VPSTimer = 4 V, VHVFB = 500 V IHVFB(off) – 0.1 3 mA PFC Feedback Switch On Resistance VHVFB = 2.75 V, IHVFB = 100 mA RFBswitch(on) – – 10 kW VHV = 162.5 V, VControl = VControl(MAX) VHV = 162.5 V, VControl = 2.5 V VHV = 325 V, VControl = VControl(MAX) ton(LL) 20.5 23.7 27.5 ms ton(LL)2 ton(HL) 9.5 5.2 11.0 6.0 13.0 7.0 tonLL(MIN) tonHL(MIN) – – – – 200 100 ns VILIM 0.46 0.50 0.54 V tOCP(LEB) 100 200 350 ns tOCP(delay) – 40 200 ns tOVS(LEB) 50 100 170 ns PSTimer Discharge Current PSTimer Discharge Turn Off Threshold PFC FB SWITCH (C/D VERSION) ON−TIME CONTROL PFC Maximum On Time Minimum On−Time VHV = 162 V VHV = 325 V CURRENT SENSE Current Limit Threshold Leading Edge Blanking Duration Current Limit Propagation Delay Step VCS/ZCD > VILIM to DRV falling edge Overstress Leading Edge Blanking Duration http://onsemi.com 8 NCP1615 Table 4. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl = 10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open, VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VCS/ZCD > VZCD(rising) to DRV falling edge tOVS(delay) – 40 200 ns TJ = 25°C TJ = −40 to 125°C VREF VREF 2.45 2.44 2.50 2.50 2.55 2.56 V VFB = 2.4 V, VVControl = 2 V VFB = 2.6 V, VVControl = 2 V IEA(SRC) IEA(SNK) 16 16 20 20 24 24 mA VFB = VREF +/− 100 mV gm 180 210 245 mS Maximum Control Voltage VFB = 2 V VControl(MAX) – 4.5 – V Minimum Control Voltage VFB = 2.6 V VControl(MIN) – 0.5 – V CURRENT SENSE Over Stress Detection Propagation Delay REGULATION BLOCK Reference Voltage Error Amplifier Current Source Sink Open Loop Error Amplifier Transconductance EA Output Control Voltage Range VControl(MAX) − VControl(MIN) DVControl 3.9 4.0 4.1 V DRE Detect Threshold VFB decreasing VDRE – 2.388 – V DRE Threshold Hysteresis VFB increasing VDRE(HYS) – – 25 mV Ratio between the DRE Detect Threshold and the Regulation Level VFB decreasing, VDRE / VREF KDRE 95.0 95.5 96.0 % Control Pin Source Current During Start−Up (C/D Version) PFCOK = Low, VVControl = 2 V IControl(start−up) 80 100 113 mA Iboost(start−up) – 80 – mA IControl(DRE) 180 220 250 mA Iboost(DRE) – 200 – mA EA Boost Current During Start−Up (C/D Version) Control Pin Source Current During DRE VVControl = 2 V EA Boost Current During DRE PFC GATE DRIVE Rise Time (10−90%) VDRV from 10 to 90% of VDRV tDRV(rise) – 40 80 ns Fall Time (90−10%) 90 to 10% of VDRV tDRV(fall) – 20 60 ns Source Current Capability VDRV = 0 V IDRV(SRC) − 500 − mA Sink Current Capability VDRV = 12 V IDRV(SNK) − 800 − mA VCC = VCC(off) + 0.2 V, RDRV = 10 kW VCC = 28 V, RDRV = 10 kW VDRV(high1) 8 – – V VDRV(high2) 10 12 14 VSTDBY = 0 V VDRV(low) – – 0.25 V VCS/ZCD rising VCS/ZCD falling VZCD(rising) VZCD(falling) 675 200 750 250 825 300 mV VZCD(rising)/VILIM KZCD/ILIM 1.4 1.5 1.6 – ICS/ZCD = 0.75 mA ICS/ZCD = 5 mA VCS/ZCD(MAX1) VCS/ZCD(MAX2) 7.1 15.4 7.4 15.8 7.8 16.1 V VCS/ZCD = VZCD(rising) VCS/ZCD = VZCD(falling) ICS/ZCD(bias1) ICS/ZCD(bias2) 0.5 0.5 – – 2.0 2.0 mA Measured from VCS/ZCD = VZCD(falling) to DRV rising tZCD – 60 200 ns Measured from VZCD(rising) to VZCD(falling) tSYNC – 110 200 ns toff1 toff2 80 700 200 1000 320 1300 ms High State Voltage Low Stage Voltage ZERO CURRENT DETECTION Zero Current Detection Threshold ZCD and Current Sense Ratio Positive Clamp Voltage CS/ZCD Input Bias Current ZCD Propagation Delay Minimum detectable ZCD Pulse Width Maximum Off−Time (Watchdog Timer) VCS/ZCD > VZCD(rising) http://onsemi.com 9 NCP1615 Table 4. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl = 10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open, VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit Measured after last ZCD transition ttout 20 30 50 ms Detects open pin fault. ICS/ZCD1 – 1 – mA Pulls up at the end of toff1 ICS/ZCD2 – 250 – mA VFFCntrol = 2.6 V VFFCntrol = 1.75 V VFFCntrol = 1.0 V tDT1 tDT2 tDT3 – 4.5 11 – 6.5 13 0 7.5 15 ms FFcontrol Pin Current VHV = 162.5V, VControl = VControl(MAX) VHV = 325 V, VControl = VControl(MAX) IDT1 IDT2 180 92 200 103 220 114 mA FFcontrol Skip Level VFFCntrol = increasing VFFCntrol = decreasing Vskip(out) Vskip(in) – 0.55 0.75 0.65 0.85 – V VSKIP(HYS) 50 – – mV fMIN – 26 – kHz VFB = increasing, VSOVP/VREF KSOVP/VREF 104 105 106 % Soft−OVP Threshold VFB = increasing VSOVP – 2.625 – V Soft−OVP Hysteresis VFB = decreasing VSOVP(HYS) 35 50 65 mV Static OVP Minimum Duty Ratio VFB = 2.55 V, VControl = open DMIN – – 0 % Undervoltage to VREF Ratio VFB = increasing, VUVP1/VREF KUVP1/VREF 8 12 16 % ZERO CURRENT DETECTION Missing Valley Timeout Timer Pull−Up Current Source Source Current for CS/ZCD Impedance Testing CURRENT CONTROLLED FREQUENCY FOLDBACK Dead Time FFcontrol Skip Hysteresis Minimum Operating Frequency FEEDBACK OVER AND UNDERVOLTAGE PROTECTION Soft−OVP to VREF Ratio Undervoltage Threshold VFB = decreasing VUVP1 – 300 – mV Undervoltage to VREF Hysteresis Ratio VFB = increasing VUVP1(HYS) – – 25 mV VFB = VSOVP, HVFB = open VFB = VUVP1, HVFB = open IFB(SNK1) IFB(SNK2) 50 50 200 200 450 450 nA VFOVP – 2.675 – V Feedback Input Sink Current FAST OVERVOLTAGE AND BULK UNDERVOLTAGE PROTECTION (FOVP and BUV) Fast OVP Threshold Fast OVP Hysteresis Ratio Between Fast and Soft OVP Levels Ratio Between Fast OVP and VREF Bulk Undervoltage Threshold VFOVP/BUV increasing VFOVP/BUV decreasing VFOVP(HYS) 15 30 60 mV KFOVP/SOVP = VFOVP/ VSOVP KFOVP/SOVP 101.5 102.0 102.5 % KFOVP/VREF = VFOVP/ VREF KFOVP/VREF 106 107 108 % VFOVP/BUV decreasing VBUV – 1.9 – V KBUV/VREF 74 76 78 % VUVP2 0.2 0.3 0.4 V Undervoltage Protection Threshold to VREF Ratio VFOVP/BUV decreasing, VBUV/VREF Open Pin Detection Threshold VFOVP/BUV decreasing Open Pin Detection Hysteresis VFOVP/BUV increasing VUVP2(HYS) − 10 − mV VFOVP/BUV = VBUV VFOVP/ BUV = VUVP2 IFOVP/BUV(bias1) IFOVP/BUV(bias2) 50 50 200 200 450 450 nA VFB increasing KLOVP 111 112.5 114 % VLOVP – 2.813 – V VFB increasing tLOVP(blank) 45 55 65 ms VSTDBY decreasing Vstandby 285 300 315 mV tblank(STDBY) 0.8 1 1.2 ms Pull−Down Current Source LINE OVP Ratio Between Line OVP and VREF Line Overvoltage Threshold Line Overvoltage Filter STANDBY INPUT Standby Input Threshold Standby Input Blanking Duration http://onsemi.com 10 NCP1615 Table 4. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl = 10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open, VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VRestart/VREF Krestart 97.5 98.0 98.5 % Vrestart – 2.45 – V Irestart(bias) 50 200 450 nA Open Pin Detection Threshold VUVP3 0.2 0.3 0.4 V Open Pin Detection Hysteresis VUVP3(HYS) − 10 − mV VFault(OVP) 2.79 3.00 3.21 RESTART Restart Threshold Ratio Restart Threshold Restart Input Pull Down Current VRestart = VUVP3 FAULT INPUT Overvoltage Protection (OVP) Threshold VFault increasing V Delay Before Fault Confirmation Used for OVP Detection Used for OTP Detection VFault increasing VFault decreasing tdelay(OVP) tdelay(OTP) 22.5 22.5 30.0 30.0 37.5 37.5 Overtemperature Protection (OTP) Threshold VFault decreasing VFault(OTP_in) 0.38 0.40 0.42 V OTP Exiting Threshold (B/D Versions) VFault increasing VFault(OTP_out) 0.874 0.920 0.966 V ms OTP Blanking Delay During Start−Up OTP Pull−Up Current Source Fault Input Clamp Voltage tblank(OTP) 4 5 6 ms VFault = VFault(OTP_in) + 0.2 V IFault(OTP) 43 46 49 mA VFault = open VFault(clamp) 1.15 1.7 2.25 V RFault(clamp) 1.32 1.55 1.78 kW Fault Input Clamp Series Resistor PFCOK SIGNAL PFCOK Output Voltage IPFCOK = −5 mA VPFCOK 4.75 5.00 5.25 V PFCOK Low State Output Voltage IPFCOK = 5 mA VPFCOK(low) – – 250 mV Thermal Shutdown Temperature increasing TSHDN – 150 – °C Thermal Shutdown Hysteresis Temperature decreasing TSHDN(HYS) – 50 – °C THERMAL SHUTDOWN Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 11 NCP1615 DETAILED OPERATING DESCRIPTION • Standby Mode Input: allows the downstream converter INTRODUCTION The NCP1615 is designed to optimize the efficiency of your PFC stage throughout the load range. In addition, it incorporates protection features for rugged operation. More generally, the NCP1615 is ideal in systems where cost effectiveness, reliability, low standby power and high efficiency are the key requirements: • Current Controlled Frequency Foldback: the NCP1615 operates in Current Controlled Frequency Foldback (CCFF). In this mode, the circuit operates in classical Critical conduction Mode (CrM) when the inductor current exceeds a programmable value. When the current falls below this preset level, the NCP1615 linearly reduces the operating frequency down to a minimum of about 26 kHz when the input current reaches zero. CCFF maximizes the efficiency at both nominal and light load. In particular, standby losses are reduced to a minimum. Similar to frequency clamped CrM controllers, internal circuitry allows near−unity power factor at lower output power. • Skip Mode: to further optimize the efficiency, the circuit skips cycles near the line zero crossing when the current is very low. This is to avoid circuit operation when the power transfer is particularly inefficient at the cost of input current distortion. When superior power factor is required, this function can be inhibited by offsetting the FFcontrol pin by 0.75 V. • Integrated High Voltage Start−Up Circuit (Versions C and D): Eliminates the need of external start−up components. It is also used to discharge the input filter capacitors when the line is removed. • Integrated X2 Capacitor Discharge: reduces input power by eliminating external resistors for discharging the input filter capacitor. • PFCOK signal: the PFCOK pin is used to disable/enable the downstream converter. This pin is internally grounded when a fault is detected or when the PFC output voltage is below its regulation level. • Fast Line / Load Transient Compensation (Dynamic Response Enhancer): since PFC stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start−up) may cause an excessive over or undervoltage condition. This circuit limits possible deviations from the regulation level as follows: ♦ The soft and fast Overvoltage Protections accurately limit the PFC stage maximum output voltage. ♦ The NCP1615 dramatically speeds up the regulation loop when the output voltage falls below 95.5% of its regulation level. This function is disabled during power up to achieve a soft−start. • Power Saving Mode: disables the controller and reduces the input power consumption of the system enabling very low input power applications. to inhibit the PFC drive pulses when the load is reduced. • Safety Protections: the NCP1615 permanently monitors • the input and output voltages, the MOSFET current and the die temperature to protect the system during fault conditions making the PFC stage extremely robust and reliable. In addition to the bulk overvoltage protection, the NCP1615 include: ♦ Maximum Current Limit: the circuit senses the MOSFET current and turns off the power switch if the maximum current limit is exceeded. In addition, the circuit enters a low duty−ratio operation mode when the current reaches 150% of the current limit as a result of inductor saturation or a short of the bypass/boost diode. ♦ Undervoltage Protection (UVP): this circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). This feature protects the PFC stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). ♦ Bulk Undervoltage Detection (BUV): the circuit monitors the output voltage to detect when the PFC stage cannot regulate the bulk voltage (BUV fault). When the BUV fault is detected, the control pin is gradually discharged followed by the grounding of the PFCOK pin, to disable the downstream converter. ♦ Brownout Detection: the circuit detects low ac line conditions and stops operation thus protecting the PFC stage from excessive stress. ♦ Thermal Shutdown: an internal thermal circuitry disables the gate drive when the junction temperature exceeds the thermal shutdown threshold. ♦ A latch fault input can be used to disable the controller if a fault is detected (i.e. supply overvoltage, overtemperature) ♦ A line overvoltage circuit monitors the bulk voltage and disables the controller if voltage exceeds the overvoltage level. Output Stage Totem Pole Driver: the NCP1615 incorporates a 0.5 A source / 0.8 A sink gate driver to efficiently drive most medium to high power MOSFETs. HIGH VOLTAGE START−UP CIRCUIT Versions C and D of the NCP1615 integrate a high voltage start−up circuit accessible by the HV pin. The start−up circuit is rated at a maximum voltage of 700 V. A start−up regulator consists of a constant current source that supplies current from a high voltage rail to the supply capacitor on the VCC pin (CVCC). The start−up circuit current (Istart2) is typically 12 mA. Istart2 is disabled if the http://onsemi.com 12 NCP1615 VCC pin is below VCC(inhibit). In this condition the start−up current is reduced to Istart1, typically 0.5 mA. The internal high voltage start−up circuit eliminates the need for external start−up components. In addition, this regulator reduces no load power and increase the system efficiency as it uses negligible power in the normal operation mode Once CVCC is charged to the start−up threshold, VCC(on), typically 17 V (10.5 V for versions A and B), the start−up regulator is disabled and the controller is enabled. The start−up regulator remains disabled until VCC falls below the lower supply threshold, VCC(off), typically 9.0 V, is reached. Once reached, the PFC controller is disabled reducing the bias current consumption of the IC. The controller is disabled once a fault is detected. The controller will restart next time VCC reaches VCC(on) or after all non−latching faults are removed. The supply capacitor provides power to the controller during power up. The capacitor must be sized such that a VCC voltage greater than VCC(off) is maintained while the auxiliary supply voltage is building up. Otherwise, VCC will collapse and the controller will turn off. The operating IC bias current, ICC5, and gate charge load at the drive outputs must be considered to correctly size CVCC. The increase in current consumption due to external gate charge is calculated using Equation 1. I CC(gatecharge) + f @ Q G Figure 4. CCFF Operation As illustrated in the top waveform in Figure 4, at high load, the boost stage operates in CrM. As the load decreases, the controller operates in a controlled frequency discontinuous mode. Figure 5 details CCFF operation. A voltage representative of the input current (“current information”) is generated. If this signal is higher than a 2.5 V internal reference (named “Dead−Time Ramp Threshold”), there is no deadtime and the circuit operates in CrM. If the current information signal is lower than the 2.5 V threshold, deadtime is added. The deadtime is the time necessary for the internal ramp to reach 2.5 V from the current information floor. Hence, the lower the current information is, the longer the deadtime. When the current information is 0.75 V, the deadtime is 15 ms. To further reduce the losses, the MOSFET turn on is further delayed until its drain−source voltage is at its valley. As illustrated in Figure 5, the ramp is synchronized to the drain−source ringing. If the ramp exceeds the 2.5 V threshold while the drain−source voltage is below Vin, the ramp is extended until it oscillates above Vin so that the drive will turn on at the next valley. (eq. 1) where f is the operating frequency and QG is the gate charge of the external MOSFETs. OPERATING MODE The NCP1615 PFC controller achieves power factor correction using the novel Current Controlled Frequency Foldback (CCFF) topology. In CCFF the circuit operates in the classical critical conduction mode (CrM) when the inductor current exceeds a programmable value. Once the current falls below this preset level, the frequency is linearly reduced, reaching about 26 kHz when the current is zero. http://onsemi.com 13 NCP1615 Figure 5. Dead−Time Generation CURRENT INFORMATION GENERATION HV The FFcontrol pin sources a current that is representative of the input current. In practice, IFFcontrol is built by multiplying the internal control signal (VREGUL, i.e., the internal signal that controls the on time) by the internal sense voltage (VSENSE) that is proportional to the input voltage seen on the HV pin (see Figure 6). The multiplier gain (Km of Figure 6) is four times less in high line conditions (that is when the “LLine” signal from the brownout block is in low state) so that IFFcontrol provides a voltage representative of the input current across resistor RFF placed between the FFcontrol pin and ground. The FFcontrol voltage, VFFcontrol, is representative of the current information. Control Brown−out and Line Range Detection V to I Converter ISENSE IREGUL = K*V REGUL + ISENSE IREGUL SUM LLline RAMP FFcontrol Km *I REGUL*I SENSE Vskip(in)/ Vskip(out) Multiplier PFC_OK SKIP Figure 6. Generation of the Current Information in the NCP1615 http://onsemi.com 14 NCP1615 SKIP MODE function can be inhibited offsetting the FFcontrol pin by 0.75 V. The skip mode capability is disabled whenever the PFC stage is not in nominal operation represented by the PFCOK signal. The circuit does not abruptly interrupt the switching when VFFcontrol falls below Vskip(in). Instead, the signal VTON that controls the on time is gradually decreased by grounding the VREGUL signal applied to the VTON processing block shown in Figure 11. Doing so, the on time smoothly decays to zero in 3 to 4 switching periods typically. Figure 7 shows the practical implementation of the FFcontrol circuitry. As illustrated in Figure 6 the circuit also skips cycles near the line zero crossing where the current is very low and subsequently the voltage across RFF is low. A comparator monitors VFFcontrol and inhibits the switching operation when VFFcontrol falls below the skip level, Vskip(in), typically 0.65 V. Switching resumes when VFFcontrol exceeds the skip exit threshold, Vskip(out), typically 0.75 V (100 mV hysteresis). This function disables the driver to reduce power dissipation when the power transfer is particularly inefficient at the expense of slightly increased input current distortion. When superior power factor is needed, this Ramp For DT Control Zero Current Detection DRV 200 us delay (watchdog) Dead−time (DT) Detection DT S Q DRV SUM S Q R DRV CS / ZCD R Vzcd(th) FFcontrol TimeOut delay S CLK Q R DRV Clock Generation 2.5 V Figure 7. CCFF Practical Implementation CCFF maximizes the efficiency at both nominal and light load. In particular, the standby losses are reduced to a minimum. Also, this method avoids that the system stalls or jumps between drain voltage valleys. Instead, the circuit acts so that the PFC stage transitions from the n valley to (n + 1) valley or vice versa from the n valley to (n − 1) cleanly as illustrated by Figure 8. Figure 8. Valley Transitions Without Valley Jumping http://onsemi.com 15 NCP1615 ON TIME MODULATION One can show that the ac line current is given by: ƪ Let’s analyze the ac line current absorbed by the PFC boost stage. The initial inductor current at the beginning of each switching cycle is always zero. The coil current ramps up when the MOSFET is on. The slope is (Vin/L) where L is the coil inductance. At the end of the on time period (t1), the inductor starts to demagnetize. The inductor current ramps down until it reaches zero. The duration of this phase is (t2). In some cases, the system enters then the dead−time (t3) that lasts until the next clock is generated. t 1ǒt 1 ) t 2Ǔ I in + V in 2TL ƫ (eq. 2) Where T = (t1 + t2 + t3) is the switching period and Vin is the ac line rectified voltage. In light of this equation, we immediately note that Iin is proportional to Vin if [t1*(t1 + t2)/T] is a constant. Figure 9. PFC Boost Converter (left) and Inductor Current in DCM (right) The NCP1615 operates in voltage mode. As portrayed by Figure 10, t1 is controlled by the signal VTON generated by the regulation block and an internal ramp as follows: t1 + C ramp @ V TON Where ton(MAX) is the maximum on time obtained when VREGUL is at its maximum level, VREGUL(MAX). The parametric table shows that ton(MAX) is equal to 25 ms (tON(LL)) at low line and to 6.3 ms (ton(HL)) at high line. Hence, we can rewrite the above equation as follows: (eq. 3) I ch The charge current is constant at a given input voltage (as mentioned, it is four times higher at high line compared to its value at low line). Cramp is an internal timing capacitor. The output of the regulation block, VControl, is linearly transformed into the signal VREGUL varying between 0 and 1.5 V. VREGUL is the voltage that is injected into the PWM section to modulate the MOSFET duty ratio. The NCP1615 includes circuitry that processes VREGUL to generate the VTON signal that is used in the PWM section (see Figure 11). It is modulated in response to the deadtime sensed during the precedent current cycles, that is, for a proper shaping of the ac line current. This modulation leads to: V TON + T @ V REGUL I in + 2@L I in + V in @ t on(HL) P in(ave) + T ƪ V REGUL V REGUL(MAX) V in,rms 2 @ t on(LL) @ V REGUL 2 @ L @ V REGUL(MAX) V in,rms 2 @ t on(HL) @ V REGUL 2 @ L @ V REGUL(MAX) P in(MAX) + V in,rms 2 @ t on(LL) 2@L The maximum power at high line is given by the equation below: I in + k @ V in, k + constant + 2@L @ Hence, the maximum power that can be delivered by the PFC stage at low line is given by equation below: + V REGUL Given the low regulation bandwidth of the PFC systems, VControl and thus VREGUL are slow varying signals. Hence, the (Vton*(t1 + t2)/T) term is substantially constant. Provided that during t1 it is proportional to VTON, Equation 2 leads to: where k is a constant. V REGUL(MAX) The input power at high line is shown below: P in(ave) + ǒt 1 ) t 2Ǔ V REGUL From these equations, we can deduce the expression of the average input power at low line as shown below: or V TON @ @ at low line. (eq. 4) t1 ) t2 V in @ t on(LL) P in(MAX) + ƫ V in,rms 2 @ t on(HL) 2@L The input current is then proportional to the input voltage resulting in a properly shaped ac line current. V REGUL 1 @ @t 2L V REGUL(MAX) on(MAX) http://onsemi.com 16 NCP1615 One can note that this analysis is also valid in CrM operation. This condition is just a particular case of this functioning where (t3 = 0), which leads to (t1 + t2 = T) and (VTON = VREGUL). That is why the NCP1615 automatically adapts to the conditions and transitions from DCM to CrM (and vice versa) without power factor degradation and without discontinuity in the power delivery. Ich closed when output low PWM Comparator Turns off MOSFET VTON Cramp Vton ramp voltage PWM output Figure 10. PWM Circuit and Timing Diagram Internal timing saw−tooth PWM Comparator to PWM latch V TON OA1 V REGUL R1 C1 S3 STOP IN1 −>VTON during (t1+t2) −>0 V During t3 (dead−time) −>VTON*(t1+t2)/T in average OCP S1 The integrator OA1 amplifies the error between VREGUL and IN1 so that on average, VTON*t1+t2)/T) equates VREGUL. S2 DT (high during dead−time) Figure 11. VTON Processing Circuit REGULATION BLOCK AND LOW OUTPUT VOLTAGE DETECTION It is important to note that the “VTON processing circuit” compensates for long interruption of the driver activity by grounding the VTON signal as shown in Figure 11. Long driver interruptions are represented by the STOP signal. Such faults (excluding OCP) are BUV_fault, OVP, BONOK, OverStress, SKIP, staticOVP, Fast−OVP, RestartNOK and OFF mode. Otherwise, a long off time will be interpreted as normal deadtime and the circuit would over dimension VTON to compensate it. Grounding the VTON signal leads to a short soft−start period due to ramp up of VTON. This helps reduce the risk of acoustic noise. A transconductance error amplifier (OTA) with access to the inverting input and output is provided. Access to the inverting input is provided by the FB pin and the output is accessible through the Control pin. The OTA features a typical transconductance gain, gm, of 210 mS. The amplifier source and sink currents, IEA(SRC) and IEA(SNK), are typically 20 mA. The output voltage of the PFC stage is typically scaled down by a resistors divider and fed into the FB pin. The pin input bias current is minimized (less than 500 nA) to allow the use of a high impedance feedback network. At the same time, the bias current is enough to effectively ground the FB if the pin is open or floating. The output of the error amplifier is brought to the Control pin for external loop compensation. The compensation network on the Control pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle and provide adequate phase boost. Typically a type 2 network is used, to set the VOLTAGE REFERENCE A transconductance error amplifier regulates the PFC output voltage, Vbulk, by comparing the PFC feedback signal to an internal reference voltage, VREF. The feedback signal is applied to the inverting input and the reference is connected to the non−inverting input of the error amplifier. A resistor divider scales down Vbulk to generate the PFC feedback signal. VREF is trimmed during manufacturing to achieve an accuracy of ± 2.4%. http://onsemi.com 17 NCP1615 regulation bandwidth below about 20 Hz and to provide a decent phase boost. The minimum control voltage, VControl(MIN) is typically 0.5 V and it is set by an internal diode drop or VF. maximum control voltage, VControl(MAX) is typically 4.5 V. Therefore, the VControl swing is 4 V. VControl is offset down by a VF and Fast−OVP Comparator fastOVP UVP2 UVP UVP Comparator SoftOVP Soft−OVP Comparator VSOVP STOP BO_NOK PFC_OK VDD PFC_OK VDRE DRE IFB(bias) Error Comparator Amplifier Control + V − REF V REGUL VDD Iboost(startup) VUVP1 Iboost(DRE) VFOVP FB scaled down by a resistor divider before it connects to the “VTON processing block” and the PWM section as shown in Figure 12. The output of the regulation block is a signal (“VREGUL” of the block diagram) that varies between 0 and a maximum value corresponding to the maximum on−time. V REGUL(MAX) 0.5V Bottom Clamp V DD Regulation Detector ICONTROL(BO) OFF 4V In_Regulation 0.5 V StaticOVP (0.5V bottom clamp 3R is activated) VREGUL V Control + 0.5 V − Vf Vf + 4 V R Figure 12. Regulation Block Diagram (left) Correspondence Between Vcontrol and VREGUL (right) controls the on time is gradually decreased by grounding the VREGUL signal applied to the VTON processing block as shown in Figure 11. Doing so, the on time smoothly decays to zero in 3 to 4 cycles. If the output voltage keeps increasing, the Fast Overvoltage Protection (FOVP) comparator immediately disables the driver when the output voltage exceeds 107% of its desired level. The Undervoltage (UVP) Comparator monitors the FB voltage and disables the PFC stage if the bulk voltage falls below 12% of its regulation level. Once an undervoltage fault is detected, the PFCOK signal goes low to disable the downstream converter and the control capacitor is grounded. The Bulk Undervoltage Comparator (BUV) monitors the bulk voltage and disables the controller if the BUV voltage falls below the BUV threshold. The BUV threshold is a ratio of VREF and it is given by KBUV/VREF, typically 76% of VREF. Once a BUV fault is detected the controller is disabled and the PFCOK signal goes low. The Control capacitor is slowly discharged until it falls below the skip level. The discharge delay forces a minimum off time for the downstream converter. Once the discharge phase is complete the circuit may attempt to restart if VCC is above VCC(on). Otherwise, it will restart at the next VCC(on). The BUV fault is blanked while the PFCOK signal is low (i.e. during start−up) to allow a correct start−up sequence. Given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or undershoots. The NCP1615 embeds a “dynamic response enhancer” circuitry (DRE) that limits output voltage undershoots. An internal comparator monitors the FB pin and if its voltage falls below 95.5% of its nominal value, it enables a pull−up current source, Iboost(DRE), to increase the Control voltage by charging the compensation network and bring the system into regulation. The total current sourced from the Control Pin during DRE, IControl(DRE), is typically 220 mA. This effectively appears as a 10x increase in the loop gain. For versions A and B, Iboost(DRE) is disabled until the PFCOK signal goes high. The slow and gradual charge of the Control capacitor during power up softens the start−up sequence effectively achieving a soft−start. For versions C and D, a reduced current source, Iboost(start−up) (typically 80 mA), is enabled to speed up the start−up sequence and achieve a faster start−up time. Iboost(start−up) is disabled when faults (i.e. Brownout) are detected. Voltage overshoots are limited by the Soft Overvoltage Protection (SOVP) connected to the FB pin. The circuit reduces the power delivery when the output voltage exceeds 105% of its desired level. The NCP1615 does not abruptly interrupt the switching. Instead, the VTON signal that http://onsemi.com 18 NCP1615 for zero current detection (ZCD). This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the inductor voltage. Figure 14 shows the ZCD winding arrangement. A dedicated comparator monitors the FB voltage to detect the presence of a line overvoltage (LOVP) fault. The line overvoltage threshold, VFB(LOVP), is typically 112.5%. A timer, tLOVP(blank), typically 50 ms, blanks the line detect signal to prevent false detection during line transients and surge. Once a line OVP fault is detected the converter is latched. The input to the Error Amplifier, the soft-OVP, line OVP, UVP and DRE Comparators is the FB pin. The table below shows the relationship between the nominal output voltage, Vout(NOM), and the DRE, soft-OVP, Fast-OVP, line OVP and UVP levels. Parameter PFC Inductor Vout(NOM)*105% UVP Vout(NOM)*12% Fast−OVP Vout(NOM)*107% Line−OVP Vout(NOM)*112.5% Rsense RZCD2 The ZCD winding voltage, VZCD, is positive while the PFC Switch is off and the inductor current decays to zero. VZCD drops to and rings around zero volts once the inductor is demagnetized. The ZCD winding voltage is applied through a diode, DZCD, to prevent this signal from distorting the current sense information during the on time. Therefore, the overcurrent protection is not impacted by the ZCD sensing circuitry. As illustrated in Figure 13, an internal ZCD Comparator monitors the CS/ZCD voltage, VCS/ZCD. The start of the demagnetization phase is detected (signal ZCD is high) once VCS/ZCD exceeds the ZCD arming threshold, VZCD(rising), typically 750 mV. This comparator is able to detect ZCD pulses with a duration longer than 200 ns. When VCS/ZCD drops below the lower or trigger ZCD threshold, VZCD(falling), the end of the demagnetization phase is detected and the driver goes high within 200 ns. When a ZCD signal is not detected during start−up or during the off time, an internal watchdog timer, toff1, initiates the next drive pulse. The watchdog timer duration is typically 200 ms. Once the watchdog timer expires the circuit senses the impedance at the CS/ZCD pin to detect if the pin is shorted and disable the controller. The CS/ZCD external components must be selected to avoid false fault detection. The recommended minimum impedance connected to the CS/ZCD pin is 3.9 kW. Practically, RCS in Figure 14 must be higher than 3.9 kW. ICS/ZCD2 ICS/ZCD1 VDD LEB t OCP(LEB) Current Limit Comparator + VOCP − DRV LEB t OVS(LEB) DRV Detection of excessive current RZCD1 Figure 14. ZCD Winding Implementation The NCP1615 combines the PFC current sense and zero current detectors (ZCD) in a single input terminal, CS/ZCD. Figure 13 shows the circuit schematic of the current sense and ZCD detectors. DRV − CS/ZCD CURRENT SENSE AND ZERO CURRENT DETECTION t off1 PFC Switch RCS Vout(NOM)*95.5% Soft−OVP PFC Output Voltage DRV Vout(NOM) DRE Threshold CS/ZCD D ZCD Symbol/Value Nominal Output Voltage VDD + + VZCD − + Recitied ac line voltage − OCP OverStress ZCD Comparator ZCD +V ZCD(rising)/ − V ZCD(falling) Figure 13. PFC Current Sense and ZCD Detectors Schematic Current Sense The PFC Switch current is sensed across a sense resistor, Rsense, and the resulting voltage ramp is applied to the CS/ZCD pin. The current signal is blanked by a leading edge blanking (LEB) circuit. The blanking period eliminates the leading edge spike and high frequency noise during the switch turn−on event. The LEB period, tOCP(LEB), is typically 200 ns. The Current Limit Comparator disables the driver once the current sense signal exceeds the overcurrent threshold, VOCP, typically 0.5 V. POWER SAVING MODE Versions C and D of the NCP1615 has a low current consumption mode known as power saving mode (PSM). The supply current consumption in this mode is below 100 mA. PSM operation is controlled by an external control signal. This signal is typically generated on the secondary side of the power supply and fed via an optocoupler. PFC Zero Current Detection The CS pin is also designed to receive a signal from an auxiliary winding to detect the inductor demagnetization or http://onsemi.com 19 NCP1615 The NCP1615 enters PSM in the absence of the control signal. The control signal is applied to the PSTimer pin. The block diagram is shown in Figure 15. Power saving mode operating waveforms are shown in Figure 16. The NCP1615 controller starts once VCC reaches VCC(on) and no faults are present. The PSTimer pin is held at ground until the PFCOK signal goes high. This ensures the time to enter PSM is always constant. Once the PFCOK signal goes high, the current source on the PSTimer pin, IPSTimer1, is enabled. IPSTimer1 is typically 5.9 mA. The current source charges the capacitor connected from this pin to ground. Once VPSTimer reaches VPSTimer2 a 2nd current source, IPSTimer2, is enabled to speed up the charge of CPSM. VPSTimer2 and IPSTimer2 are typically 1 V and 1 mA, respectively. The controller enters PSM if the voltage on this exceeds, VPS_in, typically 3.5 V. An external optocoupler or switch needs to pull down on this pin before its voltage reaches VPS_in to prevent entering PSM. IPSTimer is disabled once the controller enters PSM. A resistor between this pin and ground discharges the PSTimer capacitor. The controller exits PSM once VPSTimer drops below VPS_out, typically 0.5 V. At this time the start−up circuit is enabled to charge VCC up to VCC(on). Once VCC charges to VCC(on) the capacitor on the PSTimer pin is discharged with an internal pull down transistor. The transistor is disabled once the PFCOK signal goes high. The time to enter PSM mode is calculated using Equations 3 through 7. The time to exit PSM mode is calculated using Equation 8. t PSM(in) + t PSM(in1) ) t PSM(in2) ǒ V DD V DD − V PS_in/ + V PS_out Ǔ V PS_in (eq. 8) During PSM, the start−up circuit on the HV pin maintains VCC above VCC(off). The input filter capacitor discharge circuitry continues operation in PSM. The supply voltage is maintained in PSM by enabling the HV pin start−up circuit once VCC falls below VCC(PS_on) (typically 11 V) and VHV is at its minimum value as detected by the valley detection circuitry. The start−up circuit current in PSM is increased to Istart2, typically 12 mA, to reduce the time the start−up circuit is on and thus a lower voltage on the HV pin. The start−up circuit is disabled once VCC exceeds VCC(PS_on). A voltage offset is observed on VCC while the start−up circuit is enabled due to the capacitor ESR. This will cause the start−up circuit to turn off because VCC exceeds VCC(PS_on). Internal circuitry prevents the start−up circuit from turning on multiple times on the same ac line half−cycle. The start−up circuit will turn on the next half−cycle. Eventually, VCC will be regulated several millivolts below VCC(PS_on). The offset is dependent on the capacitor ESR. This architecture enables the start−up circuit for the exact amount of time needed to regulate VCC. This results in a significant reduction in power dissipation because the average input voltage during which the start−up circuit is on is greatly reduced. Figure 16 shows operating waveforms while in PSM. Ǔ I PSTimer2 Ǔ V PS_out + Power Saving Mode Detector ǒ I PSTimer1 * R PSM In PSM In PSM I PSTimer2 * R PSM t PSM(out) + −R PSMC PSM @ ln (eq. 6) t PSM(in1) [ −R PSMC PSM @ ln 1 * V PSTimer2 ǒ t PSM(in2) [ −R PSMC PSM @ ln 1 * (eq. 5) V PSTimer2 (eq. 7) V PS_in * V PSTimer2 In PSM I PSTimer1 PSTimer RPSM Initial Discharge CPSM − PFCok Figure 15. NCP1615 Power Saving Mode Control Block Diagram http://onsemi.com 20 PSM Control NCP1615 Figure 16. Power Saving Mode Operating Waveforms BYPASS/BOOST DIODE SHORT CIRCUIT AND INRUSH CURRENT PROTECTION Since the NCP1615 maintains the VCC pin at VCC(PS_on) during PSM, the current consumption of the downstream converter can have an undesirable impact to power consumption. A simple mechanism to disconnect the supply voltage to the downstream converter during PSM is shown in Figure 17. VCC VCC PFC Converter It may be possible to turn on the MOSFET while a high current flows through the inductor. Examples of this condition include start−up when large inrush current is present to charge the bulk capacitor. Traditionally, a bypass diode is generally placed between the input and output high−voltage rails to divert this inrush current. If this diode is accidentally shorted or damaged, the MOSFET will operate at a minimum on time but the current can be very high causing a significant temperature increase. The NCP1615 operates in a very low duty ratio to reduce the MOSFET temperature and protect the system in this “Over Stress” condition. This is achieved by disabling the drive signal if the VZCD(rising) threshold is reached during the MOSFET conduction time. In this condition, a latch is set and the “OverStress” signal goes high. The driver is then disabled for a period determined by the overstress watchdog timer, toff2, typically 1 ms. This longer delay leads to a very low duty−ratio operation to reduce the risk of overheating. This operation also protects the system in the event of a boost diode short. Downstream PFCok Converter Enable Figure 17. Downstream Converter Supply Removal Circuit http://onsemi.com 21 NCP1615 D1 Vout Vin Q1 ACin CBULK DRV C IN ZCD Comparator ZCD signal for valley detection and CCFF LEB tOVS(LEB) Rsense D ZCD S VZCD(rising)/ VZCD(falling) RCS Overstress watchdog timer (toff2) DRV CS/ZCD R Current Limit Comparator VOCP RZCD1 OverStress OCP LEB tOCP(LEB) RZCD2 Q Figure 18. Current Sense and Zero Current Detection Blocks PFCOK SIGNAL zero. The start−up phase is then complete and the PFCOK signal goes high until a fault is detected. Another signal considered before setting the PFCOK signal is the BUV. The PFCOK signal will remain low until the bulk voltage is above the undervoltage threshold. The PFCOK signal will go low if the bulk voltage drops below its undervoltage threshold. The PFCOK pin provides a dedicated 5 V reference when the PFC stage is in regulation. The pin is internally grounded during the following conditions: • During Start−Up: It remains low until the output voltage achieves regulation and the voltage stabilizes at the right level. • Low Output Voltage: If the PFC stage output voltage is below the bulk undervoltage (BUV_Fault) level, this is indicative of a fault. The PFCOK signal then provides a means to disable and protect the downstream converter. • Brownout fault is detected (after discharge of control capacitor). • Low supply voltage: VCC falls below VCC(off). • Feedback undervoltage fault. • Fault condition: A fault detected through the Fault pin. • Open FB pin. • Thermal Shutdown. • Line voltage removal. The circuit schematic of the PFCOK block is shown Figure 19. BROWNOUT DETECTION The HV pin provides access to the brownout and line voltage detectors. It also provides access to the input filter capacitor discharge circuit. The brownout detector detects main interruptions and the line voltage detector determines the presence of either 110 V or 220 V ac mains. Depending on the detected input voltage range device parameters are internally adjusted to optimize the system performance. Line and neutral are diode “ORed” before connecting to the HV pin as shown in Figure 20. The diodes prevent the pin voltage from going below ground. A low value resistor in series with the diodes can be used for protection. A low value resistor is needed to reduce the voltage offset while sensing the line voltage. In_Regulation S OVLflag OFF Line_OVP BUV_fault Q Dominant Reset Latch Q R AC IN PFC_OK EMI FILTER HV PFCOK Controller Figure 19. PFCOK Circuit Schematic Figure 20. High−Voltage Input Connection The PFCOK circuit monitors the current sourced by the OTA. The OTA current reaches zero when the output voltage has reached its nominal level. This is represented in the block diagram by the “In_Regulation” Signal. The PFCOK signal goes high when the current reaches zero or falls below The controller is enabled once VHV is above the brownout threshold, VBO(start), typically 111 V, and VCC reaches VCC(on). Figure 21 shows typical power up waveforms. http://onsemi.com 22 NCP1615 Figure 21. Start−Up Timing Diagram set long enough to ignore a single cycle dropout. The timer ramp starts charging once VHV drops below VBO(stop). Figure 22 shows brownout detector waveforms during line dropout. A timer is enabled once VHV drops below its disable threshold, VBO(stop), typically 99 V. The controller is disabled if VHV doesn’t exceed VBO(stop) before the brownout timer expires, tBO, typically 54 ms. The timer is http://onsemi.com 23 NCP1615 Figure 22. Brownout Operation During Line Dropout LINE RANGE DETECTOR the high line select threshold for longer than the low to high line timer, tdelay(line), typically 300 ms as long as it was not previously in high line mode. If the controller has switched to “low line” mode, it is prevented from switching back to “high line” mode until the valley detection circuit detects 8 valleys, even if tdelay(line) has expired. The timer and logic is included to prevent unwanted noise from toggling the operating line level. In “high line” mode the high to low line timer, tline, (typically 54 ms) is enabled once VHV falls below Vlineselect(LL), typically 236 V. It is reset if VHV exceeds Vlineselect(LL). The controller switches back to “low line” mode if the high to low line timer expires. Figures 23 and 24 show operating waveforms of the line detector circuit. The input voltage range is detected based on the peak voltage measured at the HV pin. The line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications. Discrete values are selected for the PFC stage gain (feedforward) depending on the input voltage range. The controller compares VHV to the high line select threshold, Vlineselect(HL), typically 250 V. Once VHV exceeds Vlineselect(HL), the PFC stage operates in “high line” (Europe/Asia) or “220 Vac” mode. In high line mode the loop gain is divided by four (the internal PWM ramp slope is four times steeper). The default power−up mode of the controller is low line. The controller switches to “high line” mode if VHV exceed http://onsemi.com 24 NCP1615 Figure 23. Line Detector Timing Waveforms Figure 24. Valley Counter Operation http://onsemi.com 25 NCP1615 • • • • OUTPUT DRIVE SECTION A brownout fault is detected. The controller enters skip mode (see block diagram) A bulk undervoltage fault is detected. The controller enters latch mode. Generally speaking, the circuit turns off when the conditions are not proper for desired operation. In this mode, the controller stops operation and most of the internal circuitry is disabled to reduce power consumption. Below is description of the IC operation in off mode: • The driver is disabled. • The controller maintains VCC between VCC(on) and VCC(off). • The following blocks or features remain active: ♦ Brownout detector. ♦ Thermal shutdown. ♦ The undervoltage protection (“UVP”) detector. ♦ The overvoltage latch input remains active • VControl is grounded to ensure a controlled start−up sequence once the fault is removed. • The PFCOK pin is internally grounded. • The output of the “VTON processing block” is grounded. The NCP1615 incorporates a large MOSFET driver. It is a totem pole optimized to minimize the cross conduction current during high frequency operation. It has a high drive current capability (−500/+800 mA) allowing the controller to effectively drive high gate charge power MOSFET. The device maximum supply voltage, VCC(MAX), is 30 V. Typical high voltage MOSFETs have a maximum gate voltage rating of 20 V. The driver incorporates an active voltage clamp to limit the gate voltage on the external MOSFETs. The voltage clamp, VDRV(high), is typically 12 V with a maximum limit of 14 V. The gate driver is kept in a sinking mode whenever the controller is disabled. This occurs when the Undervoltage Lockout is active or more generally whenever the controller detects a fault and enters off mode (i.e., when the “STDWN” signal of the block diagram is high). OFF MODE The controller is disabled and in a low current mode if any of the following faults are detected: • Low supply input voltage. An undervoltage (or UVLO) fault is detected if VCC falls below VCC(off). • Thermal shutdown is activated due to high die temperature. http://onsemi.com 26 NCP1615 SYSTEM FAILURE DETECTION normally used for detecting an overtemperature fault. The controller operates normally while the Fault pin voltage is maintained within the upper and lower fault thresholds. Figure 25 shows the architecture of the Fault input. The lower fault threshold is intended to be used to detect an overtemperature fault using an NTC thermistor. A pull up current source IFault(OTP), (typically 45.5 mA) generates a voltage drop across the thermistor. The resistance of the NTC thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. The controller detects a fault once the thermistor voltage drops below VFault(OTP_in). Versions A and C latch-off the controller after an overtemperature fault is detected. In versions B and D the controller is re-enabled once the fault is removed such that VFault increases above VFault(OTP_out) and VCC reaches VCC(on). Figure 26 shows typical waveforms related to the latch version where−as Figure 27 shows waveforms of the auto-recovery version. An active clamp prevents the Fault pin voltage from reaching the upper latch threshold if the pin is open. To reach the upper threshold, the external pull-up current has to be higher than the pull-down capability of the clamp (set by RFault(clamp) at VFault(clamp)). The upper fault threshold is intended to be used for an overvoltage fault using a Zener diode and a resistor in series from the auxiliary winding voltage, VAUX. The controller is latched once VFault.exceeds VFault(OVP). The Fault input signal is filtered to prevent noise from triggering the fault detectors. Upper and lower fault detector blanking delays, tdelay(OVP) and tdelay(OTP) are both typically 30 ms. A fault is detected if the fault condition is asserted for a period longer than the blanking delay. The controller bias current is reduced during power up by disabling most of the circuit blocks including IFault(OTP). This current source is enabled once VCC reaches VCC(on). A bypass capacitor is usually connected between the Fault and GND pins and it will take some time for VFault to reach its steady state value once IFault(OTP) is enabled. To prevent false detection of an OTP fault during power up, a dedicated timer, tblank(OTP), blanks the OTP signal during power up. The tblank(OTP), duration is typically 5 ms. In versions B and D, IFault(OTP) remains enabled while the lower fault is present independent of VCC in order to provide temperature hysteresis. IFault(OTP) is disabled once the fault is removed. The controller can detect an upper fault (i.e. overvoltage) once VCC exceeds VCC(reset). Once the controller is latched, it is reset if a brownout condition is detected or if VCC is cycled down to its reset level, VCC(reset). In the typical application these conditions occur only if the ac voltage is removed from the system. The internal latch also resets once the controller enters power saving mode. Prior to reaching VCC(reset) Vfault(clamp) is set at 0 V. When manufacturing a power supply, elements can be accidentally shorted or improperly soldered. Such failures can also occur as the system ages due to component fatigue, excessive stress, soldering faults, or external interactions. In particular, a pin can be grounded, left open, or shorted to an adjacent pin. Such open/short situations require a safe failure without smoke, fire, or loud noises. The NCP1615 integrates functions that ease meeting this requirement. Among them are: • GND connection fault. If the GND pin is properly connected, the supply current drawn from the positive terminal of the VCC capacitor, flows out of the GND pin and returns to the negative terminal of the VCC capacitor. If the GND pin is disconnected, the internal ESD protection diodes provides a return path. An open or floating GND pin is detected if current flows in the CS/ZCD ESD diode. If current flow is detected for 200 ms, a fault is acknowledged and the controller stops operating. • Open CS/ZCD Pin: A pull-up current source, ICS/ZCD(bias1), on the CS/ZCD pin allows detection of an open CS/ZCD pin. ICS/ZCD1, is typically 1 mA. If the pin is open, the voltage on the pin will increase to the supply rail. This condition is detected and the controller is disabled. • Grounded CS/ZCD Pin: If the CS/ZCD pin is grounded, the circuit cannot detect a ZCD transition, activating the watchdog timer (typically 200 ms). Once the watchdog timer expires, a pull-up current source, ICS/ZCD2, sources 250 mA to pull-up the CS/ZCD pin. The driver is inhibited until the CS/ZCD pin voltage exceeds the ZCD arming threshold, VZCD(rising), typically 0.75 V. Therefore, if the pin is grounded, the voltage on the pin will not exceed VZCD(rising) and drive pulses will be inhibited. The external impedance should be above 3.9 kW to ensure correct operation. • Boost or bypass diode short. The NCP1615 addresses the short situations of the boost and bypass diodes (a bypass diode is generally placed between the input and output high-voltage rails to divert this inrush current). Practically, the overstress protection is implemented to detect such conditions and forces a low duty ratio operation until the fault is removed. FAULT INPUT The NCP1615 includes a dedicated fault input accessible via the Fault pin. The controller can be latched by pulling up the pin above the upper fault threshold, VFault(OVP), typically 3.0 V. The controller is disabled if the Fault pin voltage, VFault, is pulled below the lower fault threshold, VFault(OTP_in), typically 0.4 V. The lower threshold is http://onsemi.com 27 NCP1615 Figure 25. Fault Detection Schematic VCC VCC(on) VCC(off) Start−up initiated by VCC(on) Internal Latch Signal time Latch signal high during pre−start phase Noise spike blanked time QDRV Latch−off Switching allowed (no latch event) time Figure 26. Latch−off Function Timing Diagram http://onsemi.com 28 NCP1615 Figure 27. OTP Auto−Recovery Timing Diagram STANDBY OPERATION ADJUSTABLE BULK VOLTAGE HYSTERESIS A signal proportional to the downstream converter output power is applied to the STDBY pin to enable standby mode operation. A STDBY voltage below the standby threshold, Vstandby, typically 300 mV, forces the controller into a controlled burst mode, or standby mode. In standby mode, the driver is disabled until the bulk voltage falls below the bulk restart level. At which point, the driver is re−enabled. The bulk restart level determines the minimum bulk voltage in standby mode. As long as the STBY pin voltage is below the standby threshold, the controller will operate in controlled burst mode. The controller is not allowed to enter standby mode while the PFCOK signal is low. A dedicated timer, tblank(STDBY), blanks the standby signal for 1 ms (typically) right after the PFCOK signal transitions high. This ensures the signal proportional to the downstream converter output power has enough time to build up and prevent disabling the PFC while powering up the downstream converter. The standby circuit block is shown in Figure 28. The bulk restart threshold allows the user to enable the bulk level at which the controller exits standby mode. The restart threshold is set at 2% below the internal reference, VREF. The ratio between VREF and the restart level is given by KRestart. The user can set a restart level of 2% below the regulation level without using additional components as shown in Figure 29. If a different restart level is desired, a resistor network can be used as shown in Figure 30. STDBY Figure 29. Minimum Restart Level Configuration Vstandby S In_Regulation Q DRV Disable R Restart IRestart PFC_OK 0.98*VREF t blank(STDBY) UVP3 VUVP3 Figure 28. Standby Circuit Block http://onsemi.com 29 NCP1615 the high voltage start−up circuit to discharge the input filter capacitors upon removal of the ac line voltage. The line removal detection circuitry is always active to ensure safety compliance. The line removal is detected by digitally sampling the voltage present at the HV pin, and monitoring the slope. A timer, tline(removal) (typically 100 ms), is used to detect when the slope of the input signal is negative or below the resolution level. The timer is reset any time a positive slope is detected. Once the timer expires, a line removal condition is acknowledged initiating an X2 capacitor discharge. Once the controller detects the absence of the ac line voltage, the controller is disabled and the PFCOK signal transitions low. A second timer, tline(discharge) (typically 32 ms), is used for the time limiting of the discharge phase to protect the device against overheating. Once the discharge phase is complete, tline(discharge) is reused while the device checks to see if the line voltage is reapplied. The discharging process is cyclic and continues until the ac line is detected again or the voltage across the X2 capacitor is lower than VHV(discharge) (30 V maximum). This feature allows the device to discharge large X2 capacitors in the input line filter to a safe level. It is important to note that the HV pin cannot be connected to any dc voltage due to this feature, i.e. directly to bulk capacitor. The diodes connecting the AC line to the HV pin should be placed after the system fuse. A resistor in series with the diodes is recommended to limit the current during transient events. A low value resistor (< 3 kW) should be used to reduce the voltage drop and accurately measure the input voltage when the start−up circuit is enabled. IFB(SNK) Irestart(bias) Figure 30. Restart Level Adjustment A pull-down current source, Irestart(bias), pulls the Restart pin down to ground if it is left open. This triggers the open pin protection and disables the controller. LINE REMOVAL Safety agency standards require the input filter capacitors to be discharged once the ac line voltage is removed. A resistor network is the most common method to meet this requirement. Unfortunately, the resistor network consumes power across all operating modes and it is a major contributor of input power losses during light−load and no−load conditions. The NCP1615 eliminates the need of external discharge resistors by integrating active input filter capacitor discharge circuitry. A novel approach is used to reconfigure http://onsemi.com 30 NCP1615 VBO(start) VBO(stop) Figure 31. Line Removal Timing http://onsemi.com 31 NCP1615 VBO(start) VBO(stop) Figure 32. Line Removal Timing with AC Reapplied http://onsemi.com 32 NCP1615 VCC DISCHARGE If the downstream converter is latched due to a fault, it will require the supply voltage to be removed to reset the controller. Depending on the supply capacitor and current consumption, this may take a significant amount of time after the line voltage is removed. The NCP1615 uses the voltage at the HV pin to detect a line removal and discharge the VCC capacitor, effectively resetting the downstream converter. Immediately following the X2 discharge phase, VCC is discharged by a current sink, ICC(discharge), typically 23 mA. The current sink is disabled and the device is allowed to restart once VCC to falls down to VCC(discharge) (5 V maximum). This operation is shown in Figure 31. If the ac line is reapplied during the X2 discharge phase, the device will immediately enter the VCC discharge phase as shown in Figure 32. The device will not restart until the VCC discharge phase is completed and VCC charges to VCC(on). Figure 33. PFC FB Switch The maximum on resistance of the PFC FB Switch, RPFBswitch(on), is 10 kW. Because the PFC FB Switch is in series with R3 and R3’s value is several orders of magnitudes larger, the switch introduces minimal error on the regulation level. The off state leakage current of the PFC FB Switch, IPFBSwitch(off), is less than 3 mA. FEEDBACK DISCONNECT The PFC output voltage is typically sensed using a resistor divider comprised of R3 and R4 as shown in Figure 33. The resistor divider consumes power when the PFC stage is disabled. Versions C and D of the NCP1615 integrate a 700 V switch, PFC FB Switch, between the FBHV and FB pins. The PFC FB Switch connects in series between R3 and R4 to disconnect the resistors and reduce input power when the PFC stage is in PSM or latched mode. TEMPERATURE SHUTDOWN An internal thermal shutdown circuit monitors the junction temperature of the IC. The controller is disabled if the junction temperature exceeds the thermal shutdown threshold, TSHDN, typically 150°C. A continuous VCC hiccup is initiated after a thermal shutdown fault is detected. The controller restarts at the next VCC(on) once the IC temperature drops below below TSHDN by the thermal shutdown hysteresis, TSHDN(HYS), typically 50°C. The thermal shutdown fault is also cleared if VCC drops below VCC(reset), or if a brownout/line removal fault is detected. A new power up sequences commences at the next VCC(on) once all the faults are removed. http://onsemi.com 33 NCP1615 10.430 16.86 10.425 16.85 10.420 16.84 VCC(on) (V) VCC(on) (V) TYPICAL CHARACTERISTICS 10.415 10.410 16.82 10.405 16.81 10.400 16.80 10.395 −40 −20 0 20 40 60 80 100 16.79 −40 120 40 60 80 100 Figure 35. VCC(on) (Version C/D) vs. Temperature 120 1.4790 1.4785 1.4780 VCC(HYS) (V) 8.960 8.955 1.4775 1.4770 1.4765 8.950 1.4760 −20 0 20 40 60 80 100 1.4755 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 36. VCC(off) vs. Temperature Figure 37. VCC(HYS) (Version A/B) vs. Temperature 7.885 7.80 7.880 7.78 7.875 120 7.76 VCC(reset) (V) VCC(HYS) (V) 20 Figure 34. VCC(on) (Version A/B) vs. Temperature 8.965 7.870 7.865 7.860 7.74 7.72 7.70 7.855 7.68 7.850 7.845 −40 0 TJ, JUNCTION TEMPERATURE (°C) 8.970 8.945 −40 −20 TJ, JUNCTION TEMPERATURE (°C) 8.975 VCC(off) (V) 16.83 −20 0 20 40 60 80 100 7.66 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 38. VCC(HYS) (Version C/D) vs. Temperature Figure 39. VCC(reset) vs. Temperature http://onsemi.com 34 120 NCP1615 1.0 1.8 0.9 1.6 0.8 1.4 0.7 tstartup (ms) VCC(inhibit) (V) TYPICAL CHARACTERISTICS 0.6 0.5 0.4 0.3 1.2 1.0 0.8 0.6 0.2 0.4 0.1 0 −40 0.2 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 40. VCC(inhibit) vs. Temperature Figure 41. tstartup vs. Temperature 120 12.3 0.535 12.2 0.530 Istart2 (mA) Istart1 (mA) 12.1 0.525 0.520 12.0 11.9 11.8 0.515 11.7 0.510 −40 −20 0 20 40 60 80 100 11.6 −40 120 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 42. Istart1 (Version C/D) vs. Temperature Figure 43. Istart2 (Version C/D) vs. Temperature 20.85 0.051 20.80 0.050 20.75 0.049 20.70 0.048 20.65 ICC1 (mA) IHV(off1) (mA) −20 20.60 20.55 0.047 0.046 0.045 20.50 20.45 0.044 20.40 0.043 20.35 −40 −20 0 20 40 60 80 100 0.042 −40 120 −20 0 20 40 60 80 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 44. IHV(off1) vs. Temperature Figure 45. ICC1 vs. Temperature http://onsemi.com 35 100 120 NCP1615 0.68 0.65 0.67 0.64 0.66 0.63 ICC2b (mA) ICC2 (mA) TYPICAL CHARACTERISTICS 0.65 0.64 0.60 0.62 0.59 −20 0 20 40 60 80 100 0.58 −40 120 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) Figure 46. ICC2 vs. Temperature Figure 47. ICC2b (Version A/B) vs. Temperature 0.92 2.56 0.91 2.55 0.90 2.54 2.53 ICC4 (mA) 0.88 0.87 0.86 0.85 2.52 2.51 2.50 2.49 2.48 0.84 2.47 0.83 0.82 −40 2.46 2.45 −40 −20 0 20 40 60 80 100 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 48. ICC3 vs. Temperature Figure 49. ICC4 vs. Temperature 3.10 120 140 120 tline(removal) (ms) 3.05 3.00 2.95 2.90 2.85 −40 −20 TJ, JUNCTION TEMPERATURE (°C) 0.89 ICC3 (mA) 0.61 0.63 0.61 −40 ICC5 (mA) 0.62 100 80 60 40 20 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 50. ICC5 vs. Temperature Figure 51. tline(removal) vs. Temperature http://onsemi.com 36 120 NCP1615 TYPICAL CHARACTERISTICS 45 112.0 40 111.5 30 111.0 VBO(start) (V) tline(discharge) (ms) 35 25 110.5 20 15 110.0 10 109.5 5 0 −40 −20 0 20 40 60 80 100 109.0 −40 120 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 52. tline(discharge) vs. Temperature Figure 53. VBO(start) (Version A/B/C/D) vs. Temperature 95.0 100.8 100.6 94.8 100.4 95.2 120 100.2 94.6 100.0 VBO(stop) (V) VBO(start) (V) −20 94.4 94.2 94.0 93.8 99.8 99.6 99.4 99.2 93.6 99.0 93.4 93.2 −40 98.8 98.6 −40 −20 0 20 40 60 80 100 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 54. VBO(start) (Version C2) vs. Temperature Figure 55. VBO(stop) (Version A/B/C/D) vs. Temperature 120 10.90 87.0 86.8 10.85 86.4 VBO(HYS) (V) VBO(stop) (V) 86.6 10.80 86.2 86.0 10.75 85.8 85.6 10.70 85.4 85.2 −40 −20 0 20 40 60 80 100 10.65 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 56. VBO(stop) (Version C2) vs. Temperature Figure 57. VBO(HYS) (Version A/B/C/D) vs. Temperature http://onsemi.com 37 120 NCP1615 TYPICAL CHARACTERISTICS 8.10 250.5 250.0 8.08 249.5 249.0 Vlineselect(HL) (V) VBO(HYS) (V) 8.06 248.5 8.04 248.0 8.02 247.5 8.00 247.0 246.5 7.98 246.0 7.96 0 20 40 60 80 100 245.5 245.0 −40 120 20 40 60 80 Figure 59. Vlineselect(HL) vs. Temperature 13.7 236.5 13.6 236.0 13.5 235.5 235.0 234.5 234.0 233.5 13.4 13.3 13.2 13.1 233.0 13.0 232.5 12.9 −20 0 20 40 60 80 100 12.8 −40 120 120 100 Figure 58. VBO(HYS) (Version C2) vs. Temperature −20 0 20 40 60 80 120 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 60. Vlineselect(LL) vs. Temperature Figure 61. Vlineselect(HYS) vs. Temperature 2.5 0.30 0.25 2.0 RFBswitch(on) (kW) IFBHV(off) (mA) 0 TJ, JUNCTION TEMPERATURE (°C) 237.0 232.0 −40 −20 TJ, JUNCTION TEMPERATURE (°C) Vlineselect(HYS) (V) Vlineselect(LL) (V) 7.94 −40 −20 0.20 0.15 0.10 1.5 1.0 0.5 0.05 0 −40 −20 0 20 40 60 80 100 0 120 −40 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 62. IHVFB(off) vs. Temperature Figure 63. RFBswitch(on) vs. Temperature http://onsemi.com 38 120 NCP1615 TYPICAL CHARACTERISTICS 2.506 215.6 2.504 215.4 2.502 215.2 gm (mS) VREF (V) 2.500 2.498 2.496 2.494 214.8 2.492 214.6 2.490 2.488 −40 215.0 −20 0 20 40 60 80 100 214.4 −40 120 −20 0 20 40 60 80 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 64. VREF vs. Temperature Figure 65. gm vs. Temperature 100 120 100 120 6 2.394 2.392 5 VDRE(HYS) (mV) VDRE (V) 2.390 2.388 2.386 2.384 4 3 2 2.382 1 2.380 −20 0 20 40 60 80 100 0 −40 120 20 40 60 80 Figure 66. VDRE vs. Temperature Figure 67. VDRE(HYS) vs. Temperature 6.04 24.1 6.02 24.0 6.00 23.9 23.8 5.98 5.96 23.7 5.94 23.6 5.92 −20 0 TJ, JUNCTION TEMPERATURE (°C) 24.2 23.5 −40 −20 TJ, JUNCTION TEMPERATURE (°C) ton(HL) (ms) ton(LL) (ms) 2.378 −40 0 20 40 60 80 100 5.90 −40 −20 120 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 68. ton(LL) vs. Temperature Figure 69. ton(HL) vs. Temperature http://onsemi.com 39 120 NCP1615 TYPICAL CHARACTERISTICS 178 0.5080 176 0.5075 174 tOCP(LEB) (ns) VILIM (V) 0.5070 0.5065 0.5060 0.5055 0 20 40 60 80 100 166 160 −40 120 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 70. VILIM vs. Temperature Figure 71. tOCP(LEB) vs. Temperature 120 81 80 100 79 tOVS(LEB) (ns) 80 60 40 78 77 76 75 74 73 20 −20 0 20 40 60 80 100 72 71 −40 −20 120 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 72. tOCP(delay) vs. Temperature Figure 73. tOVS(LEB) vs. Temperature 160 70 140 60 120 50 100 tZCD (ns) 80 40 30 60 40 10 20 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 74. tOVS(delay) vs. Temperature Figure 75. tZCD vs. Temperature http://onsemi.com 40 120 80 20 0 −40 −20 TJ, JUNCTION TEMPERATURE (°C) 120 tOCP(delay) (ns) 168 162 0.5045 −40 −20 tOVS(delay) (ns) 170 164 0.5050 0 −40 172 120 NCP1615 TYPICAL CHARACTERISTICS 12.64 6.29 6.28 12.62 6.27 12.60 6.25 tDT3 (ms) tDT2 (ms) 6.26 6.24 6.23 6.22 12.56 6.21 6.20 12.54 −20 0 20 40 60 80 100 12.52 −40 120 35 30 30 25 25 20 15 60 80 5 5 20 40 60 80 100 0 −40 −20 120 120 100 120 15 10 0 100 20 10 0 20 40 60 80 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 78. tDRV(rise) vs. Temperature Figure 79. tDRV(fall) vs. Temperature 12.6 290 285 12.4 280 12.2 IFB(SNK1) (nA) VDRV(high2) (V) 40 Figure 77. tDT3 vs. Temperature 35 12.0 11.8 275 270 265 260 255 250 11.6 11.4 −40 20 Figure 76. tDT2 vs. Temperature 40 −20 0 TJ, JUNCTION TEMPERATURE (°C) 40 0 −40 −20 TJ, JUNCTION TEMPERATURE (°C) tDRV(fall) (ns) tDRV(rise) (ns) 6.19 6.18 −40 12.58 −20 0 20 40 60 80 100 245 240 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 80. VDRV(high2) vs. Temperature Figure 81. IFB(SNK1) vs. Temperature http://onsemi.com 41 120 NCP1615 TYPICAL CHARACTERISTICS 285 246 280 244 275 IFOVP/UVP(bias1) (nA) IFB(SNK2) (nA) 270 265 260 255 250 245 240 240 238 236 234 −20 0 20 40 60 80 232 −40 120 100 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 82. IFB(SNK2) vs. Temperature Figure 83. IFOVP/UVP(bias1) vs. Temperature 252 238 250 236 248 234 246 Irestart(bias) (nA) 240 232 230 228 242 240 238 224 236 −20 0 20 40 60 80 100 234 −40 120 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 84. IFOVP/UVP(bias2) vs. Temperature Figure 85. Irestart(bias) vs. Temperature 46.1 46.0 45.9 45.8 45.7 45.6 45.5 −40 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 86. IFault(OTP) vs. Temperature http://onsemi.com 42 120 244 226 222 −40 −20 TJ, JUNCTION TEMPERATURE (°C) IFault(OTP) (mA) IFOVP/UVP(bias2) (nA) 235 230 −40 242 120 120 NCP1615 PACKAGE DIMENSIONS SOIC−14 NB, LESS PIN 13 CASE 751AN−01 ISSUE A D A B 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S DETAIL A h A e DIM A A1 A3 b D E e H h L M X 45 _ M A1 C SEATING PLANE SOLDERING FOOTPRINT* 6.50 13X 1.18 1 1.27 PITCH 13X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 43 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ NCP1615 PACKAGE DIMENSIONS SOIC−16 NB, LESS PIN 15 CASE 752AC−01 ISSUE O D 16 A B 9 E H 0.25 M B M 1 8 e 15X 15X C b 0.25 C L M T A S B DIM A A1 b C D E e H h L M S A1 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. h x 45 _ A M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ SOLDERING FOOTPRINT* 6.40 15X 1 1.12 16 15X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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