PJSRV05-4, PJSRV05W-4 Low Capacitance TVS and Diode Array This diode array is configured to protect up to four data transmission lines acting as a line terminator, minimizing overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. Additionaly the TVS Device offers overvoltage transient protection between the operating voltage bus and ground plane. 4 6 3 SPECIFICATION FEATURES 1 Peak Power Dissipation of 350W 8/20µs SOT26 Maximum Capacitance of 5pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 5µA @ VRWM 4 Available in SOT23-6L and SOT363 packages 6 IEC61000-4-2, IEC61000-4-4 and IEC61000-4-5 Full Compliance 3 100% Tin Matte finish (LEAD-FREE PRODUCT) 1 SOT363 APPLICATIONS USB 2.0 and Firewire Port Protection LAN/WLAN Access Point terminals Video Signal line protection I/O3 4 3 I/O2 REF1 5 2 REF2 I/O4 6 1 I/O1 2 I C Bus Protection Touch Panel Controller lines protection Device PJSRV05-4 PJSRV05W-4 Marking Code 054 W5 MAXIMUM RATINGS Tj = 25°C Unless otherwise noted Rating Symbol Value Units Peak Pulse Power (8/20µs Waveform) P PPM 350 W Peak Pulse Current (8/20µs Waveform) I PP 20 A Operating Junction Temperature Range TJ -55 to +150 °C Storage Temperature Range Tstg -55 to +150 °C Soldering Temperature, t max = 10s TL 260 °C 9/1/2006 Page 1 www.panjit.com PJSRV05-4, PJSRV05W-4 ELECTRICAL CHARACTERISTICS Parameter Tj = 25°C unless otherwise noted Min Conditions Symbol Typical VWRM Reverse Stand-Off Voltage Max Units 5 V 6.2 Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5V 5 µA Clamping Voltage (8/20µs) Vc I pp = 3A 10 V Clamping Voltage (8/20µs) Vc I pp = 12A 15 V Clamping Voltage (8/20µs) Vc I pp = 20A 18 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and GND 4 5 pF 0 Vdc Bias f = 1MHz Between I/O pins 2 3 pF Surge Pulse Waveform Definition TVS Clamping Voltage vs Ipp 8/20µs Pulse Waveform 25 Percent of Ipp Peak Surge Current, A 30 20 15 10 TA = 25°C 5 0 8 10 12 14 16 V 18 110 100 90 80 70 60 50 40 30 20 10 0 50% of Ipp @ 20µs Rise time 10-90% - 8µs 0 20 5 10 15 20 25 30 time, µsec Clamping Voltage, V Off-State Capacitance vs Vdc @ 1MHz (L-GND) 6 Capacitance, pF 5 4 3 2 1 0 0 1 2 3 4 5 Bias Voltage, Vdc 9/1/2006 Page 2 www.panjit.com PJSRV05-4 PACKAGE DIMENSIONS TYPICAL APPLICATION CONFIGURATION D + (1) USB2.0 Port1 D - (1) Vbus + I/O3 4 3 I/O2 REF1 5 2 REF2 I/O4 6 1 I/O1 Gnd PJSRV05-4 D + (2) USB2.0 Port2 D - (2) © Copyright PanJit International, Inc 2006 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. 9/1/2006 Page 3 www.panjit.com