NCV7512 FLEXMOSt Quad Low-Side Pre-Driver The NCV7512 programmable four channel low−side MOSFET driver is one of a family of FLEXMOSTM automotive grade products used for driving logic−level MOSFETs. The product is controllable by any combination of SPI (Serial Peripheral Interface) or parallel inputs. Programmable features include optional fault recovery, shorted load detection threshold, fault retry timing, and fault masking mode. The programmable refresh time allows operation in a power−limiting PWM mode. The device offers 3.3 V / 5 V compatible logic inputs and the serial output driver can be powered from either 3.3 V or 5 V supplies. Power−on reset of the supply pin provides for a controlled power up and power down. Two enable inputs are supplied. ENA1 provides a global on/off control with a reset function for internal circuitry. ENA2 controls the output stage (during initialization). Each channel independently monitors its external MOSFET’s drain voltage for fault conditions. Shorted load fault detection thresholds are fully programmable using an externally programmed reference voltage and a combination of four discrete internal ratio values. The ratio values are SPI selectable and allow different detection thresholds for each pair of output channels. Open load fault detection threshold is a function of a percentage of the power supply voltage (VCC1). Fault information for each channel is 2−bit encoded by fault type and is available through SPI communication. The FLEXMOS family of products offers application scalability through choice of external MOSFETs. Features • • • • • • • • • • 16−Bit SPI with Frame Error Detection 3.3 V/5 V Compatible Parallel and Serial Control Inputs 3.3 V/5 V Compatible Serial Output Driver Two Enable Inputs Open−Drain Fault and Status Flags Programmable − Shorted Load Fault Detection Thresholds − Fault Recovery Mode − Fault Retry Timer − Flag Masking Load Diagnostics with Latched Unique Fault Type Data − Shorted Load − Open Load − Short to GND Scalable to Load by Choice of External MOSFET These are Pb−Free Devices* NCV Prefix for Automotive − Site and Change Control − AEC−Q100 Qualified http://onsemi.com MARKING DIAGRAM 32 LEAD LQFP FT SUFFIX CASE 873A A WL YY WW G NCV7512 AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NCV7512FTG LQFP (Pb−Free) 250 Units/Tray NCV7512FTR2G LQFP 2000 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 2 1 Publication Order Number: NCV7512/D NCV7512 IN3 IN2 IN1 IN0 ENA2 VCC2 NCV7512 CHANNEL 1 Quad Low−Side Pre−Driver POWER ON RESET & BIAS VCC1 DRN1 FAULT DETECT VSS VCC2 DRIVER ENA1 GATE SELECT GAT1 VSS FLAG MASK ENA ENA VCC2 DRN 1 2 REF DISABLE DISABLE MODE REFRESH/REF CSB PARALLEL SERIAL ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL VCC POR CSB SCLK SI SI VSS IREF 6 SCLK CHANNEL 2 CHANNEL 3 VSS IREF SPI ENA ENA VCC2 DRN 1 2 REF DISABLE 16 BIT VDD CHANNEL 4 PARALLEL SERIAL SO DRIVER VSS CH 1−2 FLTB CH 3−4 FAULT LOGIC & REFRESH TIMER GAT3 DRN4 GAT4 FAULT REFERENCE GENERATOR + FLTREF OA − 4 DRN 1:4 CLOCK MASK 1:4 GND POR N/C DRN3 VCC1 FAULT BITS N/C GAT2 VSS VCC1 8 2 VSS IREF SO DRN2 N/C N/C N/C Figure 1. Block Diagram http://onsemi.com 2 ENA 1 DRAIN FEEDBACK MONITOR N/C STAB N/C M +5V 14W UNCLAMPED LOAD VLOAD 14W 28W 5W NCV7512 RFILT CB1 +5V OR +3.3V RX1 POWER−ON RESET VCC1 VCC2 FLTREF DRN1 ENA1 GAT1 ENA2 DRN2 N/C GAT2 IN1 DRN3 IN2 GAT3 RD1 NID9N05CL 5 SPI RSPU RD3 NID9N05CL IN3 RFPU RD2 NID9N05CL IN4 4 N/C NCV7512 HOST CONTROLLER PARALLEL RX2 RST DRN4 RD4 CB2 NID9N05CL GAT4 N/C IRQ FLTB N/C I/O CSB N/C SCLK N/C SI VDD STAB SO GND VSS Figure 2. Application Diagram http://onsemi.com 3 NCV7512 PIN FUNCTION DESCRIPTION PIN Number Symbol Description 1 N/C* No Connection. 2 IN1 Channel 1 Input Parallel Control. Active High. 3 IN2 Channel 2 Input Parallel Control. Active High. 4 IN3 Channel 3 Input Parallel Control. Active High. 5 IN4 Channel 4 Input Parallel Control. Active High. 6 N/C* No Connection. 7 ENA2 Enable 2 Input. Active High. Output Driver Control and Diagnostic Circuitry. 8 ENA1 Enable 1 Input. Active High. Output Driver Control with System Reset. 9 FLTB Fault Bar Flag. Open−Drain Output. Goes Low with any Channel Open or Short Condition.** 10 CSB Chip Select Bar (SPI Control). 11 SCLK Serial Clock (SPI Control). 12 SI Serial Input (SPI Control). 13 SO Serial Output (SPI Control). 14 VDD Power Supply − Serial Output Driver. 15 STAB Status Bar Flag. Open−Drain Output. Goes Low when any DRNx is Low (FET is On).** 16 VSS Power Return (Ground) for VCC2, VDD, Drain Clamps. Isolated from GND by a Diode. 17 N/C* No Connection. 18 N/C* No Connection. 19 GAT4 Gate Drive. 20 DRN4 Drain Feedback. 21 GAT3 Gate Drive. 22 DRN3 Drain Feedback. 23 GAT2 Gate Drive. 24 DRN2 Drain Feedback. 25 GAT1 Gate Drive. 26 DRN1 Drain Feedback. 27 N/C* No Connection. 28 N/C* No Connection. 29 VCC2 Power Supply for Gate Drivers. 30 VCC1 Power Supply. Logic and Low Power Device. 31 FLTREF 32 GND Fault Detection Voltage Threshold. Ground. Power Return for VCC1. Includes Device Substrate. *True no connect. PC board traces allowable. ** Unless masked out. http://onsemi.com 4 N/C N/C GAT4 DRN4 GAT3 DRN3 GAT2 DRN2 NCV7512 24 23 22 21 20 19 18 17 GAT1 25 16 VSS DRN1 26 15 STAB N/C 27 14 VDD N/C 28 13 SO VCC2 29 12 SI VCC1 30 11 SCLK FLTREF 31 10 CSB GND 32 9 FLTB 1 2 3 4 5 6 7 8 N/C IN1 IN2 IN3 IN4 N/C ENA2 ENA1 NCV7512 Figure 3. 32 Pin LQFP Pinout (Top View) http://onsemi.com 5 NCV7512 MAXIMUM RATINGS (Voltages are with respect to device substrate.) Rating Value Unit −0.3 to 6.5 V Difference Between VCC1 and VCC2 "0.3 V Difference Between GND (Substrate) and VSS "0.3 V Output Voltage (GATx, STAB, FLTB, SO) −0.3 to 6.5 V Drain Feedback Clamp Voltage (DRNx) (Note 1) −0.3 to 40 V Drain Feedback Clamp Current (DRNx) (Note 1) 10 mA Input Voltage (ENAx, SCLK, SI, FLTREF, Inx) −0.3 to 6.5 V Junction Temperature, TJ −40 to 150 °C Storage Temperature, TSTG −65 to 150 °C Peak Reflow Soldering Temperature: Lead−Free 60 to 150 seconds at 217°C (Note 2) 260 peak °C DC Supply (VCC1, VCC2, VDD) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power dissipation is limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances. 2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and Application Note AND8003/D. 3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using a minimum width signal trace pattern (384 mm2 trace area). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 4.75 5.25 V VCC1 − 0.3 VCC1 + 0.3 V Serial Output Driver Power Supply Voltage 3.0 VCC1 V VIN High Logic Input High Voltage 2.0 VCC1 V VIN Low Logic Input Low Voltage 0 0.8 V −40 125 °C VCC1 Main Power Supply Voltage VCC2 Gate Drivers Power Supply Voltage VDD TA Ambient Still−Air Operating Temperature ATTRIBUTES Characteristic Value ESD Capability Human Body Model Machine Model w " 2.0 kV w " 200 V Moisture Sensitivity (Note 2) MSL3 Package Thermal Resistance (Note 3) Junction–to–Ambient, RqJA Junction–to–Pin, RYJL 86.0 °C/W 58.5 °C/W http://onsemi.com 6 NCV7512 ELECTRICAL CHARACTERISTICS (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 4) Conditions Characteristic Min Typ Max – – −2.3 −2.5 5.0 5.0 – −2.0 5.0 Unit VCC1 Supply Operating Current Power−On Reset Threshold VCC1 = 5.25 V, VFLTREF = 1.0 V ENAX = 0 ENA1 = ENA2 = VCC1, VDRNX = 0 V, GATX drivers off ENA1 = ENA2 = VCC1, GATX drivers on VCC1 Rising Power−On Reset Hysteresis − mA 3.65 4.20 4.60 V 0.150 0.385 – V 2.0 – – V Digital I/O VIN High ENAX, INX, SI, SCLK, CSB VIN Low ENAX, INX, SI, SCLK, CSB – – 0.8 V VIN Hysteresis ENAX, INX, SI, SCLK, CSB 100 330 500 mV Input Pullup Current CSB VIN = 0 V −25 −10 – mA Input Pulldown Current ENA2, INX, SI, SCLK, VIN = VCC1 Input Pulldown Resistance ENA1 SO Low Voltage VDD = 3.3 V, ISINK = 5 mA SO High Voltage VDD = 3.3 V, ISOURCE = 5 mA SO Output Resistance Output High or Low SO Tri−State Leakage Current CSB = 3.3 V STAB Low Voltage STAB Leakage Current – 10 25 mA 100 150 200 kW – 0.11 0.25 V VDD − 0.25 VDD − 0.11 – V – 22 – W −10 – 10 mA STAB Active, ISTAB = 1.25 mA – 0.1 0.25 V VSTAB = VCC1 – – 10 mA FLTB Low Voltage FLTB Active, IFLTB = 1.25 mA – 0.1 0.25 V FLTB Leakage Current VFLTB = VCC1 – – 10 mA Fault Detection – GATX ON FLTREF Input Current VFLTREF = 0 V −1.0 – – mA FLTREF Input Linear Range Guaranteed by Design 0 – VCC1 − 2.0 V FLTREF Op−amp VCC1 PSRR Guaranteed by Design 30 – – dB DRNX Clamp Voltage IDRNX = 10 mA IDRNX = ICL(MAX) = 10 mA 27 – 32 33.6 – 37 V DRNX Shorted Load Threshold GATX Output High, VFLTREF = 1.0 V Register 2: R1 = 0, R0 = 0 or R4 = 0, R3 = 0 20 25 30 % VFLTREF GATX Output High, VFLTREF = 1.0 V Register 2: R1 = 0, R0 = 1 or R4 = 0, R3 = 1 45 50 55 % VFLTREF GATX Output High, VFLTREF = 1.0 V Register 2: R1 = 1, R0 = 0 or R4 = 1, R3 = 0 70 75 80 % VFLTREF GATX Output High, VFLTREF = 1.0 V Register 2: R1 = 1, R0 = 1 or R4 = 1, R3 = 1 95 100 105 % VFLTREF −1.0 – 1.0 mA DRNX Input Leakage Current VCC1 = VCC2 = VDD = 5.0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) VCC1 = VCC2 = VDD = 0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) 4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 5. Guaranteed by design. http://onsemi.com 7 NCV7512 ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 4) Characteristic Symbol Conditions Min Typ Max Unit Fault Detection – GATX OFF DRNX Diagnostic Current DRNX Fault Threshold Voltage DRNX Off State Bias Voltage ISG Short to GND Detection, VDRNX = 0.30 VCC1 −27 −20 −10 mA IOL Open Load Detection, VDRNX = 0.75 VCC1 30 60 80 mA VSG Short to GND Detection 27 30 33 %VCC1 VOL Open Load Detection 72 75 78 %VCC1 – 50 – %VCC1 1.0 1.80 2.5 kW −5.25 – −1.9 mA 1.9 – 5.25 mA – – 1.0 – – 1.0 – – 1.40 ms – – 1.40 ms VCTR − Gate Driver Outputs GATX Output Resistance Output High or Low GATX High Output Current VGATX = 0 V GATX Low Output Current VGATX = VCC2 Turn−On Propagation Delay tP(ON) Turn−Off Propagation Delay tP(OFF) INX to GATX (Figure 4) CSB to GATX (Figure 5) INX to GATX (Figure 4) CSB to GATX (Figure 5) Output Rise Time tR 20% to 80% of VCC2, ms ms CLOAD = 400 pF (Figure 4, Note 5) Output Fall Time tF 80% to 20% of VCC2, CLOAD = 400 pF (Figure 4, Note 5) Fault Timers Channel Fault Blanking Timer tBL(ON) VDRNX = 5.0 V; INX rising to FLTB falling (Figure 6) 30 45 60 ms tBL(OFF) VDRNX = 0 V; INX falling to FLTB falling (Figure 6) 90 120 150 ms Channel Fault Filter Timer tFF Figure 7 7.0 12 17 ms Global Fault Refresh Timer (Auto−retry Mode) tFR Register 2: Bit R2 = 0 or R5 = 0 7.5 10 12.5 ms Register 2: Bit R2 = 1 or R5 = 1 30 40 50 ms ENA1 = High – 500 – kHz 3.0 3.3 3.6 V 4.5 5.0 5.5 V – 250 – ns Timer Clock Serial Peripheral Interface (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF SO Supply Voltage VDD 3.3 V Interface 5 V Interface SCLK Clock Period − Maximum Input Capacitance Sl, SCLK (Note 5) – – 25 pF SCLK High Time SCLK = 2.0 V to 2.0 V 125 – – ns SCLK Low Time SCLK = 0.8 V to 0.8 V 125 – – ns Sl Setup Time Sl = 0.8 V/2.0 V to SCLK = 2.0 V (Note 5) 25 – – ns Sl Hold Time SCLK = 2.0 V to Sl = 0.8 V/2.0 V (Note 5) 25 – – ns http://onsemi.com 8 NCV7512 ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 4) Characteristic Symbol Conditions Min Typ Max Unit Serial Peripheral Interface (continued) (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF SO Rise Time (20% VSO to 80% VDD) CLOAD = 200 pF (Note 5) – 25 50 ns SO Fall Time (80% VSO to 20% VDD) CLOAD = 200 pF (Note 5) – – 50 ns CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V (Note 5) 60 – – ns CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V (Note 5) 75 – – ns CSB to SO Time CSB = 0.8 V to SO Data Valid (Note 5) – 65 125 ns SO Delay Time SCLK = 0.8 V to SO Data Valid (Note 5) – 65 125 ns Transfer Delay Time CSB Rising Edge to Next Falling Edge (Note 5) 1.0 – – ms http://onsemi.com 9 NCV7512 DRNx INX Open Load Threshold Shorted Load Threshold 50% tP(OFF) GAT X tR 80% 50% 20% tP(ON) Figure 4. Gate Driver Timing Diagram – Parallel Input CSB 50% GX tP(OFF) GAT X 50% tP(ON) Figure 5. Gate Driver Timing Diagram – Serial Input DRNX INX 50% tBL(ON) FLTB tBL(OFF) 50% Figure 6. Blanking Timing Diagram http://onsemi.com 10 50% tF NCV7512 OPEN LOAD THRESHOLD SHORTED LOAD THRESHOLD DRNX INX tFF FLTB tFF 50% 50% Figure 7. Filter Timing Diagram GAT X tBL(ON) tFR tFF DRNX tFR tBL(ON) tFR SHORTED LOAD THRESHOLD (FLTREF) INX Figure 8. Fault Refresh Timing Diagram CSB SETUP TRANSFER DELAY CSB SI SETUP SCLK CSB HOLD 1 16 SI HOLD SI MSB IN SO DELAY CSB to SO VALID SO LSB IN BITS 14...1 MSB OUT SO RISE,FALL BITS 14...1 LSB OUT Note: Not defined but usually MSB of data just received. Figure 9. SPI Timing Diagram http://onsemi.com 11 SEE NOTE 80% VDD 20% VDD NCV7512 DETAILED OPERATING DESCRIPTION General The NCV7512 is a four channel general−purpose low−side pre−driver for controlling and protecting N−type logic level MOSFETs. While specifically designed for driving MOSFETs with resistive, inductive or lamp loads in automotive applications, the device is also suitable for industrial and commercial applications. Programmable fault detection and protection modes allow the NCV7512 to accommodate a wide range of external MOSFETs and loads providing the user with flexible application solutions. Separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. ON Semiconductor’s SmartDiscretest such as the NID9N05CL, clamp MOSFETs, and are recommended when driving unclamped inductive loads. The active−low CSB chip select bar input has a pull−up current source. The SI and SCLK inputs have pull−down current sources. The recommended idle state for SCLK is low. The tri−state SO line driver can operate in 3.3V or 5V systems. Power (3.3V or 5V) to the SO driver is applied via the device’s VDD and VSS pins. The NCV7512 employs frame error detection. Integer multiples of 16 SCLK cycles during each CSB high−low−high cycle (valid communication frame) is required for the device to recognize a command. A frame error does not affect error flag reporting. The CSB input controls SPI data transfer and initializes the selected device’s frame error and fault reporting logic. The host initiates communication when a selected device’s CSB pin goes low. The master’s SCLK signal shifts Output (fault) data MSB first from the SO pin while input (command) data is received MSB first at the SI pin (Figure 10). Fault data changes on the falling edge of SCLK and is guaranteed valid before the next rising edge of SCLK. Command data received must be valid before the rising edge of SCLK. When CSB goes low, frame error detection is initialized, latched fault data is transferred to the SPI, and the FLTB flag is disabled and reset if previously set. Faults while CSB is low are ignored, but will be captured if still present after CSB goes high. If a valid frame has been received when CSB goes high, the last multiple of 16 bits received is decoded into command data, and FLTB is re−enabled. Latched (previous) fault data is cleared and current fault data is captured. The FLTB flag will be set if a fault is detected. If a frame error is detected when CSB goes high, new command data is ignored, and previous fault data remains latched and available for retrieval during the next valid frame. The FLTB flag will be set if a fault is detected. Frame errors are ignored. They are not reported by FLTB. Power Up/Down Control The NCV7512’s power−up/down control prevents spurious output operation by monitoring the VCC1 power supply voltage. An internal Power−On Reset (POR) circuit holds all GATX outputs low until sufficient voltage is available to allow proper control of the device. All internal registers are initialized to their default states, fault data is cleared, and the open−drain fault (FLTB) and status flags (STAB) are disabled during a POR event. When VCC1 exceeds the POR threshold, the device is ready to accept input data, outputs are allowed to turn on, and fault and status reporting are accurate. When VCC1 falls below the POR threshold during power down, fault flags are reset and reporting is disabled. All GATX outputs are held low. Operation below VCC1=0.7V is not specified. SPI Communication The NCV7512 is a 16−bit SPI slave device. SPI communication between the host and the NCV7512 may either be directly addressed through CSB or daisy−chained through other devices using a compatible SPI protocol. CSB MSB SCLK SO 1 2 4 − 13 3 14 15 16 X B15 B14 B13 B12 − B3 B2 B1 B0 Z SI LSB B15 B14 B13 B12 − B3 B2 B1 B0 Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data Figure 10. SPI Communications Frame Format http://onsemi.com 12 X UKN Z NCV7512 Serial Data and Register Structure The 16−bit data received (SI) is decoded into a 4−bit address and a 6−bit data word (Figure 11). The upper four bits, beginning with the received MSB, are fully decoded to address one of four programmable registers and the lower six bits are decoded into data for the addressed register. Bit B15 must always be set to zero. Valid register addresses are shown in Table 1. The 16−bit data sent (SO) by the NCV7512 is encoded 8−bit fault information. The upper 6 bits are forced to zero and lower 2 bits are forced to zero (Figure 12). REGISTER SELECT COMMAND INPUT DATA MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 A2 A1 A0 X X X X X X D5 D4 D3 D2 D1 D0 Figure 11. SPI Input Data MSB LSB B15 B14 B13 B12 0 0 0 0 B11 B10 0 0 B9 B8 B7 CH4 B6 B5 CH3 B4 B3 CH2 B2 CH1 B1 B0 0 0 CHANNEL FAULT OUTPUT DATA Figure 12. SPI Output Data Table 1. Register Address Definitions FUNCTION TABLE ADDRESS 6−BIT INPUT DATA A2 A1 A0 D5 D4 D3 D2 0 0 0 Gate Select 0 0 1 Disable Mode 0 1 0 Refresh & Reference 0 1 1 Mask 1 0 0 Null D1 D0 OUTPUT DATA X X X 8−bit Fault Data Gate Select – Register 0 Each GATX output is turned on/off by programming its respective GX bit (Table 2). Setting a bit to 1 causes the selected GATX output to drive its external MOSFET’s gate to VCC2 (ON.) Setting a bit to 0 causes the selected GATX output to drive its external MOSFET’s gate to VSS (OFF.) Note that the actual state of the output depends on POR, ENAX and shorted load fault states as later defined by Equation 1. At power−up, each bit is set to 0 (all outputs OFF.) Disable Mode – Register 1 The disable mode for shorted load faults is controlled by each channel’s respective MX bit (Table 3). Setting a bit to 1 causes the selected GATX output to latch−off when a fault is detected. Setting a bit to 0 causes the selected GATX output to auto−retry when a fault is detected. At power−up, each bit is set to 0 (all outputs in auto−retry mode.) Table 3. Disable Mode Register Table 2. Gate Select Register A2 A1 A0 0 0 0 D5 D4 D3 D2 D1 G4 G3 G2 G1 D0 A2 A1 A0 0 0 1 D5 D4 D3 D2 D1 M4 M3 M2 M1 0 = AUTO−RETRY 1 = LATCH OFF 0 = GATX OFF 1 = GATX ON http://onsemi.com 13 D0 NCV7512 Refresh and Reference – Register 2 Refresh time (auto−retry mode) and shorted load fault detection references are programmable in two groups of two channels. Refresh time and the fault reference for channels 4−3 is programmed by RX bits 4−3. Refresh time and the fault reference for channels 2−1 is programmed by RX bits 2−1 (Table 4). At power−up, each bit is set to 0 (VFLT = 25% VFLTREF, tFR = 10 ms.) Table 4. Refresh and Reference Register A2 A1 A0 D5 D4 D3 D2 D1 D0 0 1 0 R5 R4 R3 R2 R1 R0 CHANNELS 4−3 CHANNELS 2−1 25% VFLTREF X 0 0 X 0 0 50% VFLTREF X 0 1 X 0 1 75% VFLTREF X 1 0 X 1 0 VFLTREF X 1 1 X 1 1 tFR = 10 ms X X X 0 X X tFR = 40 ms X X X 1 X X tFR = 10 ms 0 X X X X X tFR = 40 ms 1 X X X X X Flag / STAB Mask – Register 3 Using the mask feature, allows the user to disable the FLTB and STAB flag reporting on a channel by channel basis. No allowance is made to segregate control of masking Flag and Status reporting. The drain feedback from each channel’s DRNX input is combined with the channel’s KX mask bit (Table 5.) When KX=1, a channel’s mask is cleared and its feedback to the FLTB and STAB flags is enabled. At power−up, each bit is set to 0 (all masks set.) Table 6. Null Register A1 A0 0 1 1 D5 D4 D3 D2 D1 K4 K3 K2 K1 A1 A0 D5 D4 D3 D2 D1 D0 1 X X X X X X X X Gate Driver Control and Enable Each GATX output may be turned on by either its respective parallel INX input or SPI control of the internal GX (Gate Select) register bit. The device’s common ENAX enable inputs can be used to implement global control functions, such as system reset, over−voltage or input override by a watchdog controller. Each parallel input (Inx) and the ENA2 input have individual internal pull−down current sources. The ENA1 input has an internal pull−down resistor. Unused parallel inputs should be connected to GND and unused enable inputs should be connected to VCC1. Input signal frequency of PWM Inx signals should be kept less than 2 kHz. When ENA1 is brought low, all GATX outputs, the timer clock, and the flags are disabled. The fault and gate registers are cleared and the flags are reset. New serial GX data is ignored while ENA1 is low but other registers can be programmed. ENA1 provides global on/off control and provides a soft reset. ENA2 disables all GATX outputs and diagnostic circuitry when brought low. SPI control and Parallel (Inx) inputs are still recognized when ENA2 is low. ENA2 provides local on/off control and can be used to disable the GATX outputs during initialization of the NCV7512. ENA2 can also be used to PWM all outputs simultaneously at low frequencies. Table 5. Flag Mask Register A2 A2 D0 0 = MASK SET 1 = MASK CLEAR The STAB flag is influenced when a mask bit changes CLR→SET after one valid SPI frame. FLTB is influenced after two valid SPI frames. This is correct behavior for FLTB since, while a fault persists, the FLTB will be set when CSB goes LO→HI at the end of a SPI frame. The mask instruction is decoded after CSB goes LO→HI so FLTB will only reflect the mask bit change after the next SPI frame. Both FLTB and STAB require only one valid SPI frame when a mask bit changes SET→CLR. Null Register – Register 4 The null register (Table 6) provides a way to retrieve fault information without actively changing an input command (i.e. modifying DX). Fault information is always returned when any register is addressed. http://onsemi.com 14 NCV7512 Diagnostics are disabled when ENA1 or ENA2 is low. When both ENA1 and ENA2 are high, diagnostics are enabled. Shorted load faults are detected when a driver is on. Open load or short to GND faults are detected when a driver is off. On−state faults will initiate MOSFET protection behavior. The FLTB flag will be set and the respective channel’s DX fault bit is latched. Off−state faults will simply set the FLTB flag and the channel’s DX bits. Fault types are encoded in a 2−bit per channel format. Fault information for all channels is simultaneously retrieved by a SPI read (Figure 11). Table 8 shows the fault−encoding scheme for channel 0. The remaining channels are identically encoded. When both the ENA1 and ENA2 inputs are high, the outputs will reflect the current parallel and serial input states. Turning on a channel is an OR’d function of the parallel and serial inputs. The INX input state and the GX register bit data are logically combined with the internal (active low) power−on reset signal (POR), the ENAX input states, and the shorted load state (SHRTX) to control the corresponding GATX output such that: GATX + POR · ENA1 · ENA2 · SHRTx · (INx ) Gx) (eq. 1) The GATX state truth table is given in Table 7. Table 7. Gate Driver Truth Table POR ENA1 ENA2 SHRTX INX GX GATX 0 X X X X X L 1 0 0 X X X L 1 0 1 X X X L 1 1 0 X X X L 1 1 1 1 0 0 L 1 1 1 1 1 X H 1 1 1 1 X 1 H 1 1 1 0 X X L 1 1→0 1 X X →0 →L 1 1 1→0 X X GX →L 1 1 0→1 X 0 GX →GX Table 8. Fault Data Encoding CHANNEL 0 DX1 tFR R2 | R 5 MX IN X GX ENA1 ENA2 POR FILTER TIMER ENCODING LOGIC S LATCH OFF / AUTO RE−TRY _ EN R DRNX BLANKING TIMER SHRTX 50 FAULT DETECTION VSS VCC2 DRIVER VSS D0 STATUS 0 0 NO FAULT 0 1 OPEN LOAD 1 0 SHORT TO GND 1 1 SHORTED LOAD Fault Blanking and Fault Filter Timers Fault Blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. Fault Filter timers are used to suppress glitches while a channel is in a stable state. A turn−on blanking timer is started when a channel is commanded on. Drain feedback is sampled after tBL(ON). A turn−off blanking timer is started when a channel is commanded off. Drain feedback is sampled after tBL(OFF). Blanking timers for all channels are started when both ENA1 and ENA2 go high or when either ENAX goes high while the other is high. A filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. Drain feedback is sampled after tFF. Each channel has independent blanking and filter timers. The parameters for the tBL(ON), tBL(OFF), and tFF times are identical for all channels. Gate Drivers Each channels non−inverting GATX drivers are resistive switches (1.80 kW typ.) to VCC2 and VSS. On−chip matching of drivers insures equivalent channel capability. Load current switching matching is more dependent on the characteristics of the external MOSFET and load. Figure 12 shows the gate driver block diagram. DX0 D1 1800 GAT X Shorted Load Detection An external reference voltage (applied to the FLTREF input) serves as a common reference for all channels (Figure 13) in detecting shorted load conditions. The FLTREF voltage must be within the range of 0 to VCC1−2.0V. The part is designed to be used with a voltage divider between VCC1 and GND. Shorted load detection thresholds can be programmed via the SPI port in four 25% increments that are ratiometric Figure 13. Gate Driver Channel Fault Diagnostics and Behavior Each channel has independent fault diagnostics and employs both blanking and filter timers to suppress false faults. An external MOSFET is monitored for fault conditions by connecting its drain to a channel’s DRNX feedback input through an external series resistor. http://onsemi.com 15 NCV7512 Fault Recovery Refresh Time Refresh time for shorted load faults is SPI programmable to one of two values (10ms or 40ms) for channels 1−2 (register bit R2) and for channels 3−4 (register bit R5) via the Refresh and Reference register (Table 4). A global refresh timer is used for auto−retry timing. The first faulted channel triggers the timer and the full refresh period is guaranteed for that channel. An additional faulted channel may initially retry immediately after its turn−on blanking time, but subsequent retries will have the full refresh time period. If all channels in a group (e.g. channels 1−2) become faulted, they will become synchronized to the selected refresh period for that group. If all channels become faulted and are set for the same refresh time, all will become synchronized to the refresh period. to the applied FLTREF voltage. Separate thresholds can be selected for channels 1−2 and for channels 3−4 (Table 4). A shorted load fault is detected when a channel’s DRNX feedback is greater than its programmed fault reference (after the turn−on blanking or the fault filter has timed out). VCC1 RX1 CHANNELS 1−2 FLTREF 0 − 3V VCC1 + RX2 KELVIN 4 OA 3 2 1 2X4 DECODER 100% − R R1 R2 75% REGISTER 2 BITS R 50% R R4 R3 25% R 4 3 2 1 2X4 DECODER CHANNELS 3−4 Open Load and Short to GND Detection A window comparator with fixed references proportional to VCC1 along with a pair of bias currents is used to detect open load or short to GND faults when a channel is off. Each channel’s DRNX feedback is compared to the references after either the turn−off blanking or the filter has timed out. Figure 14 shows the DRNX fault detection zones. Note, the diagnostics are disabled and the bias currents are turned off when ENAX is low. No fault is detected if the feedback voltage at DRNX is greater than the VOL open load reference. If the feedback is less than the VSG short to GND reference, a short to GND fault is detected. If the feedback is less than VOL and greater than VSG, an open load fault is detected. Figure 14. Shorted Load Reference Generator Shorted Load Fault Recovery Each channel is SPI programmable for shorted load response. The MX bits in the device’s Disable Mode register (Table 3) control the channels to latch−off during a fault or auto−retry. When latch−off mode is selected the corresponding GATX output is turned off upon detection of a fault. Fault recovery is initiated by toggling (ON→OFF→ON) the channel’s respective INX parallel input, serial GX bit, or ENA2. When auto−retry mode is selected (default mode) the corresponding GATX output is turned off for the duration of the programmed fault refresh time (tFR) upon detection of a fault. The output is automatically turned back on (if still commanded on) when the refresh time ends. The channel’s DRNX feedback is re−sampled after the turn−on blanking time. The output will automatically turn off if a fault is again detected. This behavior will continue for as long as the channel is commanded on and the fault persists. In either mode, a fault may exist at turn−on or may occur some time afterward. To be detected, the fault must exist longer than either the channel fault blanking timer (tBL(ON)) at turn−on or longer than the channel fault filter timer (tFF)some time after turn−on. The length of time that a MOSFET stays on during a shorted load fault is thus limited to either tBL(ON) or tFF. In auto−retry mode, a persistent shorted load fault will result in a low duty cycle (tFD [ tBL(ON)/tFR) for the affected channel and help prevent thermal failure of the channel’s MOSFET. CAUTION − CONTINUOUS INPUT TOGGLING VIA INX, GX or ENA2 WILL OVERRIDE EITHER DISABLE MODE. Care should be taken to service a shorted load fault quickly. I DRNX Short to GND I OL Open Load No Fault 0 −ISG VSG VCTR VOL VDRNX Figure 15. DRNX Bias and Fault Detection Zones Figure 16 shows the simplified detection circuitry. Bias currents ISG and IOL are applied to a bridge along with bias voltage VCTR (50% VCC1 typ.). http://onsemi.com 16 NCV7512 the dynamic behavior of the short to GND/ open load diagnostic are provided in the Applications Information section of this data sheet. VCC1 I SG (20 uA) A B − CMP1 VLOAD VOL D3 + + CMP2 − D1 1600 DZ1 D4 D2 VSG VCTR + _ (VCL) I OL (60 uA) 50 Status Flag (STAB) The open−drain active−low status flag output reports the state of the channels DRNX feedback. Feedback from all channels is logically OR’d to the flag (Figure 16). STAB goes low when any DRNx is low. STAB does not report masked channels. The STAB outputs from several devices can be wire−OR’d to a common pull−up resistor connected to the controller’s 3.3 or 5 V VDD supply. When ENA1 is high, the drain feedback from a channel’s DRNX input is compared to the VOL reference and reported without regard to ENA2 or the commanded state of the channel’s driver. The status flag is reset and disabled when ENA1 is low or when all mask bits are set. See Table 9 for additional details. The status flag is set (low) when the feedback voltage is less than VOL, and the channel’s mask bit (Table 5) is cleared. The flag is reset (hi−Z) when the feedback voltage is greater than VOL, and the channel’s mask bit is cleared. RLOAD DRNX VX RDX RSG +VOS VSG = 30% Vcc1, VOL = 75% Vcc1 Figure 16. Short to GND/Open−Load Detection Normal Operation − When a channel is off and VLOAD and RLOAD are present, RSG (short to ground) is absent, and VDRNX >> VCTR, bias current IOL (open load) is supplied from VLOAD to ground through external resistors RLOAD and RDX, and through the internal 1650W resistance and bridge diode D2. Bias current ISG is supplied from VCC1 to VCTR through D3. No fault is detected if the feedback voltage (VLOAD minus the total voltage drop caused by ISG and the resistance in the path) on CMP1 is greater than VOL (and the voltage on CMP2 is greater than VSG[it will be since RSG is absent]). Open Fault − When either VLOAD or RLOAD, and RSG are absent, the bridge will self−bias so that the voltage at DRNX will settle to about VCTR. An open load fault will be detected since the feedback voltage to CMP1 and CMP2 is between VSG and VOL. Short to GND − Detection can tolerate an offset (VOS) between the NCV7512’s GND and the short. The value of the functional offset is determined by the RDX resistor value and the user defined acceptable threshold shift. When RSG is present and VDRNX << VCTR, bias current ISG is supplied from VCC1 to VOS through D1, the internal 1650W, and the external RDX and RSG resistances. Bias current IOL is supplied from VCTR to ground through D4. A “weak” short to GND can be detected when either VLOAD or RLOAD is absent and the feedback (VOS plus the total voltage rise caused by IOL and the resistance in the path) is less than VOL. The NCV7512 does not distinguish between “weak” shorts and “hard” shorts. When VLOAD and RLOAD are present, a voltage divider between VLOAD and VOS is formed by RLOAD and RSG. A “hard” short to GND may be detected in this case depending on the ratio of RLOAD and RSG and the values of RDX, VLOAD, and VOS. Note that the comparators see a voltage drop or rise due only to the 50W internal resistance and the bias currents. This produces a small difference in the comparison to the actual feedback voltage at the DRNX input. Several equations for choosing RDX and for predicting open load or short to GND resistances, and a discussion of OTHER CHANNELS KX VOL DRNX ENA1 − CMP1 + STAB D Q A 500 kHz CLR POR Figure 17. STAB Flag Logic Fault Flag (FLTB) The open−drain active−low fault flag output can be used to provide immediate fault notification to a host controller. Fault detection from all channels is logically ORed to the flag (Figure 17). The FLTB outputs from several devices can be wire−ORed to a common pull−up resistor connected to the controller’s 3.3 or 5 V VDD supply. The flag is set (low) when a channel detects any fault, the channel’s mask bit (Table 5) is cleared, and both ENAX and CSB are high. The Fault Flag is reset (hi−Z) and disabled when either ENA1 or CSB is low. See Table 9 for additional details. KX FAULT X ENA2 OTHER CHANNELS FLTB S Q R ENA1 POR CSB (RESET DOMINANT) Figure 18. FLTB Flag Logic http://onsemi.com 17 NCV7512 Fault Detection and Capture Each channel of the NCV7512 is capable of detecting shorted load faults when the channel is on, and short to ground or open load faults when the channel is off. Each fault type is uniquely encoded into two−bit per channel fault data. A drain feedback input for each channel compares the voltage at the drain of the channel’s external MOSFET to several internal reference voltages. Separate detection references are used to distinguish the three fault types and blanking and filter timers are used respectively to allow for output state transition settling and for glitch suppression. Fault diagnostics are disabled when either enable input is low. When both enable inputs are high, each channel’s drain feedback input is continuously compared to references appropriate to the channel’s input state to detect faults, but the comparison result is only latched at the end of either a blanking or filter timer event. Blanking timers for all channels are triggered when either ENx input changes state from low to high while the other enable input is high, or when both enable inputs go high simultaneously. A single channel’s blanking timer is triggered when its input state changes. If the comparison of the feedback to a reference indicates an abnormal condition when the blanking time ends, a fault has been detected and the fault data is latched into the channel’s fault latch. A channel’s filter timer is triggered when its drain feedback comparison state changes. If the change indicates an abnormal condition when the filter time ends, a fault has been detected and the fault data is latched into the channel’s fault latch. Thus, a state change of the inputs (ENAX, INX or GX) or a state change of an individual channel’s feedback (DRNX) comparison must occur for a timer to be triggered and a detected fault to be captured. can be captured and identified, and that the device cannot be inadvertently re−programmed by a communication error. The NCV7512 latches a fault when it is detected, and frame error detection will not allow any register to accept data if an invalid frame occurred. When a fault has been detected, the FLTB flag is set and fault data is latched into a channel’s fault latch. The latch captures and holds the fault data and ignores subsequent fault data for that channel until a valid SPI frame occurs. Fault data from all channels is transferred from each channel’s fault latch into the SPI shift register and the FLTB flag is reset when CSB goes low at the start of the SPI frame. Fault latches are cleared and re−armed when CSB goes high at the end of the SPI frame only if a valid frame has occurred; otherwise the latches retain the detected fault data until a valid frame occurs. The FLTB flag will be set if a fault is still present. Fault latches for all channels and the FLTB flag can also be cleared and re−armed by toggling ENA1 H−L−H. A full I/O truth table is given in Table 9. Fault Data Readback Examples Several examples are shown to illustrate fault detection, capture and SPI read−back of fault data for one channel. A normal SPI frame returns 16 bits of data but only the two bits of serial data for the single channel are shown for clarity. The examples assume: The NCV7512 is configured as in Figure 2; Both enable inputs are high; The channel’s flag mask bit is cleared ; Disable mode is set to auto−retry; The parallel input commands the channel; SPI frame is always valid. Fault Capture, SPI Communication, and SPI Frame Error Detection The fault capture and frame error detection strategies of the NCV7512 combine to ensure that intermittent faults http://onsemi.com 18 NCV7512 Shorted Load Detected Refer to Figure 18. The channel is commanded on when INX goes high. GATX goes high and the timers are started. At “A”, the STAB flag is set as the DRNX feedback falls through the VOL threshold. A SPI frame sent soon after the INX command returns data indicating “no fault”. The blanking time ends, and the filter timer is triggered as DRNX rises (a shorted load fault occurs) through the FLTREF threshold. The STAB flag is reset as DRNX passes through the VOL threshold. DRNX is nearly at VLOAD when the filter time ends at “B”. A shorted load fault is detected and captured by the fault latch, GATX goes low, the FLTB flag is set, and the auto−retry timer is started. INx 1 0 FAULT DETECTED 1 GATx A SPI frame sent soon after “B” returns data indicating “shorted load”. The FLTB flag is reset when CSB goes low (“F”). At “C” when CSB goes high at the end of the frame, the fault latch is cleared and re−armed. Since INX and the DRNX feedback are unchanged, FLTB and the fault latch are set and the fault is re−captured (“G”). When the auto−retry timer ends at “D”, GATX goes high and the blanking and filter timers are started. Since INX and DRNX are unchanged, GATX goes low when the blanking time ends at “E” and the auto−retry timer is started. Read−back data continues to indicate a “shorted load” and the FLTB flag continues to be set while the fault persists. 0 DRNx VLOAD VOL FLTREF 0 D 0 BLANK TIMER 1 FILTER TIMER 1 FAULT LATCH 1 0 0 E B t FR t BL(ON) 0 t FR t BL(ON) INTERNAL SIGNALS C t FF 00 11 11 11 11 11 1 CSB 0 SO FLTB A 1 STAB 1 0 00 11 11 11 11 G 1 0 11 F Data bits in the fault latch (00 & 11) represent single channel encoded fault data as described in Table 8. Figure 19. Shorted Load Detected http://onsemi.com 19 NCV7512 Shorted Load Recovery Figure 19 is a continuation of Figure 18. INX is high when the auto−retry timer ends. GATX goes high and the blanking and filter timers are started. The fault is removed before the blanking timer ends, and DRNX starts to fall. As DRNX passes through the VOL threshold at “A”, the STAB flag is set. DRNX continues to fall and settles below the FLTREF threshold. A SPI frame is sent during the blanking time and returns data indicating a “shorted load” fault. Although the fault is removed, updates to the fault latches are suppressed while a blanking or filter timer is active. The same fault is captured again and FLTB is set when CSB goes high. At “B” the blanking time ends and the channel’s fault bits will indicate “no fault” but because the INx GATx 1 D 0 1 0 FAULT REMOVED VLOAD DRNx latched data has not yet been read, the data remains unchanged. The SPI frame sent after the blanking time ends returns a “shorted load” fault because the previous frame occurred during the blanking time. Since the channel’s fault bits indicate “no fault”, FLTB is reset and the fault latch is updated at “C” when CSB goes high. If another SPI frame is sent before “D”, the returned data will indicate “no fault”. The channel is commanded off at “D”. GATX goes low and the timers are started. DRNX starts to rise and the STAB flag is reset as DRNX passes through the VOL threshold. The SPI frame sent at “E” returns data indicating “no fault”. A VOL FLTREF 0 STAB 1 0 BLANK TIMER 1 FILTER TIMER 1 FAULT LATCH 1 CSB SO FLTB B tFR 0 INTERNAL SIGNALS tFF 0 0 tBL(OFF) tBL(ON) 11 11 tFF 11 00 1 C 0 1 0 11 11 11 E 00 1 0 Data bits in the fault latch (00 & 11) represent single channel encoded fault data as described in Table 8. Figure 20. Shorted Load Recovery http://onsemi.com 20 NCV7512 Short to GND/Open Load Figure 20 illustrates turn−off with an open or high resistance load when some capacitance is present at DRNX. In the case of an open load, DRNX rises and settles to VCTR (shown as the solid DRNx waveform). In the case of a high resistance load, DRNX may continue to rise and may eventually settle to VLOAD. Timing diagram description: The channel is commanded off. GATX goes low and the timers are started. DRNX starts to rise and is below the VSG threshold when the blanking time ends at “A”. A short to GND fault is detected and captured by the fault latch, and the FLTB flag is set. DRNX continues to rise and as it passes through the VSG threshold at “B”, the filter timer is triggered. At the end of the filter time, the channel’s fault bits will indicate an “open load” but because the latched data has not yet been read, the data remains unchanged. INx DRNx GATx A SPI frame sent shortly after “B” returns data indicating “short to GND” and the fault latch is updated at “C” when CSB goes high. The next three SPI frames sent after “C” return data indicating an “open load”. The STAB flag is reset at “D” as DRNX passes through the VOL threshold. Note that the filter timer is not triggered as DRNX passes from a fault state to a good state. The channel’s fault bits will indicate “no fault” but because the latched data has not yet been read, the data remains unchanged. The fault latch is updated at “E” when CSB goes high and the FLTB flag remains reset. The next SPI frame sent returns data indicating “no fault”. 1 0 1 0 VLOAD VOL VCTR VSG D 0 STAB 1 FILTER TIMER 1 FAULT LATCH 1 SO FLTB B C 0 BLANK TIMER CSB A 1 0 tBL(OFF) tFF 0 0 00 INTERNAL SIGNALS tFF 10 01 01 E 01 00 1 0 1 0 00 10 01 01 01 00 1 0 Data bits in the fault latch (00, 01 & 10) represent single channel encoded fault data as described in Table 8. Figure 21. Short to GND/Open Load http://onsemi.com 21 NCV7512 Table 9. I/O Truth Table Inputs Outputs* POR ENA1 ENA2 CSB KX INX GX DRNX GATX FLTB STAB DX1DX0 0 X X X →0 X →0 X →L →Z →Z →00 1 0 X X X X X X L Z Z 00 ENA1 1 1 0 X KX X GX X L FLTB STAB DX1DX0 ENA2 1 1→0 1 X KX X →0 X →L →Z →Z →00 1 1 1→0 X KX X GX X →L FLTB STAB DX1DX0 1 1 X X 0 X X X L Z Z − FLAGS MASKED 1 1 0 X 1 X X > VOL L − Z − STAB RESET 1 1 0 X 1 X X < VOL L − L − STAB SET 1 1 0 X 1→0 X X < VOL L − L→Z − STAB RESET 1 1 0 X 0→1 X X < VOL L − Z→L − STAB SET 1 1 1 X 1 0 0 > VOL L Z Z 00 FLAGS RESET 1 1 1 1 1 0 0 VSG<V<VOL L L L 01 FLAGS SET 1 1 1 X 1→0 0 0 VSG<V<VOL L L L→Z 01 STAB RESET 1 1 1 X 0→1 0 0 VSG<V<VOL L L 01 STAB SET 1 1 1 1→0 1 0 0 VSG<V<VOL L L→Z L 01 FLTB RESET 1 1 1 0→1 1 0 0 VSG<V<VOL L Z→L L 01 FLTB SET 1 1 1 1 1 0 0 < VSG L L L 10 FLAGS SET 1 1 1 X 1→0 0 0 < VSG L L L→Z 10 STAB RESET 1 1 1 X 0→1 0 0 < VSG L L Z→L 10 STAB SET 1 1 1 1→0 1 0 0 < VSG L L→Z L 10 FLTB RESET 1 1 1 0→1 1 0 0 < VSG L Z→L L 10 FLTB SET 1 1 1 X 1 1 X < VFLTREF H Z L 00 STAB SET 1 1 1 1 1 1 X VFLTREF<V<VOL L L L 11 FLAGS SET 1 1 1 X 1→0 1 X VFLTREF<V<VOL L L L→Z 11 STAB RESET 1 1 1 X 0→1 1 X VFLTREF<V<VOL L L Z→L 11 STAB SET 1 1 1 1→0 1 1 X VFLTREF<V<VOL L L→Z L 11 FLTB RESET 1 1 1 0→1 1 1 X VFLTREF<V<VOL L Z→L L 11 FLTB SET 1 1 1 1 1 1 X > VOL L L Z 11 STAB RESET 1 1 1 X 1 X 1 < VFLTREF H Z L 00 STAB SET 1 1 1 1 1 X 1 VFLTREF<V<VOL L L L 11 FLAGS SET 1 1 1 X 1→0 X 1 VFLTREF<V<VOL L L L→Z 11 STAB RESET 1 1 1 X 0→1 X 1 VFLTREF<V<VOL L L Z→L 11 STAB SET 1 1 1 1→0 1 X 1 VFLTREF<V<VOL L L→Z L 11 FLTB RESET 1 1 1 0→1 1 X 1 VFLTREF<V<VOL L Z→L L 11 FLTB SET 1 1 1 1 1 X 1 > VOL L L Z 11 STAB RESET * Output states after blanking and filter timers end and when channel is set to latch−off mode. http://onsemi.com 22 COMMENT POR RESET ENA1 RESET ENA2 DISABLE NCV7512 APPLICATION GUIDELINES General Unused DRNX inputs should be connected to VCC1 to prevent false open load faults. Unused parallel inputs should be connected to GND and unused enable inputs should be connected to VCC1. The mask bit for each unused channel should be ‘set’ (see Table 5) to prevent activation of the flags and the user’s software should be designed to ignore fault information for unused channels. For best shorted−load detection accuracy, the external MOSFET source terminals should be star−connected. The NCV7512’s GND pin and the lower resistor in the fault reference voltage divider should be Kelvin connected to the star (See Figures 2 and 13). Auto−retry fault recovery behavior is a necessary consideration from a power dissipation viewpoint (for both the NCV7512 and the MOSFETs). EMI should also be evaluated during auto−retry. Driver slew rate and turn−on/off symmetry can be adjusted externally to the NCV7512 in each channel’s gate circuit by adding a gate series resistor. Resistors and diodes can be added for channel symmetry. Any benefit of EMI reduction by this method comes at the expense of increased switching losses in the MOSFETs. The channel fault blanking timers must be considered when choosing external components (MOSFETs, slew control resistors, etc.) to avoid false faults. Component choices must ensure that gate circuit charge/discharge times stay within the turn−on/turn−off blanking times. The NCV7512 does not have integral drain−gate flyback clamps. Clamp MOSFETs, such as ON Semiconductor’s NID9N05CL, are recommended when driving unclamped inductive loads. This flexibility allows choice of MOSFET clamp voltages suitable to each application. To limit power in the DRNX input clamps and to ensure proper open load or short to GND detection, the RDX resistor must be dimensioned according to the following constraint equations: RDX(MIN) + VPK−VCL(MIN) ICL(MAX) (eq. 2) VSG−|VOS| |ISG| (eq. 3) RDX(MAX) + Where: • VPK is the peak transient drain voltage • VCL is the DRNX input clamp voltage • ICL(MAX) is the input clamp current • VSG short to GND fault detection voltage • ISG short to GND diagnostic current • VOS is the allowable offset (1V max) between the NCV7512’s GND and the short. Once RDX is chosen, the open load and short to GND detection resistances in the application can be predicted: Once RDX is chosen, the open load and short to GND detection resistances in the application can be predicted: V −V ROL w LOAD OL * RDX IOL (eq. 4) RLOAD(VSG " VOS−|ISG|RDX) (eq. 5) RSG v VLOAD−VSG ) |ISG|(RDX ) RLOAD) Using the data sheet values for VCL(MIN) = 27 V, ICL(MAX) = 10 mA, and choosing VPK = 55 V as an example, Equation 2 evaluates to 2.8 kW minimum. Choosing VCC1 = 5.0 V and using the typical data sheet values for VSG = 30%VCC1, ISG = 20 mA, and choosing VOS = 0, Equation 3 evaluates to 75 kW maximum. DRNX Feedback Resistor Each DRNX feedback input has a clamp to keep the applied voltage below the breakdown voltage of the NCV7512. An external series resistor (RDX) is required between each DRNX input and MOSFET drain. Channels may be clamped sequentially or simultaneously but total clamp power is limited by the maximum allowable junction temperature. Selecting RDX = 6.8 kW "5%, VCC1 = 5.0 V, VLOAD = 12.0 V, VOS = 0 V, RLOAD = 555 W, and using the typical data sheet values for VOL, IOL, VSG, and ISG, Equation 4 predicts an open load detection resistance of 130.7 kW. Equation 5 predicts a short to GND detection resistance of 71.1 W. When RDX and the data sheet values are taken to their extremes, the open load detection range is 94.1 kW v ROL v 273.5 kW, and the short to GND detection range is 59.2 W v RSG v 84.4 W. http://onsemi.com 23 NCV7512 APPLICATIONS DRAWINGS Microprocessor Daisy Chain The NCV7512 is capable of being setup in a daisy chain configuration with other similar devices which include additional NCV7512 devices as well as the NCV7513 Hex Low−Side Predriver. Particular attention should be focused on the fact that the first 16 bits which are clocked out of the SO pin when the CSB pin transitions from a high to a low will be the Diagnostic Output Data. These are the bits representing the status of the IC and are detailed in Figure 22. Additional programming bits should be clocked in which follow the Diagnostic Output bits. CSB SCLK CSB SCLK CSB SCLK CSB SCLK NCV7512 NCV7512 NCV7513 Any IC using SPI protocol SI SO SI SO SI SO SI SO Figure 22. Daisy Chain Parallel Control (time consideration) A more efficient way to control multiple SPI compatible devices is to connect them in a parallel fashion and allow each device to be controlled in a multiplex mode. Figure 23 shows a typical connection between the microprocessor or microcontroller and multiple SPI compatible devices. In a daisy chain configuration, the programming information for the last device in the serial string must first pass through all the previous devices. The parallel control setup eliminates that requirement, but at the cost of additional control pins from the microprocessor for each individual CSB (chip select bar) pin for each controllable device. Serial data is only recognized by the device that is activated through its’ respective CSB pin. NCV7512 SI SCLK SI SCLK CSB OUT1 SO OUT2 OUT3 Microprocessor SO CSB chip1 NCV7512 SI SCLK CSB OUT1 SO OUT2 OUT3 CSB chip2 CSB chip3 NCV7512 SI SCLK CSB OUT1 SO OUT2 OUT3 Figure 23. SPI Parallel Control Setup http://onsemi.com 24 NCV7512 PACKAGE DIMENSIONS A1 A −T−, −U−, −Z− 32 LEAD LQFP FT SUFFIX CASE 873A−02 ISSUE C 4X 32 25 0.20 (0.008) AB T-U Z AE 1 B1 DETAIL Y F 9 −Z− 9 4X J 0.20 (0.008) AC T-U Z S1 S 8X −AB− SEATING PLANE M_ R D SECTION AE−AE DETAIL AD G ÉÉ ÉÉ ÉÉ ÉÉ N DETAIL Y V1 17 8 BASE METAL AE M V 0.20 (0.008) B AC T-U Z P −U− −T− C E −AC− H DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF W K X DETAIL AD Q_ GAUGE PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. 0.250 (0.010) 0.10 (0.004) AC FLEXMOS and SMARTDISCRETES are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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