NCP2824 Non-Clip and Power Limit Mono Class D Amplifier with AGC Description The NCP2824 is a Filterless Class D amplifier capable of delivering up to 2.4 W to a 4 W load with a 5 V supply voltage. With the same battery voltage, it can deliver 1.2 W to an 8 W load with less than 1% THD+N. The non−clipping function automatically adjusts the output voltage in order to control the distortion when an excessive input is applied to the amplifier. This adjustment is done thanks to an Automatic Gain Control circuitry (AGC) built into the chip. A simple Single wire interface allows to the non Clipping function to be enabled and disabled. It also allows the maximum distortion level in the output to be configured. A programmable power limit function is also embedded in order to protect speakers from damage caused by an excessive sound level. http://onsemi.com 1 9 PIN FLIP−CHIP FC SUFFIX CASE 499AL PIN CONFIGURATION Features Non Clipping Function with Automatic Gain Control Circuitry Programmable Power Limit Function Single Wire Interface. No Need for Additional Components Max THD+N Configurable by Swire Interface Only One Capacitor Required Fully Differential Architecture: Better RF Immunity No Need for Input Capacitors in Fully Differential Configuration High Efficiency: up to 90% Low Quiescent Current: 2.2 mA Typ Large Output Power Capability High PSRR: up to −80 dB Fully Differential Capability: RF Immunity Thermal and Auto Recovery Short−Circuit Protection CMRR (−80 dB) Eliminates Two Input Coupling Capacitors Pb−Free and Halide−Free Device Typical Applications Audio Amplifier for: • Cellular Phones • Digital Cameras • Personal Digital Assistant and Portable Media Player • GPS • The NCP2824GEVB/D evaluation board configures the device in typical application. September, 2010 − Rev. 0 A3 B1 B2 B3 C1 C2 C3 (Top View) A1 = INP A2 = VDD A3 = OUTP B1 = AGND B2 = NC B3 = PGND C1 = INM C2 = CNTL C3 = OUTM MARKING DIAGRAM A3 A1 C1 MRA F Y WW G or G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Demo Board Available: © Semiconductor Components Industries, LLC, 2010 A2 MRAG FYWW • • • • • • • • • • • • • • • A1 1 Device Package Shipping† NCP2824FCT2G WCSP−9 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NCP2824/D NCP2824 C1 4.7 mF/6.3 V VDD Auto Gain control INN PreAmplificator INP CNTL PWM Modulator Single Wire Interface Auto Gain control GND Figure 1. Simplified Block Diagram http://onsemi.com 2 H BRIDGE OUTN OUTP NCP2824 Table 1. PIN FUNCTION DESCRIPTION Pin Pin Name Type A1 INP Input Positive Input Negative Input C1 INN Input A2 PVDD POWER Description Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must bypass this input to the ground. This capacitor should be placed as close a possible to this input. B2 NC − A3 OUTP Output Non−connected: reserved for production. Must be kept floating in the final application Positive output: Special care must be observed at layout level. See the Layout consideration section C3 OUTN Output Negative output: Special care must be observed at layout level. See the Layout consideration section C2 CNTL Input B3 PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high quality ground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed to avoid high−density current flow in a limited PCB copper track. B1 AGND POWER Analog Ground: This pin is the analog ground of the device and must be connected to GND plane. Control: This pin is dedicated to the control of the chip via the Single wire protocol Table 2. MAXIMUM RATINGS Rating Symbol Value Unit VDD −0.3 to +6.0 V VINP/N −0.3 to +VDD V VDG IDG −0.3 to VDD + 0.3 1 V mA Human Body Model (HBM) ESD Rating are (Note 3) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 3) ESD MM 200 V RqJC 90 TA −40 to +85 °C AVDD, PVDD Pins: Power Supply Voltage (Note 2) INP/N Pins: Input (Note 2) Digital Input/Output: EN Pin: Input Voltage Input Current WCSP 1.5 x 1.5 mm package (Notes 6 and 7) Thermal Resistance Junction to Case °C/W Operating Ambient Temperature Range Operating Junction Temperature Range TJ −40 to +125 °C Maximum Junction Temperature (Note 6) TJMAX +150 °C Storage Temperature Range TSTG −65 to +150 °C Moisture Sensitivity (Note 5) MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C. 2. According to JEDEC standard JESD22−A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins. 4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. 6. The thermal shutdown set to 150°C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max output current and external components selected. R qCA + 125 * T A * R qJC PD http://onsemi.com 3 NCP2824 Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VDD = 3.6 V. (see Note 8)) Symbol Parameter Conditions Min Typ Max Unit 5.5 V 300 350 kHz GENERAL PERFORMANCES VDD Operational Power Supply 2.5 FOSC Oscillator Frequency 250 Idd Isd Supply current Shutdown current VDD = 3.6 V, No Load VDD = 5.5 V, No Load, TA = 85°C 2.2 VDD = 3.6 V, VCNTL = 0 V VDD = 5.5 V, VCNTL = 0 V, TA = 85°C 0.01 mA 4.2 mA 1 TON Turn ON Time Single Wire Activation 7.4 ms TOFF Turn Off Time Single Wire Deactivation 5 ms Class D Output impedance in shutdown mode VENL = 0 V 20 kW 250 mW VDD = 3.6 V, Po = 800 mW, RL = 8 W, F = 1 kHz 86 % VDD = 3.6 V, Po = 1.3 W, RL = 4 W, F = 1 kHz 79 Zsd RDS(ON) h FLP Static drain−source on−state resistance of power Mosfets Efficiency −3 dB Cut off Frequency of the Built in Low Pass Filter kHz 30 TSD Thermal Shut Down Protection 150 °C TSDH Thermal Shut Down Hysteresis 20 °C AGC SECTION Av Voltage gain Single Wire 4 12 dB Av Voltage gain Single Wire 5 18 dB Aa Max AGC attenuation −15 dB Avn AGC Gain step resolution 0.5 dB TA Attack time 0.033 ms/Step TR Release Time 0.013 s/Step TH Hold Time 0.013 s/Step S−WIRE INTERFACE (see Note 9) VIH Rising Voltage Input Logic High VIL Falling Voltage Input Logics Low 1.2 − 5.5 V 0 − 0.4 V VIHYS Input Voltage Hysteresis 100 mV RPLD Pull Down Resistor 20 kW TR Swire Rising time 200 ns TF Swire Falling time 200 ns TSWH Swire High 5 10 45 ms TSWL Swire Low 5 10 75 ms 8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25°C. 9. Single Wire performances is guaranteed by design and characterized 10. Audio performances are given for Vdd = 3.6 V, TA = 25°C and characterized http://onsemi.com 4 NCP2824 Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VDD = 3.6 V. (see Note 8)) Symbol Parameter Conditions Min Typ Max Unit S−WIRE INTERFACE (see Note 9) FSWF Input S−wire Frequency TEHDT Enable High Delay Time TSDD Time to Shunt Down Delay TWAKE−UP TVALID 100 kHz 0 400 ms 300 400 ms 500 ms 400 ms Time to Wake up from shutdown Time to Valid Data 300 AUDIO PERFORMANCES (see Note 10) Output offset Av = 12 dB 0.3 mV PSRRDC Power supply rejection ratio From VDD = 2.5 V to 5.5 V −80 dB PSRRAC Power supply rejection ratio F = 217 Hz, Input ac grounded, Av = 12 dB −70 dB voo F = 1 kHz, Input ac grounded Av = 12 dB −70 Signal to noise ratio Vp = 5 V, Pout = 600 mW (A. Weighted) Av = 12 dB 96 dB Common mode rejection ratio Input shorted together VIC = 1 Vpp, f = 217 Hz −80 dB Vn Output Voltage noise Input ac grounded, Av = 12 dB 20 Hz < f < 20 kHz A. Weighted 34 mV Po Output Power RL = 8 W F = 1 kHz VDD = 5 V 1.2 W VDD = 3.6 V 0.6 VDD = 2.5 V 0.22 VDD = 5 V 1.5 VDD = 3.6 V 0.8 VDD = 2.5 V 0.4 SNR CMRR THD+N<1% THD+N<10% RL = 4 W F = 1 kHz THD+N<1% THD+N<10% THD+N Total harmonic distortion plus noise VDD = 5 V 2 VDD = 3.6 V 1 VDD = 2.5 V 0.4 VDD = 5 V 2.4 VDD = 3.6 V 1.3 VDD = 2.5 V 0.6 VDD = 3.6 V, Po = 0.5 W 0.06 VDD = 5 V, Po = 1 W 0.09 % 8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25°C. 9. Single Wire performances is guaranteed by design and characterized 10. Audio performances are given for Vdd = 3.6 V, TA = 25°C and characterized http://onsemi.com 5 NCP2824 TSWH TF TSWL TR 90% VIH VIL 10% Figure 2. S−Wire Logic Diagram Initial Stage S−Wire CNTL Tsdd / Tvalid T_Wake up Ton Amplifier Mode Off Toff Change configuration On default configuration Figure 3. S−Wire / Enable Timing Diagram http://onsemi.com 6 Amplifier Off NCP2824 TYPICAL OPERATING CHARACTERISTICS 100 100 90 RL = 8 W 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 90 60 50 40 30 20 10 0 200 400 600 40 30 800 10 0 1000 Vdd = 3.6 V 0 1000 1250 Figure 4. Efficiency vs. Pout Figure 5. Efficiency vs. Pout Vdd = 2.5 V 1500 THD (%) Vdd = 3.6 V Vdd = 4.2 V Vdd = 3.0 V 1 Vdd = 2.5 V Vdd = 2.7 V Vdd = 3.0 V Vdd = 3.6 V Vdd = 4.2 V Vdd = 5.0 V Vdd = 5.5 V 10 Vdd = 5.0 V 1 Vdd = 5.5 V 0.1 0.1 10 100 1k 0.01 10 k 10 100 1k 10 k Pout (mW) Pout (mW) Figure 6. THD+N vs. Pout, RL = 8 W Figure 7. THD+N vs. Pout, RL = 4 W 10 1 Pout = 250 mW Pout = 500 mW 1 THD+N (%) THD+N (%) 750 Pout (mW) Vdd = 2.7 V 0.1 0.01 500 100 10 0.01 250 Pout (mW) 100 THD (%) 60 50 20 Vdd = 3.6 V 0 RL = 4 W 10 100 1k 10 k 100 k 0.1 0.01 0.001 Pout = 250 mW 10 100 1k 10 k 100 k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. THD+N vs. Frequency, Vdd = 2.5 V Figure 9. THD+N vs. Frequency, Vdd = 3.6 V http://onsemi.com 7 NCP2824 TYPICAL OPERATING CHARACTERISTICS 1 0 Vdd = 3.0 V Vdd = 3.6 V Vdd = 5.0 V −20 Pout = 999 mW 0.1 Pout = 250 mW PSRR (dB) THD+N (%) −10 Pout = 500 mW 0.01 −30 −40 −50 −60 −70 0.001 10 1k 10 k −80 100 k PEAK VOLTAGE (V) Vdd = 3.0 V Vdd = 3.6 V Vdd = 5.0 V −40 −50 −60 1k 10 k 100 k 2.25 V 1.80 V 1.5 1.35 V 1.0 0.9 V 0 100 2.70 V 2.0 −80 10 3.15 V 2.5 0.5 0.45 V 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (Hz) Vin (V) Figure 12. PSRR vs. Frequency (Inputs Grounded, Gain = 18 dB, Cin = 1 mF) Figure 13. Peak Output Voltage in Power Limit vs. Input Voltage (rms) and Power Limit Settings, Av = 12 dB 25 25 20 PVDD = 3.6 V Temp = 25°C 15% 10 10% 8% 6% 4% 2% 1% 5 0.2 0.4 0.6 PVDD = 3.6 V Temp = 25°C THD+N Target = 20% 20 THD+N Target = 20% THD+N (%) THD+N (%) 100 k Vpeak Target = 3.6 V VDD = 5 V Temp = 25°C 3.0 −70 0 10 k Figure 11. PSRR vs. Frequency (Inputs Grounded, Gain = 12 dB, Cin = 1 mF) 3.5 0 1k Figure 10. THD+N vs. Frequency, Vdd = 5 V −10 15 100 FREQUENCY (Hz) 4.0 −30 10 FREQUENCY (Hz) 0 −20 PSRR (dB) 100 15 15% 10 10% 5 0.8 1.0 0 1.2 0 0.2 0.4 8% 6% 4% 2% 1% 0.6 0.8 1.0 1.2 Vin (V) Vin (V) Figure 14. THD+N vs. Input Voltage (rms) and Non Clip Settings, RL = 8 W, Av = 12 dB Figure 15. THD+N vs. Input Voltage (rms) and Non Clip Settings, RL = 4 W, Av = 12 dB http://onsemi.com 8 NCP2824 Detailed Operating Description General Description AGC Operation The NCP2824 is a Mono class D audio amplifier featuring a preamplifier stage, a PWM stage and an H−Bridge stage with an automatic Gain control circuitry which performs the non clipping function. The AGC operation defines the timings when the non clipping function is engaged. The typical values are described in the Electrical Table (“AGC Section”). Non Clipping Function Attack time (Ta): is defined as the minimum time between two gain decrease. In the presence of an exceeded input signal, when the audio signal is going to be clipped, the gain of the audio amplifier automatically decreases as defined by the AGC operation. The maximum level of THD is programmable and can be set by a final user through the single wire interface (see table n°1). At the same time, the battery voltage is continuously monitored. The output signal is adapted to the dynamic battery voltage (Vdd) in order to avoid distortion due to supply voltage fluctuation like GSM burst. This function solution allows the chip to maximize the sound pressure level while maintaining a controlled THD level. The following picture depicts the non clipping operation. Hold time (Th): is defined as the minimum time between a gain increase after a gain decrease. Release time (Tr): is defined as the minimum time between two gain increase. The following pictures depict the NCP2824 non clipping operation. Th Tr Ta Without Non clip function VP VP/2 With Non clip function Single Wire Interface Operation The single wire interface allows changing the default configuration of the NCP2824. After Wake up, the NCP2824 is configured with: • AGC enable • Non Clip + Power limit • Gain = 18 dB • THD max = 1% The following table described all the NCP2824 configurations. Figure 16. Output of the Amplifier during a Line Transient on the Battery Voltage Power Limit Function: Speaker Protection In addition to the non clipping function, a Power limit function is embedded in the NCP2824 in order to protect speakers from excessive output signal levels. When the output signal exceed this limit, the ??? Thus, the final user can use the Single Wire interface to program the maximum voltage rated by the speaker or to disable this power limit protection. http://onsemi.com 9 NCP2824 use input capacitors when the differential source is not biased or in single ended configuration. In this case it is necessary to take into account the corner frequency which can influence the low frequency response of the NCP2824. The following equation will help choose the adequate input capacitor. Table 4. NCP2824 CONFIGURATION Pulse Counting Register Description 01 AGC AGC disable 03 Reset Reset configuration 04 Gain Control Gain = 12 dB THD Control 1% 02 05 06 07 AGC Enable fc + Gain = 18 dB Over Current Protection This protection allows an over current in the H−Bridge to be detected. When the current is higher than 2 A, the H−Bridge is positioned in high impedance. When the short circuit is removed or the current is lower, the NCP2824 goes back to normal operation. This protection avoids over current due to a bad assembly (Output shorted together, to Vdd or to ground). 2% 08 4% 09 6% 10 8% 11 10% 12 15% 13 20% Layout Recommendations 14 NC+L Non Clip + Power limit 15 NC Non Clip only 16 Power Limit Control 0.45 VPeak 17 1.35 VPeak 19 1.8 VPeak 20 2.25 VPeak 21 2.7 VPeak 22 3.15 VPeak 23 3.6 VPeak NOTE: For Efficiency and EMI considerations, it is strongly recommended to use Power and ground plane in order to reduce parasitic resistance and inductance. For the same reason, it is recommended to keep the output traces short and well shielded in order to avoid them to act as antenna. The level of EMI is strongly dependent upon the application. However, ferrite beads placed close to the NCP2824 will reduce EMI radiation when it is needed. Ferrite value is strongly dependent upon the application. 0.9 VPeak 18 1 2 @ p @ 75 @ 10 3 @ Cin The given values are typical for Vdd = 3.6 V and TA = 25°C characterized Built−in Low Pass Filter This filter allows the user to connect a DAC or a CODEC directly to the NCP2824 input without increasing the output noise by mixing frequency with the DAC/CODEC output frequency. Consequently, optimized operation with DACs or CODECs is guaranteed without additional external components. Figure 17. Example of PCB Layout Decoupling Capacitors The NCP2824 requires a correct decoupling of the power supply in order to guarantee the best operation in terms of audio performances. To achieve optimum performance, it is necessary to place a 4.7 mF low ESR ceramic capacitor as close as possible to the VDD pin in order to reduce high frequency transient spikes due to parasitic inductance (see Layout considerations). Input Capacitors Cin Components Selection To achieve optimum performance, one 4.7 mF 6.3 V X5R should be used to bypass the power input supply (VDD). Also particular care must be observed for DC−bias effects in the ceramic capacitor selection. Smaller case−size and higher DC bias voltage is preferred. Some recommended capacitors include but are not limited to: Thanks to its fully differential architecture, the NCP2824 does not require input capacitors. However, it is possible to 4.7 mF 6.3 V 0603 TDK: C1608X5R0J475MT 0.95 mm max. http://onsemi.com 10 NCP2824 Example of Application Schematic BATTERY C1 4.7 mF/6.3 V INP Differential Audio Input VDD OUTP INN OUTN CNTL PGND AGND Output from microcontroller U1 NCP2824 Figure 18. Differential Configuration BATTERY C1 4.7 mF/6.3 V Single Ended Audio Input INP VDD INN Output from microcontroller OUTP OUTN CNTL PGND AGND U1 NCP2824 Figure 19. Single Ended Configuration http://onsemi.com 11 NCP2824 PACKAGE DIMENSIONS 9 PIN FLIP−CHIP CASE 499AL−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. −A− 4X D 0.10 C −B− DIM A A1 A2 D E b e D1 E1 E TOP VIEW A 0.10 C 0.05 C −C− MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC A2 A1 SIDE VIEW SEATING PLANE D1 e C B e A 9X b 1 2 E1 3 0.05 C A B 0.03 C BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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