THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 RAD-TOLERANT CLASS V, WIDEBAND OPERATIONAL AMPLIFIER FEATURES DESCRIPTION/ORDERING INFORMATION 1 • • • • • • • • Wide Bandwidth: 1 GHz Minimum Gain of 2 V/V (6 dB) High Slew Rate: 800 V/μs Low Voltage Noise: 2.4 nV/√Hz Single Supply: 5 V, 3 V Quiescent Current: 18 mA Rad-Tolerant: 150 kRad (Si) TID QML-V Qualified, SMD 5962-07219 APPLICATIONS • • • • • Active Filter ADC Driver Ultrasound Gamma Camera RF/Telecom The THS4304 is a wideband, voltage-feedback operational amplifier designed for use in high-speed analog signal processing chains operating with a single 5 V power supply. Developed in the BiCom3 silicon germanium process technology, the THS4304 offers best-in-class performance using a single 5 V supply as opposed to previous generations of operational amplifiers requiring ±5 V supplies. The THS4304 is a traditional voltage-feedback topology that provides the following benefits: balanced inputs, low offset voltage and offset current, low offset drift, high common mode and power supply rejection ratio. The THS4304 is offered in 10-pin ceramic flatpack (U) and is specified over the full military temperature range, –55°C to 125°C. DIFFERENTIAL ADC DRIVE From 50 W Source 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 These devices have limited built in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. U PACKAGE TOP VIEW 10 9 8 7 VS– 5 6 NC – No internal connection ORDERING INFORMATION (1) (1) (2) PACKAGED DEVICES PACKAGE TYPE (2) PACKAGE MARKINGS TRANSPORT MEDIA, QUANTITY 5962-0721901VHA Ceramic Flatpack 0721901VHA Tubes, 25 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DISSIPATION RATINGS (1) POWER RATING (1) PACKAGE θJC (°C/W) θJA (°C/W) TA ≤ 25°C TA = 85°C TA = 125°C U (10) 14.7 189 661 mW 344 mW 132 mW Power rating determined for a maximum junction temperature of 150°C. However, distortion starts to substantially increase above 125°C. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT VS Supply voltage VI Input voltage +6.0 V IO Output current VID Differential input voltage ±VS 150 mA ±2 V Continuous power dissipation See Dissipation Rating Table TJ Maximum junction temperature, any condition (2) Tstg Storage temperature range ESD Ratings (1) (2) 150°C –65°C to 150°C HBM 1600 V CDM 1000 V MM 100 V The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. 2 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX ±1.35 ±2.5 2.7 5 VS– – 0.2 VS+ + 0.2 Dual supply Supply voltage, (VS+ and VS–) Single supply Input common-mode voltage range UNIT V V ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad) Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +3 unless otherwise noted TYP PARAMETER CONDITIONS 25°C OVER TEMPERATURE 25°C –55°C to 125°C UNITS MIN/ MAX AC PERFORMANCE Small-Signal Bandwidth G = +2, VO = 100 mVpp 1 GHz Typ G = +3, VO = 100 mVpp 800 MHz Typ G = +5, VO = 100 mVpp 220 MHz Typ Gain Bandwidth Product G > +5 1 GHz Typ 0.1 dB Flat Bandwidth G= +3, VO = 100 mVpp, CF = 0 pF 100 MHz Typ Large-Signal Bandwidth G = +3, VO = 2 VPP 290 MHz Typ Slew Rate G = +3, VO = 2-V Step 800 V/μs Typ Settling Time to 1% G = +3, VO = 2-V Step 11 ns Typ Rise/Fall Times G = +3, VO = 2-V Step 2.5 ns Typ RL= 100 Ω –67 dBc Typ RL = 1 kΩ –85 dBc Typ RL = 100 Ω –100 dBc Typ RL = 1 kΩ –85 dBc Typ G = +3, VO= 2-VPP envelope, 200 kHz tone spacing, Third-Order Output Intercept f = 20 MHz (OIP3) –80 dBc Typ 41 dBm Typ Noise Figure G = +2, f = 1 GHz 15 dB Typ Input Voltage Noise f = 1 MHz 2.4 nV/√Hz Typ Input Current Noise f = 1 MHz 2.1 pA/√Hz Typ Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion G = +3, VO = 2 VPP, f = 10 MHz Third-Order Intermodulation Distortion (IMD3) 3 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad) Specifications: VS = ±2.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted PARAMETER CONDITIONS TYP OVER TEMPERATURE 25°C 25°C –55°C to 125°C UNITS MIN/ MAX 58 54 49 dB Min 0.5 4 6 mV Max 5 μV/°C Typ 20 μA Max 50 nA/°C Typ 1.5 μA Max 10 nA/°C Typ DC PERFORMANCE Open-Loop Voltage Gain (AOL) VO = ±0.8 V Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift 7 VO = 0 V Input Offset Current 0.5 12 1 Input Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio Input Resistance Input Capacitance VO = 0 V, VCM = ±1 V Each input, referenced to GND ±2.7 ±2.3 ±2 V Min 86 78 52 dB Min 100 kΩ Typ 1.5 pF Typ V Min OUTPUT CHARACTERISTICS RL = 100 Ω ±1.4 ±1.3 ±1.15 RL = 1 kΩ ±1.5 ±1.4 ±1.25 Output Current (Sourcing) RL = 10 Ω 98 80 70 mA Min Output Current (Sinking) RL = 10 Ω 95 70 55 mA Min Output Impedance f = 100 kHz Ω Typ Output Voltage Swing 0.016 POWER SUPPLY Maximum Operating Voltage ±2.5 ±2.75 ±2.75 Minimum Operating Voltage ±2.5 ±1.35 ±1.35 V Max Min Maximum Quiescent Current IO = 0 mA 18 18.9 19.7 mA Max Minimum Quiescent Current IO = 0 mA 18 17.5 16.0 mA Min Power Supply Rejection (+PSRR) VS+ = 3 V to 2 V, VS– = –2.5 V 78 72 64 dB Min Power Supply Rejection (–PSRR) VS+ = 2.5 V, VS– = –2 V to –3 V 60 57 53 dB Min 4 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad) Specifications: VS = 3 V: RF = 249 Ω, RL = 500 Ω, and G = +3 unless otherwise noted TYP PARAMETER CONDITIONS 25°C OVER TEMPERATURE 25°C –55°C to 125°C UNITS MIN/ MAX AC PERFORMANCE Small-Signal Bandwidth G = +2, VO = 100 mVpp 1 GHz Typ G = +5, VO = 100 mVpp 230 MHz Typ Gain Bandwidth Product G > +5 1 GHz Typ Slew Rate G = +3, VO = 1-V Step 675 V/μs Typ Rise/Fall Times G = +3, VO = 0.5-V Step 1.5 ns Typ –82 dBc Typ –82 dBc Typ HARMONIC DISTORTION Second Harmonic Distortion G = +3, VO = 0.5 VPP, Third Harmonic Distortion f = 10 MHz RL = 499 Ω Noise Figure G = +2, f = 1 GHz 15 dB Typ Input Voltage Noise f = 1 MHz 2.4 nV/√Hz Typ Input Current Noise f = 1 MHz 2.1 pA/√Hz Typ 5 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad) Specifications: VS = ±1.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted TYP PARAMETER CONDITIONS OVER TEMPERATURE UNITS MIN/ MAX 25°C 25°C –55°C to 125°C Open-Loop Voltage Gain (AOL) VO = ±0.3 V 57 52 50 dB Min Input Offset Voltage 1 4 6 mV Max 5 μV/°C Typ 6 12 20 μA Max 50 nA/°C Typ 0.4 1 1.5 μA Max 10 nA/°C Typ DC PERFORMANCE Input Offset Voltage Drift Input Bias Current Input Bias Current Drift VO = 0 V Input Offset Current Input Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio Input Resistance Input Capacitance VO = 0 V, VCM = ±0.3 V Each input, referenced to GND ±1.7 ±1.3 ±1 V Min 68 62 50 dB Min 100 kΩ Typ 1.5 pF Typ V Min Min OUTPUT CHARACTERISTIC RL = 100 Ω ±0.4 ±0.3 ±0.2 RL = 1 kΩ ±0.5 ±0.4 ±0.3 Output Current (Sourcing) RL = 10 Ω 30 25 20 mA Output Current (Sinking) RL = 10 Ω 32 27 21 mA Min Output Impedance f = 100 kHz Ω Typ Output Voltage Swing 0.016 POWER SUPPLY Maximum Operating Voltage ±1.5 ±2.75 ±2.75 Minimum Operating Voltage ±1.5 ±1.35 ±1.35 V Max Min Maximum Quiescent Current IO = 0 mA 17.2 17.9 18.6 mA Max Minimum Quiescent Current IO = 0 mA 17.2 16.5 15.0 mA Min Power Supply Rejection (+PSRR) VS+ = 1.8 V to 1.2 V, VS– = –1.5 V 80 60 53 dB Min Power Supply Rejection (–PSRR) VS+ = 1.5 V, VS– = –1.2 V to –1.8 V 60 55 52 dB Min 6 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE 5V Frequency Response 1 through 3, 5, 6 0.1 dB Flatness 4 S-Parameters vs Frequency 7 2nd Harmonic Distortion vs Frequency 8, 10 3rd Harmonic Distortion vs Frequency 9, 11 Harmonic Distortion vs Output voltage 12 IMD3 3rd Order Intermodulation Distortion vs Frequency 13 OIP3 3rd Order Output Intercept Point vs Frequency 14 SR Slew Rate vs Output voltage 15 Vn/In Noise vs Frequency 16 Noise Figure vs Frequency 17 Quiescent Current vs Supply voltage 18 Rejection Ratio vs Frequency 19 VO Output Voltage vs Load resistance 20 VOS Input Offset Voltage vs Input common-mode voltage 21 IIB/IIO Input Bias and Offset Current vs Case temperature 22 VOS Input Offset Voltage vs Case temperature 23 VO Small-signal Transient Response 24 VO Large-signal Transient Response 25 VO Settling Time 26 VO Overdrive Recovery Time 27 Iq 3V Frequency Response 28 through 30 Harmonic Distortion vs Frequency 31 Harmonic Distortion vs Output voltage 32 SR Slew Rate vs Output voltage 33 VO Output Voltage vs Load resistance 34 IIB/IIO Input Bias and Offset Current vs Case temperature 35 VOS Input Offset Voltage vs Case temperature 36 7 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (5 V) FREQUENCY RESPONSE FREQUENCY RESPONSE VO = 100 mVP-P Gain = 2, VO = 100 mVpp, RF = 249 W, RL = 100 W, VS = 5 V VO = 2 VP-P Signal Gain – dB VO = 1 VP-P G=2 CF = 0 pF CF = 0.5 pF Signal Gain – dB Signal Gain – dB Gain = 2, RF = 249 W, RL = 100W, VS = 5 V FREQUENCY RESPONSE CF = 1 pF G=3 G=5 VO = 100 mVpp, RF = 249 W, RL = 100 W, VS = 5 V 10 M 1M 10 M 100 M 1G 100 M 1M 10 G 10 M 100 M 1G 10 G f – Frequency – Hz f – Frequency – Hz Figure 1. Figure 2. Figure 3. 0.1 dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE f – Frequency – Hz Gain = 3, VO = 100 mVpp, RF = 249 W, RL = 100 W, VS = 5 V G=5 G=5 100 M VO = 2 Vpp, RF = 249 W, RL = 100 W, VS = 5 V 10 M 100 M 1G 10 G 1M 10 M G=2 100 M 1G 10 G f – Frequency – Hz Figure 4. Figure 5. Figure 6. S-PARAMETERS vs FREQUENCY 2nd-HARMONIC DISTORTION vs FREQUENCY 3rd-HARMONIC DISTORTION vs FREQUENCY S22 2nd-Harmonic Distortion – dBc Signal Gain – dB VO = 1 Vpp, RF = 249 W, RL = 100 W, VS = 5 V G=3 f – Frequency – Hz S21 S12 S11 Gain = 3, VO = 100 mVpp, RF = 249 W, RL = 100 W, VS = 5 V 10 M G=2 1M 1G Signal Gain – dB Signal Gain – dB Signal Gain – dB G=3 10 M 1M 1M 1G 10 G 100 M f – Frequency – Hz Figure 7. 1G Gain = 3, VO = 2 Vpp, RF = 249 W, VS = 5 V f – Frequency – Hz RL = 100 RL = 1 K 3rd-Harmonic Distortion – dBc 1M Gain = 3, VO = 2 Vpp, RF = 249 W, VS = 5 V RL = 100 RL = 1 K 10 G f – Frequency – MHz f – Frequency – MHz Figure 8. Figure 9. 8 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (5 V) (continued) 2nd-HARMONIC DISTORTION vs FREQUENCY RL = 1 K Gain = 3, RF = 249 W, RL = 100 W, VS = 5 V f = 10 MHz Harmonic Distortion – dBc RL = 100 HARMONIC DISTORTION vs OUTPUT VOLTAGE Gain = 3, VO = 1 Vpp, RF = 249 W, VS = 5 V 3rd-Harmonic Distortion – dBc 2nd-Harmonic Distortion – dBc Gain = 3, VO = 1 Vpp, RF = 249 W, VS = 5 V 3rd-HARMONIC DISTORTION vs FREQUENCY RL = 1 K HD3 HD2 RL = 100 f – Frequency – MHz f – Frequency – MHz Output Voltage – Vpp Figure 10. Figure 11. Figure 12. 3rd-ORDER INTERMODULATION DISTORTION vs FREQUENCY 3rd-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY SLEW RATE vs OUTPUT VOLTAGE 900 Gain = 3, RF = 249 Ω, RL = 100 Ω, 200 kHz spacing, VS = 5 V 800 SR − Slew Rate − V/ µ s IMD3 – dBc OIP3 – dBc VO = 1 VPP envelope VO = 2 VPP envelope VO = 2 VPP envelope VS = 5 V Gain = 3, RF = 249 W, RL = 100 W, 200 kHz spacing f – Frequency – MHz Hz V n − Voltage Noise − nV/ Fall 650 600 550 450 400 0 0.5 1 1.5 2 2.5 Figure 13. Figure 14. Figure 15. NOISE vs FREQUENCY NOISE FIGURE vs FREQUENCY QUIESCENT CURRENT vs SUPPLY VOLTAGE Noise Figure − dB 100 In 10 Vn 20 22 18 20 14 12 10 8 6 Gain = 2, RF = 249 Ω, RG = 249 Ω, RL = 100 Ω, VS = 5 V 4 2 1 1k 10 k 100 k 1M 10 M f − Frequency − Hz Figure 16. 0 3 VO − Output Voltage −VPP I q − Quiescent Current − mA Hz I n − Current Noise − pA/ Rise 700 500 16 100 750 f – Frequency – MHz 1000 10 Gain = 2, RF = 249 Ω, RL = 100 Ω, VS = 5 V 850 VO = 1 VPP envelope TA = 125°C TA = 85°C 18 16 TA = 25°C 14 TA = -40°C 12 TA = -55°C 10 8 6 4 2 0 10 M 500 M f − Frequency − Hz Figure 17. 1G 2 2.5 3.5 4.5 3 4 VS − Supply Voltage − V 5 Figure 18. 9 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (5 V) (continued) REJECTION RATIO vs FREQUENCY OUTPUT VOLTAGE vs LOAD RESISTANCE 4 110 4.5 3.5 PSRR+ VO − Output Voltage − V 90 80 70 60 PSRR− 50 5 VS = 5 V CMRR VOS − Input Offset Voltage − mV 100 Rejection Ratio − dB INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE VOLTAGE 40 30 20 3 VS = 5 V 2.5 2 1.5 VS = 5 V 4 3.5 3 2.5 2 1.5 1 0.5 10 0 0 1 10 k 100 k 1M 10 M 100 M 10 1G 100 1000 −1 RL − Load Resistance − Ω f − Frequency − Hz 0 1 2 3 4 5 6 VICR − Input Common-Mode Range − V Figure 19. Figure 20. Figure 21. INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE INPUT OFFSET VOLTAGE vs CASE TEMPERATURE SMALL-SIGNAL TRANSIENT RESPONSE VS = 5 V VS = 5 V IIB Case Temperature – °C Output Voltage – V IIB– Output Gain = 3, RF = 249 W, RL = 100 W, VS = 5 V Time – ns Case Temperature – °C Figure 23. Figure 24. LARGE-SIGNAL TRANSIENT RESPONSE SETTLING TIME OVERDRIVE RECOVERY TIME Time – ns Figure 25. Output Voltage – V Input Gain = 3, RF = 249 W, RL = 100 W, VO = 2 VPP VS = 5 V Input Voltage – V Gain = 3, RF = 249 W, RL = 100 W, VS = 5 V Input Voltage – V Output Voltage – V Output Output Voltage – % of Final Value Figure 22. Input Input Voltage – V Input Offset Current – nA Input Offset Voltage – µV Input Bias Current – µA Input IIO Output Gain = 3, RF = 249 W, RL = 100 W, VS = 5 V Time – ns Figure 26. 10 Time – µs Figure 27. Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (3 V) FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE 15 15 Gain = 2, VO = 100 mVpp, RF = 249 W, RL = 499 W, VS = 3 V VO = 100 mV Signal Gain – dB VO = 200 mV Signal Gain – dB VO = 500 mV G=5 CF = 0 pF 10 Signal Gain – dB Gain = 2, RF = 249 W, RL = 499 W, VS = 3 V CF = 0.5 pF CF = 1 pF 5 10 G=2 5 VO = 100 mVpp, RF = 249 W, RL = 499 W, VS = 3 V 0 10 M 1M 10 M 1M 100 M 1G 100 M 1G 0 10 G f – Frequency – Hz f – Frequency – Hz 100 M 1G 10 G f – Frequency – Hz Figure 28. Figure 29. Figure 30. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SLEW RATE vs OUTPUT VOLTAGE -40 900 HD2 -70 -80 -90 HD3 Gain = 3, RF = 249 W, RL = 499 W, f = 10 MHz, VS = 3 V Gain = 2, RF = 249 Ω, RL = 499 Ω, VS = 3 V 850 SR − Slew Rate − V/µ s -60 Harmonic Distortion – dBc Gain = 3, RF = 249 W, RL = 499 W, VO = 500 mVpp, VS = 3 V -50 Harmonic Distortion – dBc 10 M 1M 10 G HD3 HD2 800 Rise 750 Fall 700 650 600 550 500 -100 450 -110 1 10 400 100 0 f – Frequency – MHz 0.1 0.2 0.3 0.4 0.5 0.6 VO − Output Voltage − VPP Output Voltage – Vpp Figure 31. Figure 32. Figure 33. OUTPUT VOLTAGE vs LOAD RESISTANCE INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE INPUT OFFSET VOLTAGE vs CASE TEMPERATURE 2.25 VS = 3 V IIB+ Input Bias Current – µA VO − Output Voltage − V 1.75 1.5 1.25 1 IIB- IIO Input Offset Current – nA Input Offset Voltage – mV Vs = 3 V 2 Vs = 3 V 0.75 0.5 10 100 1000 RL − Load Resistance − Figure 34. TC – Case Temperature – °C Figure 35. TC – Case Temperature – °C Figure 36. 11 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com APPLICATION INFORMATION For many years, high-performance analog design has required the generation of split power supply voltages, like ±15 V, ±8 V, and more recently ±5 V, to realize the full performance of the amplifiers available. Modern trends in high-performance analog are moving toward single-supply operation at 5 V, 3 V, and lower. This reduces power-supply cost due to less voltage being generated and conserves energy in low-power applications. It also can take a toll on available dynamic range, a valuable commodity in analog design, if the available voltage swing of the signal also must be reduced. Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). SNR is simply the signal level divided by the noise: Signal SNR + Noise and SFDR is the signal level divided by the highest spur: Signal SFDR + Spur In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltage available to operate the transistors within the amplifier. When noise and distortion remain constant, the result is a commensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used to make the operational amplifier must have superior noise and distortion performance with lower power supply overhead required for proper transistor operation. The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2 Vpp signal swing at its output on a single 5 V supply with noise and distortion performance similar to the best 10 V operational amplifiers on the market today GENERAL APPLICATION The THS4304 is a traditional voltage-feedback topology with wideband performance up to 1 GHz at a gain of 2 V/V. Care must be taken to ensure that parasitic elements do not erode the phase margin. Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can cause problems. To reduce parasitic capacitance, the ground plane should be removed from under the part. To reduce inductance in the feedback, the circuit traces should be kept as short and direct as possible. For a gain of +2V/V, it is recommended to use a 249 Ω feedback resistor. With good layout, this should keep the frequency response peaking to around 6 dB. This resistance is high enough to not load the output excessively, and the part is capable of driving 100 Ω load with good performance. Higher-value resistors can be used, with more peaking. Lower-value feedback resistors also can be used to reduce peaking, but degrade the distortion performance with heavy loads. Power supply bypass capacitors are required for proper operation. The most critical are 0.1 μF ceramic capacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared with other components in the same area as the operational amplifier. HARMONIC DISTORTION For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypass capacitors when using a split supply. It also is recommended to use a single ground or reference point for input termination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow the EVM layout closely in your application. 12 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 EVALUATION MODULES The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the other for the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the part and building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for the boards are shown in the following illustrations. −VS J3 −VS J4 +VS J6 FB1 VREF R3 GND GND J5 FB2 +VS R6 +VS C5 C1 C2 GND C4 TP1 C3 R8 C8 −VS R7 C6* +VS R9 +VS U1 J1 C7 R10 THS4304 4 3 5 1 R2 C9 J2 2 R11 R1 R12* −VS VREF *C6 − DGK EVM Only *R12 − DBV EVM Only Figure 37. EVM Full Schematic 13 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 EVM BILL OF MATERIALS THS4304 EVM (1) Item 1 Description SMD Size Reference Designator PCB Quantity Manufacturer's Part Number Distributor's Part Number FB1, FB2 2 (STEWARD) HI1206N800R-00 (DIGI-KEY) 240-1010-1-ND Bead, ferrite, 3 A, 80 Ω 1206 2 Capacitor, 3.3 μF, Ceramic 1206 C1, C2 2 (AVX) 1206YG335ZAT2A (GARRETT) 1206YG335ZAT2A 3 Capacitor, 0.1 μF, Ceramic 0603 C4, C5 2 (AVX) 0603YC104KAT2A (GARRETT) 0603YC104KAT2A 4 Open 0603 C3, C6 (2) 2 5 Open 0603 R1, R3, R6, R9, R12 (3) 5 6 Resistor, 0 Ω, 1/10 W, 1% 0603 C7. C8, C9, C10 4 (KOA) RK73Z1JTTD (GARRETT) RK73Z1JTTD 7 Resistor, 49.9 Ω, 1/10 W, 1% 0603 R2, R11 2 (KOA) RK73H1JLTD49R9F (GARRETT) RK73H1JLTD49R9F 8 Resistor, 249 Ω, 1/10 W, 1% 0603 R7, R8 2 (KOA) RK73H1JLTD2490F (GARRETT) RK73H1JLTD2490F 9 Jack, banana recepticle, 0.25 in. diameter hole J3, J4, J5, J6 4 (HH SMITH) 101 (NEWARK) 35F865 10 Test point, black 11 Connector, edge, SMA PCB jack 12 Integrated Circuit, THS4304 13 TP1 1 (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND J1, J2 2 (JOHNSON) 142-0701-801 (NEWARK) 90F2624 U1 1 (TI) THS4304DGK, or (TI) THS4304DBV Standoff, 4-40 HEX, 0.625 in. Length 4 (KEYSTONE) 1808 14 Screw, Phillips, 4-40, 0.250 in. 4 SHR-0440-016-SN 15 Board, printed-circuit 1 (TI) THS4304DGK ENG A, or (TI) THS4304DBV ENG A (1) (2) (3) NEWARK) 89F1934 NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted. C6 used on DGK EVM only. R12 used on DBV EVM only. 14 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Figure 38. THS4304DGK EVM Layout Top and L2 Figure 39. THS4304DGK EVM Layout Bottom and L3 Figure 40. THS4304DBV EVM Layout Top and L2 Figure 41. THS4304DBV EVM Layout Bottom and L3 15 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 NON-INVERTING GAIN WITH SPLIT SUPPLY The following schematic shows how to configure the operational amplifier for non-inverting gain with split power supply (±2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposes because most signal generators and analyzer are designed to use ground-referenced signals by default. Note the input and output provides 50 Ω termination. −VS −VS C5 0.1 mF C8 R8 R7 249 W 249 W GND J3 GND J4 +VS J6 FB1 J5 FB2 C1 3.3 mF C2 3.3 mF +VS C4 0.1 mF GND TP1 0 +VS J1 4 C7 R10 0 0 R11 49.9 W U1 5 3 1 2 THS4304DBV R2 C9 49.9 W 0 J2 −VS Figure 42. Non-Inverting Gain With Split Power Supply 16 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 INVERTING GAIN WITH SPLIT POWER SUPPLY The following schematic shows how to configure the operational amplifier for inverting gain of 1 (–1 V/V) with split power supply (±2.5 V). Note the input and output provides 50 Ω termination for convenient interface to common test equipment. −VS −VS C5 0.1 mF R7 GND J3 J4 C7 R9 0 221 W J6 +VS J5 FB2 FB1 C1 3.3 mF C2 3.3 mF +VS C4 0.1 mF GND 249 W J1 GND TP1 +VS U1 R11 61.9 W 44 3 R1 124 W − + 5 22 11 THS4304DBV R2 C9 49.9 W 0 J2 −VS C8 0 Figure 43. Inverting Gain With Split Power Supply 17 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 NON-INVERTING SINGLE-SUPPLY OPERATION The THS4304 EVM can easily be configured for single 5 V supply operation, as shown in the following schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to reference (or bias) the input signal to mid-supply. If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input (C7) and output (C9). VREF R3 R6 +VS 10 kW 10 kW −VS GND GND J3 J4 J6 +VS J5 +VS FB2 NC C8 R8 R7 0.1 mF 249 W 249 W C2 3.3 mF GND C4 0.1 mF TP1 +VS J1 C7 R10 0 0 44 33 − + R1 49.9 W U1 55 22 11 THS4304DBV R2 C9 49.9 W 0 J2 C5 0 VREF Figure 44. Non-Inverting 5-V Single-Supply Amplifier DIFFERENTIAL ADC DRIVE AMPLIFIER The circuit shown in Figure 44 is adapted as shown in Figure 45 to provide a high-performance differential amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14 bit 125 MSP ADC). For testing purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the input signal source in your application is differential and biased to mid-rail, no transformer is required. The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two 10 kΩ resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the single-supply circuit of Figure 44). Applying this voltage to the one side of RG and to the positive input of the operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled from the amplifier output, via the two 1 nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is used to bias the ADC input to the required voltage, via the 1 kΩ resistors. Note: 100 μA common-mode current is drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100 mV shift in the input common-mode voltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect, a voltage divider from the power supply can be used to derive the input common-mode voltage reference. Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide impedance matching and amplification of the signal. 18 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP THS4304-SP www.ti.com SGDS038A – SEPTEMBER 2007 – REVISED OCTOBER 2007 +5 V 10 k W V REF (= 2 .5V ) RG RF 0.1 mF 10 k W V REF +5V + 3 .3 VA +3 .3 VD THS4304 1 :1 100 W V IN V REF From 50 W Source 49 .9 W 1 nF 1k W CM +5V A IN+ ADS 5500 1k W A IN− CM D A THS4304 100 W 1 nF CM 0. 1 mF V REF RG RF Figure 45. Differential ADC Drive Amplifier Circuit 19 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): THS4304-SP PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 5962-0721901VHA ACTIVE CFP U Pins Package Eco Plan (2) Qty 10 1 TBD Lead/Ball Finish A42 MSL Peak Temp (3) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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