MC10EL32, MC100EL32 5V ECL ÷2 Divider Description Features • 510 ps Propagation Delay • 3.0 GHz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, • • • MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 8 1 > 100 V Machine Model PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK(s) and R. Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 82 devices Pb−Free Packages are Available TSSOP−8 DT SUFFIX CASE 948R 8 8 HEL32 ALYW G 1 KEL32 ALYW G 1 8 1 8 HL32 ALYWG G 4U M G G • • • • • http://onsemi.com 1 4 1 KL32 ALYWG G 2J M G G The MC10EL/100EL32 is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple EL32’s in a system. The 100 Series contains temperature compensation. 1 4 DFN8 MN SUFFIX CASE 506AA H = MC10 K = MC100 4U = MC10 2J = MC100 A = Assembly Location L Y W M G = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 8 1 Publication Order Number: MC10EL32/D MC10EL32, MC100EL32 Reset CLK 1 8 R 2 7 Table 1. PIN DESCRIPTION VCC PIN Q ÷2 CLK VBB 3 6 4 5 Q VEE FUNCTION CLK, CLK ECL Clock Inputs* Reset ECL Asynch Reset* Q, Q ECL Data Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. Logic Diagram and Pinout Assignment *Pins will default low when left open. Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 8 V −8 V 6 −6 V V 50 100 mA mA ± 0.5 mA VCC PECL Mode Power Supply VEE = 0 V VEE NECL Mode Power Supply VCC = 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C qJC Thermal Resistance (Junction−to−Case) 35 to 40 °C/W Pb Pb−Free VI VCC VI VEE DFN8 DFN8 (Note 1) DFN8 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) http://onsemi.com 2 MC10EL32, MC100EL32 Table 3. 10EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 2) −40°C Symbol Characteristic Min 25°C Typ Max 25 30 Min 85°C Typ Max 25 30 Min Typ Max Unit 25 30 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 3) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single−Ended) 3770 4110 3870 4190 3940 4280 mV VIL Input LOW Voltage (Single−Ended) 3050 3500 3050 3520 3050 3555 mV VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.81 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 2.5 4.6 2.5 4.6 2.5 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 0.5 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V. 3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 4. 10EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 5) −40°C Symbol Characteristic Typ Max 25 30 Max 25 30 −1080 −990 −890 −980 −895 −810 Output LOW Voltage (Note 6) −1950 −1800 −1650 −1950 −1790 VIH Input HIGH Voltage (Single−Ended) −1230 −890 VIL Input LOW Voltage (Single−Ended) −1950 VBB Output Voltage Reference VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) IIH Input HIGH Current IIL Input LOW Current Power Supply Current VOH Output HIGH Voltage (Note 6) VOL Min 85°C Typ IEE Min 25°C Typ Max Unit 25 30 mA −910 −815 −720 mV −1630 −1950 −1773 −1595 mV −1130 −810 −1060 −720 mV −1500 −1950 −1480 −1950 −1445 mV −1.43 −1.30 −1.35 −1.25 −1.31 −1.19 V −2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V 150 mA 150 0.5 Min 150 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V. 6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 3 MC10EL32, MC100EL32 Table 5. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 8) −40°C Symbol Characteristic Min 25°C Typ Max 25 30 Min 85°C Typ Max 25 30 Min Typ Max Unit 29 35 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 9) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 9) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 2.5 4.6 2.5 4.6 2.5 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 9. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 6. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 11) −40°C Symbol Characteristic Min 25°C Typ Max 25 30 Min 85°C Typ Max 25 30 Min Typ Max Unit 29 35 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 12) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 12) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) −2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 12. Outputs are terminated through a 50 W resistor to VCC−2 volts. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 4 MC10EL32, MC100EL32 Table 7. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V or VCC = 0 V; VEE = −5.0 V (Note 14) −40°C Symbol Characteristic fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay VPP Input Swing (Note 15) tJITTER Cycle−to−Cycle Jitter tr tf Output Rise/Fall Times Q (20% − 80%) CLK to Q Reset to Q Min Typ 2.2 3.0 360 390 500 540 150 25°C Max Min Typ 2.6 3.0 640 690 420 440 510 540 1000 150 TBD 100 225 85°C Max Min Typ 2.6 3.0 600 640 450 450 540 550 1000 150 TBD 350 100 Max GHz 630 650 ps 1000 mV TBD 225 350 100 225 Unit ps 350 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. 10 Series: VEE can vary +0.25 V / −0.5 V. 100 Series: VEE can vary +0.8 V / −0.5 V. 15. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. CLK RESET Q Figure 2. Timing Diagram Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 5 MC10EL32, MC100EL32 ORDERING INFORMATION Package Shipping† SOIC−8 98 Units / Rail MC10EL32DG SOIC−8 (Pb−Free) 98 Units / Rail MC10EL32DR2 SOIC−8 2500 / Tape & Reel MC10EL32DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC10EL32DT TSSOP−8 100 Units / Rail MC10EL32DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC10EL32DTR2 TSSOP−8 2500 / Tape & Reel MC10EL32DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC10EL32MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel SOIC−8 98 Units / Rail MC100EL32DG SOIC−8 (Pb−Free) 98 Units / Rail MC100EL32DR2 SOIC−8 2500 / Tape & Reel MC100EL32DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100EL32DT TSSOP−8 100 Units / Rail MC100EL32DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100EL32DTR2 TSSOP−8 2500 / Tape & Reel MC100EL32DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100EL32MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC10EL32D MC10EL32MNR4G MC100EL32D MC100EL32MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 6 MC10EL32, MC100EL32 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC10EL32, MC100EL32 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B −U− 4 M A −V− S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 8 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC10EL32, MC100EL32 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ TOP VIEW 0.10 C 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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