EVALUATION KIT AVAILABLE MAX15003 Triple-Output Buck Controller with Tracking/Sequencing General Description The MAX15003 is a triple-output, pulse-width-modulated (PWM), step-down DC-DC controller with tracking and sequencing capability. The device operates over the input voltage range of 5.5V to 23V or 5V ±10%. Each PWM controller provides an adjustable output down to 0.6V and delivers up to 15A for each output with excellent load and line regulation. The MAX15003 is optimized for high-performance, small-size power management solutions. The options of coincident tracking, ratiometric tracking, and output sequencing allow the tailoring of the powerup/power-down sequence depending on the system requirements. Each of the MAX15003 PWM sections utilizes a voltage-mode control scheme with external compensation allowing for good noise immunity and maximum flexibility with a wide selection of inductor values and capacitor types. Each PWM section operates at the same, fixed switching frequency that is programmable from 200kHz to 2.2MHz and can be synchronized to an external clock signal using the SYNC input. Each converter operating at up to 2.2MHz with 120° out-of-phase, increases the input capacitor ripple frequency up to 6.6MHz, thereby reducing the RMS input ripple current and the size of the input bypass capacitor requirement significantly. The MAX15003 includes internal input undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of each converter. The power-on reset (RESET) with an adjustable timeout period monitors all three outputs and provides a RESET signal to the processor when all outputs are within regulation. Protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. The MAX15003 is available in a space-saving, 7mm x 7mm, 48-pin TQFN-EP package and is specified for operation over the -40°C to +125°C automotive temperature range. See the MAX15002 data sheet for a dual version of the MAX15003. Applications PCI Express® Host Bus Adapter Power Supplies Features o 5.5V to 23V or 5V ±10% Input Voltage Range o Triple-Output Synchronous Buck Controller o Selectable In-Phase or 120° Out-of-Phase Operation o Output Voltages Adjustable from 0.6V to 0.85VIN o Lossless Valley-Mode Current Sensing or Accurate Valley Current Sensing Using RSENSE o External Compensation for Maximum Flexibility o Digital Soft-Start and Soft-Stop o Sequencing or Coincident/Ratiometric VOUT Tracking o Individual PGOOD Outputs o RESET Output with a Programmable Timeout Period o 200kHz to 2.2MHz Programmable Switching Frequency o External Frequency Synchronization o Hiccup Mode Short-Circuit Protection o Space-Saving (7mm x 7mm) 48-Pin TQFN Package Ordering Information PART TEMP RANGE MAX15003ATM+ -40°C to +125°C PIN-PACKAGE 48 TQFN-EP* (7mm x 7mm) +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: Devices are also available in a tape-and-reel packaging. Specify tape and reel by adding “T” to the part number when ordering. Tape-and-reel orders are available in 2.5k increments. Networking/Server Power Supplies Point-of-Load DC-DC Converters Pin Configuration appears at end of data sheet. PCI Express is a registered trademark of PCI-SIG Corporation. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-1048; Rev 1; 8/12 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing ABSOLUTE MAXIMUM RATINGS IN, LX_, CSN_ to SGND..........................................-0.3V to +30V BST_ to SGND ........................................................-0.3V to +30V BST_ to LX_ ..............................................................-0.3V to +6V REG, DREG_, SYNC, EN_, RT, CT, RESET, PHASE, SEL to SGND ...............................-0.3V to +6V ILIM_, PGOOD_, FB_, COMP_, CSP_ to SGND .......-0.3V to +6V DL_ to PGND_.......................................-0.3V to (VDREG_ + 0.3V) DH_ to LX_ ...............................................-0.3V to (VBST_ + 0.3V) PGND_ to SGND, PGND_ to Any Other PGND_.......-0.3V to +0.3V Continuous Power Dissipation (TA = +70°C) 48-Pin TQFN (derate 38.5mW/°C above +70°C) .......3076.9mW* Operating Junction Temperature Range ...........-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C *As per JEDEC51 standard (multilayer board). Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) 48 TQFN Junction-to-Ambient Thermal Resistance (θJA)...............26°C/W Junction-to-Case Thermal Resistance (θJC)......................1.3°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA = TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 23.0 V VIN = VREG = VDREG_ (Note 2) 4.5 5.5 V VIN rising 3.95 4.15 V SYSTEM SPECIFICATIONS Input Voltage Range Input Undervoltage Lockout Threshold VIN VUVLO Input Undervoltage Lockout Hysteresis 4.05 0.35 Operating Supply Current VIN = 12V, VFB_ = 0.8V, no switching Shutdown Supply Current VIN = 12V, EN_ = 0V, PGOOD_ unconnected V 5 8 mA 150 300 µA REG VOLTAGE REGULATOR Output-Voltage Setpoint VREG Load Regulation VIN = 5.5V to 23V 4.9 IREG = 0 to 120mA, VIN = 12V 5.2 V 0.2 V DIGITAL SOFT-START/SOFT-STOP Soft-Start/Soft-Stop Duration Reference Voltage Steps 2048 Clocks 64 Steps ERROR TRANSCONDUCTANCE AMPLIFIER FB_, TRACK_ Input Bias Current FB_ Voltage Setpoint 2 -250 VFB TA = TJ = 0°C to +85°C TA = TJ = -40°C to +125°C +250 nA 0.5945 0.6 0.6065 V 0.590 0.6 0.608 V Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing ELECTRICAL CHARACTERISTICS (continued) (VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA = TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN FB_ to COMP_ Transconductance TYP MAX 2.1 COMP_ Output Swing 0.75 UNITS mS 3.50 V Open-Loop Gain 80 dB Unity-Gain Bandwidth 10 MHz CLOAD = 5nF 20 ns DRIVERS DL_, DH_ Break-Before-Make Time DH1 On-Resistance DH2 On-Resistance DH3 On-Resistance DL1 On-Resistance DL2 On-Resistance DL3 On Resistance LX_ to PGND_ On-Resistance Low, sinking 100mA 0.9 High, sourcing 100mA 1.3 Low, sinking 100mA 0.9 High, sourcing 100mA 0.3 Low, sinking 100mA 0.9 High, sourcing 100mA 1.3 Low, sinking 100mA 0.9 High, sourcing 100mA 1.3 Low, sinking 100mA 0.9 High, sourcing 100mA 1.3 Low, sinking 100mA 0.9 High, sourcing 100mA 1.3 Sinking 10mA Ω Ω Ω Ω Ω Ω Ω 8 CURRENT-LIMIT AND HICCUP MODE Cycle-By-Cycle Valley CurrentLimit Adjustment Range VCL VCL_ = VILIM_ / 10 50 300 Cycle-By-Cycle Valley CurrentLimit Threshold Tolerance VILIM_ = 0.5V 44 54 VILIM_ = 3V 290 310 ILIM_ Reference Current VILIM_ = 0 to 3V, TA = TJ = +25°C ILIM_ Reference Current Temperature Coefficient CSP_, CSN_ Input Bias Current Number of Cumulative CurrentLimit Events to Hiccup Number of Consecutive NonCurrent-Limit Cycles to Clear NCL VCSP_ = 0V, VCSN_ = -0.3V mV 20 µA 3333 ppm/°C -20 +20 NCL 8 NCLR 3 Hiccup Timeout mV µA Clock periods 4096 ENABLE/PHASE/SEL EN_ Threshold VEN–TH EN_ rising 1.19 EN_ Threshold Hysteresis EN_ Input Bias Current Maxim Integrated 1.215 1.24 V +1 µA 0.12 -1 V 3 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing ELECTRICAL CHARACTERISTICS (continued) (VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA = TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS PHASE Input Logic High MIN TYP MAX UNITS 0.8 V 2 V PHASE Input Logic Low PHASE Input Bias Current -1 SEL High Threshold 80 +1 SEL Low Threshold SEL Input Bias Current Present only during startup -100 FB_ For Threshold PGOOD_ FB_ falling 0.540 RESET, PGOOD_ Output Low Level Sinking 3mA µA %VREG 20 %VREG +100 µA 0.570 V 0.1 V PGOOD, RESET OUTPUTS RESET, PGOOD_ Leakage -1 CT Charging Current 1.8 CT Pulldown Resistance 0.555 2.0 Sinking 3mA CT rising CT Threshold for RESET Delay 1.8 CT failling +1 µA 2.2 µA 33 Ω 2.6 1.2 V OSCILLATOR Switching Frequency Range (Each Converter) fSW Switching Frequency Accuracy (Each Converter) 200 2200 fSW ≤ 1500kHz -5 +5 fSW ≥ 1500kHz -7 +7 VPHASE = 0V (DH1 rising to DH2 rising and DH2 rising to DH3 rising) Phase Delay RT Voltage VSYNC = 0V, fCLK = 1011 / (RRT + 1.75kΩ) VRT kHz % 120 degrees VPHASE = VREG (DH1 rising to DH2 rising and DH2 rising to DH3 rising) 0 degrees 40kΩ < RRT < 500kΩ 2 V Minimum Controllable On-Time tON(MIN) 75 ns Minimum Off-Time tOFF(MIN) 150 ns SYNC High-Level Voltage 2 V SYNC Low-Level Voltage SYNC Internal Pulldown Resistor SYNC Frequency Range 50 (Note 3) 100 0.6 0.8 V 200 kΩ 6.9 MHz SYNC Minimum On-Time SYNC Minimum Off-Time 30 30 ns ns PWM Ramp Amplitude (Peak-to-Peak) 2 V PWM Ramp Valley 1 V Note 1: 100% production tested at TA = TJ = +25°C and TA = TJ = +125°C. Limits at other temperature are guaranteed by design. Note 2: For 5V applications, connect REG directly to IN. Note 3: The switching frequency is 1/3 of the SYNC frequency. 4 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Characteristics (Figure 8, VIN = 12V, CREG = 2.2µF, TA = +25°C, unless otherwise noted.) VIN = 16V 60 VIN = 12V 60 VIN = 16V 50 40 0 1 0.1 0.1 10 CONVERTER 1 LOAD REGULATION 0.25 0 -0.25 -0.50 -0.75 0.1 CONVERTER 3 LOAD REGULATION 0.75 1.00 0.50 0.25 0 -0.25 -0.50 2000 2500 3000 0 1000 2000 3000 4000 5000 4.97 VREG (V) -0.50 VOUT3 = 1.2V 0 6000 2000 4.96 4.95 4.94 4.93 4.92 VIN = 12V CREG = 2.2µF 4.91 4.90 60 IREG (mA) 80 4000 6000 8000 10,000 LOAD CURRENT (mA) 100 10,000 SWITCHING FREQUENCY (kHz) 4.98 Maxim Integrated -0.25 CONVERTER_ SWITCHING FREQUENCY vs. RRT MAX15003 toc07 4.99 40 0 LOAD CURRENT (mA) 5.00 20 0.25 -1.00 INTERNAL VOLTAGE REGULATION (REG) 0 0.50 MAX15003 toc08 1500 0.75 -0.75 VOUT2 = 2.5V -1.00 LOAD CURRENT (mA) 10 1 LOAD CURRENT (mA) -0.75 VOUT1 = 3.3V MAX15003 toc03 0 MAX15003 toc05 OUTPUT VOLTAGE ACCURACY (%) 0.50 1000 VOUT3 = 1.2V fSW = 600kHz 10 10 1 1.00 MAX15003 toc04 0.75 500 VIN = 12V 40 CONVERTER 2 LOAD REGULATION 1.00 0 VIN = 16V 50 LOAD CURRENT (A) LOAD CURRENT (A) -1.00 60 20 VOUT2 = 2.5V fSW = 600kHz 10 OUTPUT VOLTAGE ACCURACY (%) 40 70 30 20 VOUT1 = 3.3V fSW = 600kHz VIN = 6V 80 30 50 OUTPUT VOLTAGE ACCURACY (%) 90 MAX15003 toc06 70 70 EFFICIENCY (%) VIN = 12V 80 EFFICIENCY (%) 90 VIN = 6V 90 100 MAX15003 toc02 VIN = 6V EFFICIENCY (%) 100 MAX15003 toc01 100 80 CONVERTER 3 EFFICIENCY vs. LOAD CURRENT CONVERTER 2 EFFICIENCY vs. LOAD CURRENT CONVERTER 1 EFFICIENCY vs. LOAD CURRENT 1000 100 0 0 100 200 300 400 500 600 RRT (kΩ) 5 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Characteristics (continued) (Figure 8, VIN = 12V, CREG = 2.2µF, TA = +25°C, unless otherwise noted.) 4 2 0 -2 -4 -6 -8 fSW = 600kHz -10 -25 0 25 50 75 250 200 150 100 80 70 60 50 40 TEMPERATURE COEFFICIENT (NOM.) = 3,333ppm/°C 30 20 50 500 100 125 150 RILIM = 25.5kΩ 90 1000 1500 2000 2500 3000 -50 3500 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) VILIM (mV) SWITCHING CURRENT vs. FREQUENCY RATIOMETRIC STARTUP RATIOMETRIC SHUTDOWN MAX15003 toc14 MAX15003 toc13 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 MAX15003 toc11 300 MAX15003 toc12 SWITCHING CURRENT (mA) -50 100 VALLEY CURRENT-LIMIT THRESHOLD (mV) 6 350 MAX15003 toc10 MAX15003 toc09 8 VALLEY CURRENT-LIMIT THRESHOLD (mV) SWITCHING FREQUENCY ACCURACY (kHz) 10 VALLEY CURRENT-LIMIT THRESHOLD vs. TEMPERATURE VALLEY CURRENT-LIMIT THRESHOLD vs. VILIM SWITCHING FREQUENCY ACCURACY vs. TEMPERATURE 10V/div 0V VIN 500mV/div VOUT1 VOUT2 1V/div 1V/div VOUT3 500mV/div 1V/div VOUT1, 2, 3 200 700 1700 1200 VEN2 = VEN3 = 0V, SEL = REG 0V VOUT1, 2, 3 VEN2 = VEN3 = 0V, SEL = REG 400µs/div 1ms/div 2200 FREQUENCY (kHz) CHANNEL 2 SHORT CIRCUIT (RATIOMETRIC MODE) CHANNEL 1 SHORT CIRCUIT (RATIOMETRIC MODE) MAX15003 toc15 MAX15003 toc16 1V/div VOUT2 VOUT1 1V/div VOUT2 0V 1V/div VOUT3 1V/div VOUT1 1V/div VOUT3 0V VEN2 = VEN3 = 0V, SEL = REG 400µs/div 6 0V VEN2 = VEN3 = 0V, SEL = REG 400µs/div Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Characteristics (continued) (Figure 8, VIN = 12V, CREG = 2.2µF, TA = +25°C, unless otherwise noted.) COINCIDENT STARTUP COINCIDENT SHUTDOWN MAX15003 toc17 MAX15003 toc18 10V/div VIN 0V VOUT1 500mV/div VOUT2 500mV/div VOUT3 500mV/div 1V/div 1V/div 1V/div VOUT1, 2, 3 0V CIRCUIT OF FIGURE 8, SEL = REG 0V 1ms/div 400µs/div CHANNEL 2 SHORT CIRCUIT (COINCIDENT MODE) CHANNEL 1 SHORT CIRCUIT (COINCIDENT MODE) MAX15003 toc19 VIN MAX15003 toc20 VOUT2 10V/div 1V/div VOUT1 0V 1V/div VIN 10V/div 1V/div VOUT1 0V VOUT2 1V/div 1V/div VOUT3 VOUT3 1V/div 0V 0V 400µs/div 400µs/div SEQUENCING SHUTDOWN SEQUENCING STARTUP MAX15003 toc22 MAX15003 toc21 10V/div 0V VIN VOUT1 500mV/div VOUT2 500mV/div VOUT3 500mV/div 1V/div 1V/div 1V/div VOUT1, 2, 3 1ms/div Maxim Integrated 0V 0V SEL = REG SEL = REG 400µs/div 7 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Characteristics (continued) (Figure 8, VIN = 12V, CREG = 2.2µF, TA = +25°C, unless otherwise noted.) RESET AT STARTUP (SEQUENCING MODE) CHANNEL 1 OUTPUT SHORT CIRCUIT (SEQUENCING MODE) MAX15003 toc24 MAX15003 toc23 10V/div VIN 2V/div 0V VOUT1 5V/div VRESET 0V 0V 1V/div VOUT2 1V/div 1V/div 0V 1V/div VOUT3 1V/div VOUT1, 2, 3 0V SEL = GND 0V 20ms/div 400µs/div SEL = GND EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 RESET AT SHUTDOWN (SEQUENCING MODE) CONVERTER 1 SHORT-CIRCUIT CONDITION (HICCUP MODE) MAX15003 toc25 VRESET VOUT1 VOUT2 MAX15003 toc26 5V/div VOUT1 500mV/div 0V IOUT1 10A/div 1V/div VLX1 10V/div VDL1 5V/div VPGOOD1 1V/div 1V/div VOUT3 1V/div 0V SEL = GND 400µs/div 1ms/div EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 CONVERTER 1 OUTPUT SHORT-CIRCUIT (SEQUENCING MODE) CONVERTER 2 OUTPUT SHORT-CIRCUIT (SEQUENCING MODE) MAX15003 toc27 MAX15003 toc28 VIN VOUT1 10V/div SEL = GND 2V/div VIN SEL = GND VOUT2 0V 10V/div 0V 2V/div 0V VOUT2 1V/div VOUT1 2V/div VOUT3 1V/div 0V VOUT3 1V/div 0V 400µs/div EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 8 0V 400µs/div EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Characteristics (continued) (Figure 8, VIN = 12V, CREG = 2.2µF, TA = +25°C, unless otherwise noted.) CONVERTER 3 OUTPUT SHORT-CIRCUIT (SEQUENCING MODE) 120° OUT-OF-PHASE OPERATION MAX15003 toc30 MAX15003 toc29 VIN SEL = GND 10V/div 0V 1V/div VOUT3 0V 5V/div VSYNC 0V VLX1 10V/div 0V VOUT1 2V/div VOUT2 1V/div VLX2 10V/div 0V VLX3 10V/div SEL = GND 0V 0V 400ns/div 400µs/div EN/TRACK2 = PGOOD1 EN/TRACK3 = PGOOD2 BREAK-BEFORE-MAKE TIMING IN-PHASE OPERATION MAX15003 toc31 MAX15003 toc32 SEL = GND 5V/div VSYNC 5V/div VLX1 0V 10V/div VLX1 0V 0V 10V/div VLX2 VDL1 2V/div 0V 10V/div VLX3 0V 0V 400ns/div 20ns/div LOAD-TRANSIENT RESPONSE (IOUT3 = 100mA TO 10A) LOAD-TRANSIENT RESPONSE (IOUT3 = 5A TO 10A) MAX15003 toc34 MAX15003 toc33 100mV/div (AC-COUPLED) VOUT3 5A/div VOUT3 100mV/div (AC-COUPLED) IOUT3 5A/div IOUT3 0A 0A 200µs/div Maxim Integrated 200µs/div 9 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Pin Description 10 PIN NAME FUNCTION 1 CT RESET Timeout Capacitor Connection. Connect a timing capacitor from CT to SGND to set the RESET delay. CT sources 2µA into the timing capacitor. When the voltage at CT passes 2V, open-drain RESET goes high impedance. 2 IN Supply Input Connection. Connect to an external voltage source from 5.5V to 23V. For 4.5V to 5.5V input application, connect IN and REG together. 3 REG 5V Regulator Output. Bypass with a 2.2µF ceramic capacitor to SGND. 4 SEL Track/Sequence Select Input. Connect SEL to REG to configure as a triple tracker at startup or connect SEL to SGND to configure as a triple sequencer or leave SEL unconnected to configure as a dual tracker and independent sequencer. Note: When configured as a triple sequencer, each rail is independently enabled using the EN_. 5 PGND1 Controller 1 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of the synchronous MOSFET, and the output filter capacitor’s return to PGND1. Connect externally to SGND at a single point near the input capacitor return terminal. 6 DL1 Controller 1 Low-Side Gate Driver Output. DL1 is the gate driver output for the synchronous MOSFET. Controller 1 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode. Connect a minimum of 0.1µF ceramic capacitor from DREG1 to PGND1. 7 DREG1 8 LX1 9 DH1 Controller 1 High-Side Gate Driver Output. DH1 drives the gate of the high-side MOSFET. 10 BST1 Controller 1 High-Side Gate Driver Supply. Connect BST1 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 11 CSN1 Controller 1 Negative Current-Sense Input. Connect CSN1 to the synchronous MOSFET drain (connected to LX1). When using a current-sense resistor, connect CSN1 to the junction of a low-side MOSFET’s source and the current-sense resistor. See Figure 11. 12 CSP1 Controller 1 Positive Current-Sense Input. Connect CSP1 to the synchronous MOSFET source (connected to PGND1). When using a current-sense resistor, connect CSP1 to the PGND1 end of the current-sense resistor. 13 ILIM1 Controller 1 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM1, from ILIM1 to SGND to program the valley current-limit threshold from 50mV to 300mV. ILIM1 sources 20µA out to RILIM1. The resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense resistor, connect a resistive divider from REG to ILIM1 to SGND to set the valley current limit. See Figure 11. 14 COMP1 Controller1 Error Transconductance Amplifier Output. Connect COMP1 to the compensation feedback network. 15 EN1 Controller 1 Enable Input. EN1 must be above 1.24V, VEN-TH, for the PWM controller to start Output 1. Controller 1 is the master. Use the master as the highest output voltage in a coincident tracking configuration. Controller 1 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the inductor and the negative side of the boost capacitor to LX1. Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Pin Description (continued) PIN NAME FUNCTION Controller 1 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to SGND to set the output voltage. The FB1 voltage regulates to VFB (0.6V). 16 FB1 17 PGOOD1 Controller 1 Power-Good Output. Open-drain PGOOD1 output goes high impedance (releases) when FB1 is above 0.925 x VFB = 0.555V. 18 PGND2 Controller 2 Power Ground Connection. Connect the input filter capacitor’s negative terminal, the source of the synchronous MOSFET, and the output filter capacitor’s return to PGND2. Connect externally to SGND at a single point near the input capacitor return terminal. 19 DL2 20 DREG2 21 LX2 Controller 2 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the inductor and the negative side of the boost capacitor to LX2. 22 DH2 Controller 2 High-Side Gate Driver Output. DH2 drives the gate of the high-side MOSFET. 23 BST2 Controller 2 High-Side Gate Driver Supply. Connect BST2 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 24 CSN2 Controller 2 Negative Current-Sense Input. Connect CSN2 to the synchronous MOSFET drain (connected to LX2). When using a current-sense resistor, connect CSN2 to the junction of the low-side MOSFET’s source and the current-sense resistor. See Figure 11. 25 CSP2 Controller 2 Positive Current-Sense Input. Connect CSP2 to the synchronous MOSFET source (connected to PGND2). When using a current-sense resistor, connect CSP2 to the PGND2 end of the current-sense resistor. 26 ILIM2 Controller 2 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM2, from ILIM2 to SGND to program the valley current-limit threshold from 50mV to 300mV. ILIM2 sources 20µA out to RILIM2. The resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense resistor, connect a resistive divider from REG to ILIM2 to SGND to set the valley current limit. See Figure 11. 27 COMP2 Controller 2 Error Transconductance Amplifier Output. Connect COMP2 to the compensation feedback network. 28 EN/TRACK2 Controller 2 Enable/Tracking Input. See Figure 2. When sequencing, EN/TRACK2 must be above 1.24V for the PWM controller 2 to start. Coincident tracking—connect the same resistive divider used for FB2, from Output 1 to EN/TRACK2 to SGND. Ratiometric tracking—connect EN/TRACK2 to analog ground. 29 FB2 30 PGOOD2 Controller 2 Power-Good Output. Open-drain PGOOD2 output goes high impedance (releases) when FB2 is above 0.925 x VFB = 0.555V. 31 PGOOD3 Controller 3 Power-Good Output. Open-drain PGOOD3 output goes high impedance (releases) when FB3 is above 0.925 x VFB = 0.555V. 32 FB3 Maxim Integrated Controller 2 Low-Side Gate Driver Output. DL2 is the gate driver output for the synchronous MOSFET. Controller 2 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode. Connect at minimum, a 0.1µF ceramic capacitor from DREG2 to PGND2. Controller 2 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to SGND to set the output voltage. The FB2 voltage regulates to VFB (0.6V). Controller 3 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to SGND to set the output voltage. The FB3 voltage regulates to VFB (0.6V). 11 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Pin Description (continued) PIN 12 NAME FUNCTION 33 EN/TRACK3 Controller 3 Enable/Tracking Input. See Figure 2. When sequencing, EN/TRACK3 must be above 1.24V for the PWM controller 3 to start. Coincident tracking—connect the same resistive divider used for FB3, from Output 1 to EN/TRACK3 to SGND. Ratiometric tracking—connect EN/TRACK3 to analog ground. 34 COMP3 Controller 3 Error Transconductance Amplifier Output. Connect COMP3 to the compensation feedback network. 35 ILIM3 Controller 3 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM3, from ILIM3 to SGND to program the valley current-limit threshold from 50mV to 300mV. ILIM3 sources 20µA out to RILIM3. The resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense resistor, connect a resistive divider from REG to ILIM3 to SGND to set the valley current limit. See Figure 11. 36 CSP3 Controller 3 Positive Current-Sense Input. Connect CSP3 to the synchronous MOSFET source (connected to PGND3). When using a current-sense resistor, connect CSP3 to the PGND3 end of the current-sense resistor. 37 CSN3 Controller 3 Negative Current-Sense Input. Connect CSN3 to the synchronous MOSFET drain (connected to LX3). When using a current-sense resistor, connect CSN3 to the junction of low-side MOSFET’s source and the current-sense resistor. See Figure 11. 38 BST3 Controller 3 High-Side Gate Driver Supply. Connect BST3 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 39 DH3 Controller 3 High-Side Gate Driver Output. DH3 drives the gate of the high-side MOSFET. 40 LX3 Controller 3 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the inductor and the negative side of the boost capacitor to LX3. 41 DREG3 42 DL3 43 PGND3 44 SYNC Synchronization Input. Drive with a frequency at least 20% higher than three times the frequency programmed using the RT pin. The switching frequency is 1/3 the SYNC frequency. Connect SYNC to SGND when not used. 45 SGND Analog Ground Connection. Connect SGND and PGND_ together at one point near the input bypass capacitor return terminal. 46 RT 47 PHASE Phase Select Input. Connect PHASE to SGND for 120° out-of-phase operation between the controllers. Connect to REG for in phase operation. 48 RESET RESET Output. Open-drain RESET output releases after all PGOODs are released and timeout programmed by CT finishes. — EP Controller 3 Low-Side Gate Driver Supply. Connect externally to REG and anode of the boost diode. Connect a minimum of 0.1µF ceramic capacitor from DREG3 to PGND3. Controller 3 Low-Side Gate Driver Output. DL3 is the gate driver output for the synchronous MOSFET. Controller 3 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of the synchronous MOSFET, and the output filter capacitor’s return to PGND3. Connect externally to SGND at a single point near the input capacitor return terminal. Oscillator Timing Resistor Connection. Connect a 500kΩ to 45kΩ resistor from RT to SGND to program the switching frequency from 200kHz to 2.2MHz. Exposed Pad. Solder the exposed pad to a large SGND plane. Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Functional Diagrams PWM CONTROLLER 1 SEL IN EN1 CT RESET 1.24VON 1.12VOFF RESET TIMEOUT CONFIG SELECTOR LDO MAX15003 REG EN 1.24V SGND SEQ_ PGPD_ SHDN SHDN 0.6V REF CSP1 SEQ_ VREGOK EN1 CSN1 DOWN1 VREF DIGITAL SOFT-START AND SOFT-STOP OVL CONFIG OVL1 VR1 IMAX1 RES OVERLOAD MANAGEMENT E/A CLK1 OVL_ CURRENTLIMIT SET CLK1 ILIM1 BST1 FB1 DH1 R SET DOMINANT COMP1 SYNC RT PHASE CPWM EN OSC LX1 Q DREG1 S RAMP DL1 LEVEL CLK1 SHIFT CLK2 CLK3 PGND1 0.925 x VREF PGPD1 FB1 PGOOD1 Maxim Integrated 13 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Functional Diagrams (continued) PWM CONTROLLERS 2 AND 3 EN1 1.24VON 1.12VOFF MAX15003 CSP2/3 SEQ_ SEQ_ VREF EN CONFIG DOWN2/3 DIGITAL SOFT-START AND SOFT-STOP EN_ SHDN EN2/3 CSN2/3 OVL CONFIG OVL_ CURRENTLIMIT SET CLK2/3 SEL_ OVL2/3 RES OVERLOAD IMAX2/3 MANAGEMENT VREF VR2/3 EN/ TRACK2/3 E/A CLK2/3 BST2/3 FB2/3 DH2/3 R COMP2/3 CPWM CLK2/3 ILIM2/3 RAMP LEVEL SHIFT CLK2/3 0.925 x VREF LX2/3 Q SET DOMINANT DREG2/3 S DL2/3 PGND2/3 PGPD2/3 FB2/3 PGOOD2/3 Detailed Description The MAX15003 is a triple-output, pulse-width-modulated (PWM), step-down, DC-DC controller with tracking and sequencing options. The device operates over the input voltage range of 5.5V to 23V or 5V ±10%. Each PWM controller provides an adjustable output down to 0.6V and delivers up to 15A load current with excellent load and line regulation. Each of the MAX15003 PWM sections utilizes a voltage-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 200kHz to 2.2MHz and can be synchronized to an external clock signal using the SYNC input. Each converter, operating at up to 2.2MHz with 120° out-of-phase, increases the input capacitor ripple frequency up to 6.6MHz, reducing the RMS input ripple current and the size of the input bypass capacitor requirement significantly. 14 The MAX15003 provides either coincident tracking, ratiometric tracking, or sequencing. This allows tailoring of the power-up/power-down sequence depending on the system requirements. The MAX15003 features lossless valley-mode currentlimit protection by monitoring the voltage drop across the synchronous MOSFET’s on-resistance to sense the inductor current. The MAX15003’s internal current source exhibits a positive temperature coefficient to help compensate for the MOSFET’s temperature coefficient. Use an external voltage-divider when a more precise current limit is desired. This divider along with a precision shunt resistor allows for more accurate current limit. The MAX15003 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converters. The power-on reset (RESET) with adjustable timeout period monitors all three outputs and provides a RESET signal to a system controller/processor indicating when all outputs are within regulation. Protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Internal Undervoltage Lockout (UVLO) VIN must exceed the default UVLO threshold before any operation can commence. The UVLO circuitry keeps the MOSFET drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. The UVLO rising threshold is 4.05V with 350mV hysteresis. Digital Soft-Start/Soft-Stop The MAX15003 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating outputvoltage overshoot. Soft-start begins after VIN exceeds the undervoltage lockout threshold and the enable input is above 1.24V. The soft-start circuitry gradually ramps up the reference voltage. This controls the rate of rise of the output voltage and reduces input surge currents during startup. The soft-start duration is 2048 clock cycles. The output voltage is incremented through 64 equal steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load. Soft-stop commences when the enable input falls below 1.12V. The soft-stop circuitry ramps down the reference voltage controlling the output voltage rate of fall. The output voltage is decremented through 64 equal steps in 2048 clock cycles. Internal Linear Regulator (REG) REG is the output terminal of a 5V LDO powered from IN that provides power to the IC. Connect REG externally to DREG to provide power for the low-side MOSFET gate driver. Bypass REG to SGND with a minimum 2.2µF ceramic capacitor. Place the capacitor physically close to the MAX15003 to provide good bypassing. REG is intended for powering only the internal circuitry and should not be used to supply power to external loads. REG can source up to 120mA. This current, I REG , includes quiescent current (IQ) and gate drive current (IDREG): IREG = IQ + [fSW x Σ(QGHS_ + QGLS_)] where QGHS_ to QGLS_ are the total gate charge of each of the respective high- and low-side external MOSFETs at VGATE = 5V. fSW is the switching frequency of the converter and IQ is the quiescent current of the device at the switching frequency. MOSFET Gate Drivers low-side MOSFET switches on, high peak current is drawn from DREG for a short amount of time. Adding an RC filter (1Ω to 3.3Ω and 2.2µF in parallel to 0.1µF ceramic capacitors are typical) from REG to DREG_ filters out high-peak currents. BST_ supplies the power for the high-side MOSFET drivers. Connect the bootstrap diode from BST_ to DREG_ (anode at DREG_ and cathode at BST_). Connect a bootstrap 0.1µF or higher ceramic capacitor between BST_ and LX_. Though not always necessary, it may be useful to insert a small resistor (4.7Ω to 22Ω) in series with the BST_ pin and the cathode of the bootstrap diode for additional noise immunity. The high-side (DH_) and low-side (DL_) drivers drive the gates of the external n-channel MOSFETs. The drivers’ 2A peak source- and sink-current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced switching losses. The gate driver circuitry also provides a break-beforemake time (20ns typ) to prevent shoot-through currents during transition. Oscillator/Synchronization Input/Phase Staggering (RT, SYNC, PHASE) Use an external resistor at RT to program the MAX15003 switching frequency from 200kHz to 2.2MHz. Choose the appropriate resistor at RT to calculate the desired output switching frequency (fSW): fSW (Hz) = 1011/(RRT + 1750) (Ω) Connect an external clock at SYNC for external clock synchronization. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by RRT. This maintains output regulation even with intermittent SYNC signals. For proper synchronization, the external frequency must be at least 20% higher than three times the frequency programmed through the RT input. The switching frequency is 1/3 the SYNC frequency. Connect SYNC to SGND when not used. Connect PHASE to SGND for 120° out-of-phase operation between the controllers. Connect PHASE to REG for in-phase operation. DREG_ is the supply input for the low-side MOSFET driver. Connect DREG_ to REG externally. Everytime the Maxim Integrated 15 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Coincident/Ratiometric Tracking (SEL, EN/TRACK_) VOUT1 The enable/tracking input in conjunction with digital softstart and soft-stop provides coincident/ratiometric tracking (see Figure 1). Track an output voltage by connecting a resistive divider from the output being tracked to the enable/tracking input. For example, for VOUT2 to coincidentally track VOUT1, connect the same resistive divider used for FB2, from OUT1 to EN/TRACK2 to SGND. See Figure 2 and the Coincident Startup and Coincident Shutdown graphs in the Typical Operating Characteristics. Track ratiometrically by connecting EN/TRACK_ to SGND. This synchonizes the soft-start and soft-stop of all the controllers’ references, and hence their respective output voltages track ratiometrically. See Figure 2 and the Typical Operating Characteristics (Ratiometric Startup and Ratiometric Shutdown graphs). Connect SEL to REG to configure as a triple tracker. When the MAX15003 converter is configured as a tracker, the output short-circuit fault situations at master or slave outputs are handled carefully so that either the master or slave output does not stay on when the other outputs are shorted to the ground. When the slave is shorted and enters in hiccup mode, both the master and the other slave soft-stop. When the master is shorted and the part enters in hiccup mode, the slaves ratiometrically soft-stop. Coming out of the hiccup, all outputs soft-start coincidently or ratiometrically depending on their initial configuration. See the Typical Operating Characteristics for the output behaviour during the fault conditions. During power-off, when the input falls below its UVLO, the output voltages fall down at the rate depending on the respective output capacitor and load. Output-Voltage Sequencing (SEL, EN/TRACK_, PGOOD) Referring to Figure 1c, when sequencing, the enable/tracking input must be above 1.24V for each PWM controller to start. The PGOOD_ outputs and EN/TRACK_ inputs can be daisy-chained to generate power sequencing. Open-drain PGOOD_ outputs go high impedance 16 VOUT2 VOUT3 SOFT-START SOFT-STOP A) COINCIDENT TRACKING OUTPUTS VOUT1 VOUT2 VOUT3 SOFT-START SOFT-STOP B) RATIOMETRIC TRACKING OUTPUTS VOUT1 VOUT2 VOUT3 SOFTSTART SOFT-STOP C) SEQUENCED OUTPUTS Figure 1. Graphical Representation of Coincident Tracking, Ratiometric Tracking, or PGOOD Sequencing when FB_ is above the PGOOD_ threshold (555mV typ). Connect a resistive divider from the power-good output to the enable/tracking input to SGND to set when each controller will start. See Figure 2. Connect SEL to SGND to configure as a triple sequencer. Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing COINCIDENT TRACKING RATIOMETRIC TRACKING PGOOD SEQUENCING VIN VIN VIN EN1 EN1 EN1 VOUT1 EN/TRACK2 REG RA EN/TRACK2 EN/TRACK3 RC PGOOD1 RB EN/TRACK2 SEL REG REG EN/TRACK3 VOUT2 VOUT3 RA FB2 RD RC FB3 RB SEL PGOOD2 EN/TRACK3 RD SEL REG Figure 2. Ratiometric Tracking, Coincident Tracking, PGOOD Sequencing Configurations Error Amplifier The output of the internal error transconductance amplifier (COMP_) is provided for frequency compensation (see the Compensation Design Guidelines section). The inverting input is FB_ and the output COMP_. The error transamplifier has an 80dB open-loop gain and a 10MHz GBW product. Output Short-Circuit Protection (Hiccup Mode) The current-limit circuit employs a valley current-limiting algorithm that either uses a shunt or the synchronous MOSFET’s on-resistance as the current-sensing element. Once the high-side MOSFET turns off, the voltage across the current-sensing element is monitored. If this voltage does not exceed the current-limit threshold, Maxim Integrated the high-side MOSFET turns on normally at the start of the next cycle. If the voltage exceeds the current-limit threshold just before the beginning of a new PWM cycle, the controller skips that cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to decrease because the on-time of the low-side MOSFET extends beyond a clock cycle. If the current-limit threshold is exceeded for more than eight cumulative clock cycles (NCL), the device shuts down (both DH and DL are pulled low) for 4096 clock cycles (hiccup timeout) and then restarts with a softstart sequence. If three consecutive cycles pass without a current-limit event, the count of NCL is cleared (see Figure 3). Hiccup mode protects against a continuous output short circuit. 17 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing CURRENT LIMIT IN COUNT OF 8 NCL INITIATE HICCUP TIMEOUT NHT CLR The minimum input voltage is limited by the maximum duty cycle and is calculated using the following equation: VIN(MIN) ≥ ( VOUT 1 − t OFF(MIN) × fSW ) where tOFF(MIN) typically is equal to 150ns. Inductor Selection IN COUNT OF 3 NCLR CLR Figure 3. Hiccup-Mode Block Diagram PWM Controller Design Procedures Setting the Switching Frequency Connect a 500kΩ to 45kΩ resistor from RT to SGND to program the switching frequency from 200kHz to 2.2MHz. Calculate the switching frequency using the following equation: fSW = 1011/(RRT + 1750) Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I 2 R losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. Effective Input Voltage Range Although the MAX15003 converters can operate from input supplies ranging from 5.5V to 23V, the input voltage range can be effectively limited by the MAX15003 duty-cycle limitations for a given output voltage. The maximum input voltage is limited by the minimum ontime (tON(MIN)): VIN(MAX) ≤ where tON(MIN) is 75ns. 18 VOUT t ON(MIN) × fSW Three key inductor parameters must be specified for operation with the MAX15003: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (∆IP-P). Higher ∆IP-P allows for a lower inductor value. A lower inductance value minimizes size and cost and improves large-signal and transient response. However, efficiency is reduced due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. A higher inductance increases efficiency by reducing the ripple current, however resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good rule of thumb is to choose ∆IP-P equal to 30% of the full load current. Calculate the inductance using the following equation: L = VOUT (VIN − VOUT ) VIN × fSW × ∆IP −P VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency is programmable between 200kHz and 2.2MHz (see Oscillator/Synchronization Input/Phase Staggering (RT, SYNC, PHASE) section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output current ripple is acceptable. The inductor saturation current (ISAT) is also important to avoid runaway current during continuous output short-circuit conditions. Select an inductor with an ISAT specification higher than the maximum peak current. Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Input Capacitor Selection The discontinuous input current of the buck converter causes large input ripple currents, and therefore, the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage ripple within design requirements. The 120° ripple phase operation increases the frequency of the input capacitor ripple current to thrice the individual converter switching frequency. When using ripple phasing, the worst-case input capacitor ripple current is when the one converter with the highest output current is on. The input voltage ripple comprises ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of ∆VQ and ∆VESR which peaks at the end of the on-cycle. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ESR = ∆VESR ∆IP −P ⎞ ⎛ ⎜ ILOAD(MAX) + ⎟ ⎝ 2 ⎠ ⎛V ⎞ ILOAD(MAX) × ⎜ OUT ⎟ ⎝ VIN ⎠ CIN = ∆VQ × fSW where: ∆IP −P = (VIN − VOUT ) × VOUT VIN × fSW × L ILOAD(MAX) is the maximum output current, ∆IP-P is the peak-to-peak inductor current, and fSW is the switching frequency. For the condition with only one converter is on, calculate the input ripple current using the following equation: ICIN(RMS) =ILOAD(MAX) × VOUT × ( VIN − VOUT ) VIN The MAX15003 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. At lower input voltage, additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during transient loading. Output Capacitor Selection The allowed output voltage ripple and the maximum deviation of the output voltage during load steps determine Maxim Integrated the required output capacitance and its ESR. The output ripple is mainly composed of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the voltage drop across the equivalent series resistance of the output capacitor). The equations for calculating the output capacitance and its ESR are: COUT = ESR = ∆IP −P 8 × ∆VQ × fSW 2 × ∆VESR ∆IP −P ∆VESR and ∆VQ are not directly additive because they are out of phase from each other. If using ceramic capacitors, which generally have low ESR, ∆VQ dominates. If using electrolytic capacitors, ∆V ESR dominates. The allowable deviation of the output voltage during fast load transients also affects the output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the gain bandwidth of the converter (see the Compensation Design Guidelines section). The resistive drop across the output capacitor’s ESR, the drop across the capacitor’s ESL, and the capacitor discharge cause a voltage droop during the load-step (ISTEP). Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for better load-transient and voltage-ripple performance. Surfacemount capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ∆VESR ISTEP ×t I COUT = STEP RESPONSE ∆VQ ESR = ESL = ∆VESL × t STEP ISTEP where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller. 19 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Setting the Current Limit The MAX15003 uses a valley current-sense method for current limiting. The voltage drop across the low-side MOSFET due to its on-resistance is used to sense the inductor current. The voltage drop (VVALLEY) across the low-side MOSFET at the valley point and at ILOAD is: ⎛ VVALLEY = RDS(ON) × ⎜ ILOAD ⎝ − ∆IP − P ⎞ 2 ⎟⎠ VALLEY CURRENT-LIMIT THRESHOLD AND RDS(ON) vs. TEMPERATURE 1.4 MAX15003 fig04 1.5 VILIM AND RDS(ON) (NORMALIZED) Connect a 25kΩ to 150kΩ resistor, RILIM, from ILIM to SGND to program the valley current-limit threshold (VCL) from 50mV to 300mV. ILIM sources 20µA out to RILIM. The resulting voltage divided by 10 is the valley current-limit threshold. RDS(ON) 1.3 1.2 1.1 VILIM 1.0 0.9 0.8 0.7 0.6 RILIM = 25.5kΩ 0.5 RDS(ON) is the on-resistance of the low-side MOSFET, ILOAD is the rated load current, and ∆IP-P is the peakto-peak inductor current. The RDS(ON) of the MOSFET varies with temperature. Calculate the RDS(ON) of the MOSFET at its operating junction temperature at full load using the MOSFET datasheet. To compensate for this temperature variation, the 20µA ILIM reference current has a temperature coefficient of 3333ppm/°C. This allows the valley current-limit threshold (VCL) to track and partially compensate for the increase in the synchronous MOSFET’s RDS(ON) with increasing temperature. Use the following equation to calculate RILIM: -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) Figure 4. Current-Limit Trip Point and VRDS(ON) vs. Temperature Compensation Design Guidelines Power MOSFET Selection The MAX15003 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by differentially comparing the “sampled” output voltage against a fixed reference. The subsequent error voltage that appears at the error amplifier output (COMP) is compared against an internal ramp voltage to generate the required duty cycle of the pulse-width modulator. A second order lowpass LC filter removes the switching harmonics and passes the DC component of the pulsewidth-modulated signal to the output. The LC filter, which has an attenuation slope of -40dB/decade, introduces 180° of phase shift at frequencies above the LC resonant frequency. This phase shift, in addition to the inherent 180° of phase shift of the regulator’s self-governing (negative) feedback system, poses the potential for positive feedback. The error amplifier and its associated circuitry are designed to compensate for this instability to achieve a stable closed-loop system. When choosing the MOSFETs, consider the total gate charge, RDS(ON), power dissipation, the maximum drainto-source voltage and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs that are optimized for high-frequency switching applications. The average gatedrive current from the MAX15003’s output is proportional to the frequency and gate charge required to drive the MOSFET. The power dissipated in the MAX15003 is proportional to the input voltage and the average drive current (see the Power Dissipation section). The basic regulator loop consists of a power modulator (comprises the regulator’s pulse-width modulator, associated circuitry, and LC filter), an output feedback divider, and an error amplifier. The power modulator has a DC gain set by VIN / VRAMP, with a double pole and a single zero set by the output inductance (L), the output capacitance (COUT), and its equivalent series resistance (ESR). A second, higher frequency zero also exists, which is a function of the output capacitor’s ESR and ESL); though only taken into account when using very high-quality filter components and/or frequencies of operation. ∆I ⎛ ⎞ RDS(ON) × ⎜ ICL(MAX) − P −P ⎟ ×10 ⎝ 2 ⎠ RILIM = 20 ×10 −6 ⎡1+ 3.333 ×10 −3 (T − 25°C)⎤ ⎣⎢ ⎦⎥ Figure 4 illustrates the effect of the MAX15003 ILIM reference current temperature coefficient to compensate for the variation of the MOSFET RDS(ON) over the operating junction temperature range. 20 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Below are equations that define the power modulator: VIN VRAMP 1 GMOD(DC) = fLC = 2π × L × COUT 1 fZERO,ESR = 2π ×ESR× COUT fZERO,ESL = ESR 2π ×ESL The switching frequency is programmable between 200kHz and 2.2MHz using an external resistor at RT. Typically, the crossover frequency (fCO), which is the frequency when the system’s closed-loop gain is equal to unity crosses the 0dB axis—should be set at or below one-tenth the switching frequency (fSW/10) for stable, closed-loop response. The MAX15003 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use aluminum electrolytic capacitors and for space-sensitive applications, use low-ESR tantalum or multilayer ceramic chip (MLCC) capacitors at the output. The higher switching frequencies of the MAX15003 allow the use of MLCC as the primary filter capacitor(s). First, select the passive and active power components that meet the application’s output ripple, component size, and component cost requirements. Second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below. Closed-Loop Response and Compensation of Voltage-Mode Regulators The power modulator’s LC lowpass filter exhibits a variety of responses, depending on the value of the L and C (and their parasitics). One such response is shown in Figure 5a. In this example the power modulator’s uncompensated crossover is approximately 1/6th the desired crossover frequency, fCO. Note also, the uncompensated roll-off through the 0dB plane follows the double-pole, -40dB/decade slope and approaches 180° of phase shift, indicative of a potentially unstable system. Together with the inherent 180° of phase delay in the negative feedback system, this may lead to near 360° or positive feedback—an unstable system. The desired (compensated) roll-off follows a -20dB/decade slope (and commensurate 90° of phase shift), and, in this example, occurs at approximately 6x the uncompensated crossover frequency, fCO. In this example, a Type II compensator provides for stable closed-loop operation, leveraging the +20dB/decade slope of the capacitor’s ESR zero (see Figure 5b). POWER MODULATOR (LARGE, BULK OUTPUT CAPACITOR(S)) GAIN (REAL, ASYMPTOTIC/ PHASE RESPONSE vs. FREQUENCY MAX15003 fig05a fLC 60 45 |GMOD| -45 fZERO,ESR -90 -40 MAGNITUDE (dB) < GMOD 180 135 40 0 PHASE (DEGREES) |GMOD| 0 -20 MAX15003 fig05b 80 <GEA 20 MAGNITUDE (dB) 90 90 fZERO,ESR |GEA| 20 0 45 0 fLC -20 -45 < GMOD -40 fZERO,ESL -90 -135 -60 PHASE (DEGREES) 40 POWER MODULATOR (LARGE, BULK OUTPUT CAPACITOR(S)) AND TYPE II COMPENSATION GAIN (ASYMPTOTIC)/PHASE RESPONSE vs. FREQUENCY fZERO,ESL -60 -135 fCO -80 10 100 1k 10k 100k 1M -180 10M FREQUENCY (Hz) Figure 5a. Power Modulator Gain and Phase Response (Large, Bulk COUT) Maxim Integrated -80 10 100 1k 10k 100k 1M -180 10M FREQUENCY (Hz) Figure 5b. Power Modulator (Large, Bulk COUT) and Type II Compensator Responses 21 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing The Type II compensator’s mid-frequency gain (approximately 18dB shown here) is designed to compensate for the power modulator’s attenuation at the desired crossover frequency, fCO (GE/A + GMOD = 0dB at fCO). In this example, the power modulator’s inherent -20dB/decade roll-off above the ESR zero (fZERO, ESR) is leveraged to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5b, the net result is a 6x increase in the regulator’s gain bandwidth while providing greater than 75° of phase margin (the difference between G E/A and G MOD respective phases at crossover, fCO). Other filter schemes pose their own problems. For instance, when choosing high-quality filter capacitor(s), e.g., MLCCs, and an inductor with minimal parasitics, the inherent ESR zero may occur at a much higher frequency, as shown in Figure 5c. As with the previous example, the actual gain and phase response is overlaid on the power modulator’s asymptotic gain response. One readily observes the more dramatic gain and phase transition at or near the power modulator’s resonant frequency, fLC, versus the gentler response of the previous example. This is due to the component’s lower parasitics leading to the higher frequency of the inherent ESR zero of the output capacitor. In this example, the desired crossover frequency occurs below the ESR zero frequency. In this example, a compensator with an inherent midfrequency double-zero response is required to mitigate the effects of the filter’s double-pole. Such is available with the Type III topology. POWER MODULATOR (HIGH-QUALITY OUTPUT CAPACITORS (S)) GAIN (REAL, ASYMPTOTIC)/ PHASE RESPONSE vs. FREQUENCY POWER MODULATOR (HIGH-QUALITY OUTPUT CAPACITOR(S)) AND TYPE III COMPENSATOR GAIN (ASYMPTOTIC)/ PHASE RESPONSE vs. FREQUENCY 90 40 0 0 -20 -45 |GMOD| -40 -90 fZEROES fZEROES -80 10 100 1k 10k 100k 1M -135 -180 10M FREQUENCY (Hz) Figure 5c. Power Modulator Gain and Phase Response (HighQuality COUT) 22 203 135 fLC 20 68 0 fZEROES |GMOD| -20 -60 -135 -203 fCO fZEROES -80 10 100 1k 0 -68 < GMOD -40 -60 270 |GEA| MAGNITUDE (dB) MAGNITUDE (dB) |GMOD| < GEA 60 45 fLC PHASE (DEGREES) 20 MAX15003 fig05d 80 |GMOD| PHASE (DEGREES) MAX15003 fig05c 40 As demonstrated in Figure 5d, the Type III’s midfrequency double-zero gain (exhibiting a +20dB/ decade slope, noting the compensator’s pole at the origin) is designed to compensate for the power modulator’s double-pole -40dB/decade attenuation at the desired crossover frequency, fCO (again, GE/A + GMOD = 0dB at fCO). (See Figure 5d). In the above example, the power modulator’s inherent (mid-frequency) -40dB/decade roll-off is mitigated by the mid-frequency double zero’s +20dB/decade gain to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5d, the net result is an approximate doubling in the regulator’s gain bandwidth while providing greater than 60° of phase margin (the difference between GE/A and GMOD respective phases at crossover, fCO). Design procedures for both Type II and Type III compensators are shown below. 10k 100k 1M -270 10M FREQUENCY (Hz) Figure 5d. Power Modulator (High-Quality COUT) and Type III Compensator Responses Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Type II: Compensation When fCO > fZERO, ESR 1) Calculate the fZERO,ESR and LC double pole, fLC: fZERO,ESR = VOUT fLC = R1 - COMP gM VREF R2 1 2π × L × COUT 2) Calculate the unity-gain crossover frequency as: f fCO ≤ SW + RF CF 1 2π ×ESR× COUT 10 CCF 3) Determine RF from the following: V (2π × fCO ×L)VOUT RF = RAMP VFB × VIN × gm ×ESR Figure 6a. Type II Compensation Network Note: RF is derived by setting the total loop gain at crossover frequency to unity, e.g., GEA(fCO) x GM(fCO) = 1V/V. The transconductance error amplifier gain is GEA(fCO) = gM x RF while the modulator gain is: GAIN (dB) GMOD (fCO ) = VIN V ESR × × FB VRAMP 2π × fCO ×L VOUT The total loop gain can be expressed logarithmically as follows: 1ST ASYMPTOTE GMODVREFVOUT-1(ωCF)-1 [ ] 20log10 gmRF + 2ND ASYMPTOTE GMODVREFVOUT-1RF 1ST POLE (AT ORIGIN) 1ST ZERO (RFCF)-1 ⎡ ⎤ ESR× VIN × VFB ⎥ = 0 dB 20log10 ⎢ ⎢⎣ (2π × fCO ×L ) × VOUT × VRAMP ⎥⎦ 3RD ASYMPTOTE GMODVREFVOUT-1(ωCCF)-1 2ND POLE (RFCCF)-1 ω(rad/s) where V RAMP is the peak-to-peak ramp amplitude equal to 2V. 4) Place a zero at or below the LC double pole, fLC: Figure 6b. Type II Compensation Network Response When the fZERO,ESR is lower than fCO and close to fLC, a Type II compensation network provides the necessary closed-loop response. The Type II compensation network provides a mid-band compensating zero and high-frequency pole (see Figures 6a and 6b). R F C F provides the mid-band zero f MID,ZERO , and RFCCF provides the high-frequency pole. Use the following procedure to calculate the compensation network components. CF = 1 2π ×RF × fLC 5) Place a high-frequency pole at or below fP = 0.5 x fSW: CCF = 1 π ×RF × fSW 6) Choose an appropriately sized R1 (connected from OUT_ to FB_, start with a 10kΩ). Once R1 is selected, calculate R2 using the following equation: V FB R2 = R1 × VOUT − VFB where VFB = 0.6V. Maxim Integrated 23 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Type III: Compensation When fCO < fZERO, ESR As indicated above, the position of the output capacitor’s inherent ESR zero is critical in designing an appropriate compensation network. When low-ESR ceramic output capacitors are used, the ESR zero frequency (f ZERO, ESR ) is usually much higher than unity crossover frequency (fCO). In this case, a Type III compensation network is recommended (see Figure 7a). Use the following procedure to calculate the compensation network components. 1) Select a crossover frequency, fCO: f fCO ≤ SW 10 2) Calculate the LC double-pole frequency, fLC : fLC = VOUT CCF RI R1 3) Select RF ≥ 10kΩ. 4) Place a zero fZ1 = CF RF 1 at 0.75 x fLC where 2π x RF x CF CI R2 VREF + 1 2π ×RF × 0.75 × fLC 5) Calculate CI for a target unity-gain crossover frequency, fC: CI = Figure 7a. Type III Compensation Network 2π × fCO ×L × COUT × VRAMP VIN ×RF Note: CI is derived by setting the total loop gain at crossover frequency to unity, e.g., G EA (f CO ) x G MOD (f CO ) = 1V/V. The total loop gain can be expressed logarithmically as follows: GAIN (dB) 4TH ASYMPTOTE RFRI-1 3RD ASYMPTOTE ωRFCI 5TH ASYMPTOTE (ωRICCF)-1 1ST ASYMPTOTE (ωRICF)-1 2ND ASYMPTOTE (RFRI)-1 1ST POLE (AT ORIGIN) 1ST ZERO 2ND POLE (RFCF)-1 (RICI)-1 2ND ZERO (RICI)-1 20 × log10 [2π × fCO × RF × CI ] + ⎡ ⎤ GMOD(DC) ⎥ = 0dB 20 × log10 ⎢ 2 ⎢ 2π × f ⎥ × × L C ( ) CO OUT ⎦ ⎣ 6) Place a second zero, fZ2, at or below fLC thereby determining R1. 3RD POLE ω(rad/sec) (RFCCF)-1 Figure 7b. Type III Compensation Network Response As shown in Figure 7b, a Type III compensation network introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole at the origin, two zeros, and higher frequency poles. The locations of the zeros and poles should be such that the phase margin peaks at fCO. Set the ratios of fCO-to-fZ and fP-to-fCO equal to one another, e.g., fCO fP = is a good number to get about = 5 fZ fCO 60° of phase margin at fCO. Whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. 24 CF = COMP gM 1 2π× L × COUT R1 = 1 2π × fZ2 × CI 1 7) Place a pole (fP1 = ), at or below fZERO,ESR. (2π x R1 x CI) R1 = 1 2π × fZERO,ESR × CI 1 ) at or below 2π x RF x CCF one-half the switching frequency. 8) Place a second pole (fP2 = CCF = 1 π × fSW ×RF 9) Calculate R2 using the following equation: V FB R2 = R1 × VOUT − VFB where VFB = 0.6V. Maxim Integrated 34kΩ 34kΩ VOUT3 1.15kΩ 2.2Ω 470pF 10kΩ COUT 120µF (2) 11kΩ 25.5kΩ 470nF IRF7807Z 22µF 47pF 1.2nF NTMFS4835N 100nF 0.1µF IN DREG2 PGOOD3 ILIM3 COMP3 FB3 EN/TRACK3 PGND3 CSP3 DL3 CSN3 LX3 DH3 BST3 DREG3 0.1µF LX2 PHASE DH2 SEL 2.2µF CSN2 SYNC (1/2) IRF7904 100µF 165kΩ MAX15003 CSP2 10kΩ 750Ω 19.1kΩ 1nF 2.2µF PGND2 VOUT2 DL2 RT SGND REG PGND SGND 150µF/16V 11kΩ 1.8µF 0.022µF FB2 CIN COMP2 10kΩ EP 47pF 6.04kΩ RESET Maxim Integrated 25.5kΩ PGOOD1 ILIM1 COMP1 FB1 EN1 PGND1 CSP1 DL1 CSN1 LX1 DH1 BST1 DREG1 PGOOD2 IN 1800pF 47pF (1/2) FDS6982A5 (1/2) FDS6982A5 0.1µF 25.5kΩ 13kΩ 100µF 3.3µF 22µF 2.2Ω 10kΩ 1200nF 750kΩ 4.22kΩ 19.1kΩ VOUT1 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Typical Operating Circuits Figure 8. Coincident Triple Tracker with Lossless Current Sense 25 ILIM2 CT EN/TRACK2 BST2 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing PGOOD1 ILIM1 COMP1 FB1 EN1 PGND1 CSP1 DL1 CSN1 LX1 DH1 BST1 DREG1 VOUT1 Typical Operating Circuits (continued) PGOOD2 ILIM2 EP RESET COMP2 FB2 CT EN/TRACK2 SGND MAX15003 PGND2 REG RT CSP2 DL2 SYNC LX2 PHASE DH2 SEL VOUT2 CSN2 PGOOD3 ILIM3 COMP3 FB3 PGND3 CSP3 DL3 IN VOUT3 PGND CIN IN SGND COUT CSN3 LX3 DH3 BST3 DREG2 DREG3 EN/TRACK3 BST2 Figure 9. Triple Sequencer with Lossless Current Sense 26 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing PGOOD1 ILIM1 COMP1 FB1 EN1 PGND1 CSP1 DL1 CSN1 LX1 DH1 BST1 DREG1 VOUT1 Typical Operating Circuits (continued) PGOOD2 ILIM2 COMP2 EP RESET FB2 CT EN/TRACK2 SGND MAX15003 PGND2 REG RT CSP2 DL2 SYNC LX2 PHASE DH2 SEL VOUT2 CSN2 PGOOD3 ILIM3 COMP3 FB3 PGND3 CSP3 DL3 IN VOUT3 PGND CIN IN SGND COUT CSN3 LX3 DH3 BST3 DREG2 DREG3 EN/TRACK3 BST2 Figure 10. Coincident Dual Tracker and a Sequencer with Lossless Current Sense Maxim Integrated 27 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing PGOOD1 ILIM1 COMP1 FB1 EN1 CSP1 PGND1 CSN1 DL1 LX1 DH1 BST1 DREG1 VOUT1 Typical Operating Circuits (continued) PGOOD2 ILIM2 COMP2 EP RESET FB2 EN/TRACK2 CT PGND2 SGND CSP2 MAX15003 REG RT DL2 LX2 PHASE DH2 SEL VOUT2 CSN2 SYNC PGOOD3 ILIM3 COMP3 FB3 PGND3 CSP3 CSN3 IN VOUT3 PGND CIN IN SGND COUT DL3 LX3 DH3 BST3 DREG2 DREG3 EN/TRACK3 BST2 Figure 11. Ratiometric Triple Tracker with Accurate Valley-Mode Current Sense 28 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing PWM Controller Applications Information Power Dissipation The 48-pin TQFN thermally enhanced package can dissipate up to 3.08W. Calculate power dissipation in the MAX15003 as a product of the input voltage and the total REG output current (IREG). IREG includes quiescent current (I Q ) and the total gate drive current (IDREG): PD = VIN x IREG IREG = IQ + [fSW x (QG1 + QG2 + QG3 + QG4 + QG5 + QG6)] where QG1 to QG6 are the total gate charge of the lowside and high-side external MOSFETs. f SW is the switching frequency of the converter and IQ is the quiescent current of the device at the switching frequency. Use the following equation to calculate the maximum power dissipation (PDMAX) in the chip at a given ambient temperature (TA): PDMAX = 38.5 x (150 - TA)……….mW PCB Layout Guidelines Use the following guidelines to layout the switching voltage regulator. 1) Place the IN, REG, and DREG_ bypass capacitors close to the MAX15003. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. Maxim Integrated 3) Keep the current loop formed by the lower switching MOSFET, inductor, and output capacitor short. 4) Keep SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) Run the current-sense lines CSP_ and CSN_ close to each other to minimize the loop area. 6) Avoid long traces between the DREG_ bypass capacitor, low-side driver outputs of the MAX15003, MOSFET gate, and PGND. Minimize the loop formed by the DREG_ bypass capacitor, bootstrap diode, bootstrap capacitor, high-side driver output of the MAX15003, and upper MOSFET gates. 7) Place the bank of output capacitors close to the load. 8) Distribute the power components evenly across the board for proper heat dissipation. 9) Provide enough copper area at and around the switching MOSFETs, and inductor to aid in thermal dissipation. 10) Connect the MAX15003 exposed paddle to a large copper plane to maximize its power dissipation capability. Connect the exposed paddle to SGND. Do not connect the exposed paddle to the SGND pin (pin 45) directly underneath the IC. 11) Use 2oz copper to keep the trace inductance and resistance to a minimum. Thin copper PCBs compromise efficiency because high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. 29 MAX15003 Triple-Output Buck Controller with Tracking/Sequencing CSP2 ILIM2 COMP2 EN/TRACK2 FB2 PGOOD2 PGOOD3 FB3 ILIM3 COMP3 CSP3 TOP VIEW EN/TRACK3 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 CSN2 CSN3 37 24 BST3 38 23 BST2 DH3 39 22 DH2 LX3 40 21 LX2 DREG3 41 20 DREG2 DL3 42 19 DL2 MAX15003 PGND3 43 18 PGND2 SYNC 44 17 PGOOD1 SGND 45 16 FB1 15 EN1 14 COMP1 13 ILIM1 7 8 9 10 11 12 BST1 CSP1 6 CSN1 5 DH1 4 LX1 3 DREG1 2 DL1 1 SEL 48 PGND1 RESET + IN 47 REG 46 CT RT PHASE THIN QFN (7mm x 7mm) Chip Information PROCESS: BiCMOS 30 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 48 TQFN-EP T4877+3 21-0144 90-0129 Maxim Integrated MAX15003 Triple-Output Buck Controller with Tracking/Sequencing Revision History REVISION NUMBER REVISION DATE 0 10/07 Initial release — 1 8/12 Updated MOSFET Gate Drivers section 15 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 31 © 2012 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.