IS31AP4832 DUAL 2.5W AUDIO POWER AMPLIFIER AND STEREO HEADPHONE DRIVER WITH TONE CONTROL AND 3D ENHANCEMENT January 2012 GENERAL DESCRIPTION FEATURES The IS31AP4832 is a monolithic integrated circuit that provides tone (bass and treble) controls as well as a stereo audio power amplifier capable of delivering 2.5W (Typ.) into 4Ω or 1.7W (Typ.) into 8Ω with less than 10% THD with a 5V supply. The IS31AP4832 uses flexible I2C control interface for multiple application requirements. The IS31AP4832 also features 3D sound circuitry which can be externally adjusted via a simple RC network. The headphone amplifier features Output Capacitor-less (OCL) architecture that eliminates the output coupling capacitors required by traditional headphone amplifiers. 3D enhancement Treble and Bass control I2C control interface Thermal shutdown protection Minimum external components Click-and-Pop suppression Micro-power shutdown Software & Hardware control shutdown function QFN-28(4mm × 4mm) package Applications The IS31AP4832 features a 13 step tone control for the headphone and stereo outputs. The device mode select and Tone are controlled through an I2C compatible interface. Cell phones, PDA, MP4,PMP Portable and desktop computers Desktops audio system Multimedia monitors Thermal shutdown protection prevents the device from being damaged during fault conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. TYPICAL APPLICATION CIRCUIT VDD 20K 2.2nF 0.1uF 2.2nF 10uF 30pF 7 0.22uF 20K 1 Left Input Left input 14 12 Left Left Left tone in tone out loop in - left channel tone control + 4,18 L OFF 5 POUTA 3 NOUTB 17 + 20 I2C Reset GND SPEAKER + 9 SDA I2C BUS NOUTA + H VDD ON SPEAKER - Left channel 3D enhance Left loop out 8 I2C interface 10 SCL 16 Left 3D in POUTB 19 HP Logic - 0.68uF + 15 Right input L GND 0.22uF 20K Right channel 3D enhance 5K Right 3D in 21 Right input right channel tone control + - Biass Click/pop suppresion + VOC - H VDD 24 PHONE JACK Shutdown Working 6 Right Right Right loop out tone in tone out SHUTDOWN 100K 30pF 28 27 22 Right loop in Bypass 23 26 11,13,25 GND 1µF 20K 2.2nF Figure 1 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 2.2nF Typical Application Circuit 1 IS31AP4832 PIN CONFIGURATION Right tone in Bypass GND VOC Right loop in Right tone out Pin Configuration (Top View) Right loop out Package 28 27 26 25 24 23 22 Left input 1 21 Right input NC 2 20 I2C Reset POUTA 3 QFN-28 19 POUTB VDD 4 18 VDD NOUTA 5 17 NOUTB SHUTDOWN 6 16 L3Din 15 R3Din 8 9 10 11 12 13 14 Left tone in SDA SCL GND Left loop in GND Left tone out Left loop out 7 Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 2 IS31AP4832 PIN DESCRIPTION No. Pin 1 Left input 2 NC 3 POUTA 4,18 VDD 5 NOUTA 6 ——————————— Description Left channel input. Not connection. Left channel +output in BTL mode. Supply voltage. Left channel –output in BTL mode. It will be into shutdown mode when pull low. 7 SHUTDOWN Left loop out 8 Left tone in 9 SDA The input for the I2C data signal. 10 SCL The input for the I2C clock signal. 11,13,25 GND GND. 12 Left loop in 14 Left tone out 15 R3Din Right channel 3D input. 16 L3Din Left channel 3D input. 17 NOUTB Right channel –output in BTL mode. 19 POUTB Right channel +output in BTL mode. Left channel tone control loop out. Left channel tone control in. Left channel tone control loop in. Left channel tone control out. 20 I2C Reset Reset chip logic and states. Internal pulled low to enable communication; pull high to reset IS31AP4832 to power on default mode and stop communication; a longer than 200ns high pulse can reset the chip. 21 Right input Right channel input. 22 Right tone out 23 Right loop in Right channel tone control loop in. 24 VOC Reference (1/2 VDD) of headphone. 26 Bypass 27 Right tone in Right channel tone control in. 28 Right loop out Right channel tone control loop out. Thermal Pad Connect to GND. Right channel tone control out. Bypass capacitor which provides the common mode voltage. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 3 IS31AP4832 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31AP4832-QFLS2-TR QFN-28, Lead-free 2500 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 4 IS31AP4832 ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA Solder information, vapor phase (60s) infrared (15s) -0.3V ~ +6.0V -0.3V ~ VDD+0.3V 150°C -65°C ~ +150°C −40°C ~ +85°C 215°C 220°C Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS The following specifications apply for VDD = 5V, unless otherwise noted. Limits apply for TA=25°C. Symbol VDD IDD Parameter Condition Typ. Supply voltage Quiescent power supply current ISD Shutdown current TWU Turn on time VOC inside ground for headphone VIL SD Shutdown pin input low voltage VIH SD Shutdown pin input high voltage Bass Control AR Attenuator range As Bass step size ESE Bass step size error ET Bass tracking error Treble Control AR Attenuator range As Treble step size ESE Treble step size error ET Treble tracking error I2C Bus Timing fmax Maximum bus frequency Start signal: hold time before Tstart;hold clock/data transitions Td;setup Data setup time Tc;high Minimum high clock duration Tc;low Minimum low clock duration Stop signal: setup time before Tstop;setup clock/data transitions 2 I C Bus Input And Output VIL I2C I2C input low voltage VIH I2C I2C input high voltage IIN Input current Output voltage—SDA Vo acknowledge Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 VIN = 0V, Io = 0A, BTL mode VIN = 0V, Io = 0A, SE mode Standby mode Cbp = 1μF VIN = 0 8 5 1.75 130 2.5 Limit Unit 3.0 V(min) 5.5 11 7 5 V(max) mA(max) mA(max) μA(max) ms V V(max) V(min) 0.4 1.4 f = 100Hz, VIN = 0.25V ±12 2 0.5 0.15 dB dB dB(max) dB(max) f = 10kHz, VIN = 0.25V ±12 2 0.1 0.15 dB dB dB(max) dB(max) 400 kHz 0.6 μs 0.1 0.6 1.3 μs μs μs 0.6 μs 0.8 1.6 V(max) V(min) μA 0.2 V(max) 0.15 5 IS31AP4832 ELECTRICAL CHARACTERISTICS FOR BRIDGED-MODE OPERATION (5V) Symbol Vos Po THD+N PSRR Parameter Output offset voltage Output power Total harmonic distortion +noise Power supply rejection ratio Condition VIN = 0V Typ. Limit Unit 5 25 mV(max) THD+N = 1%, f = 1kHz, RL = 4Ω 1.9 THD+N = 1%, f = 1kHz, RL = 8Ω 1.2 THD+N = 10%, f = 1kHz , RL = 4Ω 2.5 THD+N = 10%, f = 1kHz, RL = 8Ω 1.7 1kHz Avd = 2, RL = 4Ω, Po = 0.5W 0.12 1kHz Avd = 2, RL = 8Ω, Po = 0.2W 0.03 W 1.0 W(min) W % Input grounded 217Hz, Vripple = 200mVp-p Cbp = 1μF, RL = 8Ω 70 dB Input grounded 1kHz, Vripple = 200mVp-p Cbp = 1μF, RL = 8Ω 64 dB Xtalk Channel separation f = 1kHz, Cbp = 1μF Stereo Enhanced control = Low 88 dB VNO Output noise voltage 1kHz, A-weighted 10 μV ELECTRICAL CHARACTERISTICS FOR SINGLE-ENDED OPERATION (5V) Symbol Po Parameter Condition Output power THD+N = 0.5%,f = 1kHz, RL = 32Ω THD+N Total harmonic distortion + noise Po = 75mW,1kHz, RL = 32Ω PSRR Power supply rejection raito VNO Output noise voltage Typ. Limit Unit 90 85 mW(min) 0.015 % Input grounded 217Hz, Vripple = 200mVp-p Cbp = 1μF, RL = 32Ω 75 dB Input grounded 1kHz, Vripple = 200mVp-p Cbp = 1μF, RL = 32Ω 72 dB 1kHz, A-weighted 25 μV Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 6 IS31AP4832 ELECTRICAL CHARACTERISTICS FOR BRIDGED-MODE OPERATION (3V) Symbol Vos Po THD+D PSRR VNO Parameter Output offset voltage Output power Total harmonic distortion+noise Power supply rejection ratio Output noise voltage Condition Typ. Limit Unit VIN = 0V 2.5 mV THD+N = 1%, f = 1kHz, RL = 4Ω 0.7 THD+N = 1%, f = 1kHz, RL = 8Ω 0.45 THD+N = 10%, f = 1kHz, RL = 4Ω 0.88 THD+N = 10%, f = 1kHz, RL = 8Ω 0.55 1kHz, Avd = 2, RL = 4Ω, Po = 0.35W 0.12 1kHz, Avd = 2, RL = 8Ω, Po = 0.15W 0.08 Input grounded 217Hz Vripple = 200mVp-p, Cbp = 1μF, RL = 8Ω 71 dB Input grounded 1kHz Vripple = 200mVp-p, Cbp = 1μF, RL = 8Ω 65 dB 1kHz, A-weighted 10 μV W % ELECTRICAL CHARACTERISTICS FOR SINGLE-ENDED OPERATION (3V) Symbol Po THD+N VNO Parameter Condition Output power THD+N = 0.5%,f = 1kHz, RL = 32Ω Total harmonic distortion+noise Po = 25mW, 1kHz, RL = 32Ω Output noise voltage 1kHz, A-weighted Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 Typ. Limit Unit 32 mW 0.02 % 25 μV 7 IS31AP4832 TYPICAL PERFORMANCE CHARACTERISTICS % 10 10 5 5 2 2 1 1 0.5 0.5 % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 0.01 20 20k 50 100 200 Hz Figure 2 THD+N vs. Frequency VDD=3V, RL=4ohm, BTL, PO=350mW, Avd=2, BW=80kHz Figure 3 10 10 5 5 2 2 1 1 0.1 0.05 0.05 0.02 0.02 THD+N vs. Frequency VDD=5V, RL=4ohm, BTL, PO=500mW, Avd=2, BW=80kHz 50 100 200 500 1k 2k 5k 0.01 20 20k 50 100 200 Hz 500 1k 2k 5k 20k Hz THD+N vs. Frequency VDD=3V, RL=8ohm, BTL, PO=150mW, Avd=2, BW=80kHz Figure 5 10 10 5 5 2 2 1 1 0.5 THD+N vs. Frequency VDD=5V, RL=8ohm, BTL, PO=200mW, Avd=2, BW=80kHz 0.5 % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 20k 0.01 20 THD+N vs. Frequency VDD=3V, RL=32ohm, SE, PO=25mW, Avd=2, BW=80kHz Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 50 100 200 500 1k 2k 5k 20k Hz Hz Figure 6 20k 0.2 0.1 0.01 20 % 5k 0.5 % 0.2 Figure 4 2k Hz 0.5 % 500 1k Figure 7 THD+N vs. Frequency VDD=5V, RL=32ohm, SE, PO=75mW, Avd=2, BW=80kHz 8 IS31AP4832 20 10 5 % 20 10 5 10kHz 2 1 0.5 % 1kHz 0.2 0.1 0.05 2 1 0.5 0.2 0.1 0.05 20Hz 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 1 0.01 10m 20m 2 50m 100m W Figure 8 THD+N vs. Output Power VDD=3V, RL=4ohm, BTL, Avd=2, BW=80kHz Figure 9 2 1 0.5 10kHz % 0.2 0.1 0.05 20Hz 2 1 0.5 10kHz 1kHz 20Hz 0.02 0.01 10m 20m 50m 100m 200m 500m 0.01 10m 20m 1 50m 100m 200m THD+N vs. Output Power VDD=3V, RL=8ohm, BTL, Avd=2, BW=80kHz Figure 11 20 10 5 20 10 5 2 1 0.5 2 1 0.5 % 10kHz 0.2 0.1 0.05 1kHz 20Hz 0.02 0.01 1m 2m 3m 5m 7m 1 2 20m 40m 80m THD+N vs. Output Power VDD=3V, RL=32ohm, SE, Avd=2, BW=80kHz Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 THD+N vs. Output Power VDD=5V, RL=8ohm, BTL, Avd=2, BW=80kHz 1kHz 10kHz 0.2 0.1 0.05 20Hz 0.02 0.01 1m 2m 5m 10m 20m 50m 200m W W Figure 12 500m W W % 2 3 THD+N vs. Output Power VDD=5V, RL=4ohm, BTL, Avd=2, BW=80kHz 0.2 0.1 0.05 1kHz 0.02 Figure 10 1 20 10 5 20 10 5 % 500m W Figure 13 THD+N vs. Output Power VDD=5V, RL=32ohm, SE, Avd=2, BW=80kHz 9 IS31AP4832 Figure 14 PSRR vs. Frequency VDD=3V, RL=8ohm, BTL, Input AC-grounded Figure 15 PSRR vs. Frequency VDD=5V, RL=8ohm, BTL, Input AC-grounded +0 100u -1 0 50u 3V and 5V SE, 32ohm -2 0 20u -3 0 -4 0 10u V d B 5u -5 0 -6 0 B to A 3V and 5V BTL, 8ohm 2u -7 0 -8 0 1u 20 50 100 200 500 1k 2k 5k 20k Hz Figure 16 -1 0 0 20 50 100 200 500 1k 2k 5k 10k 20k Hz Noise Floor A-Weighted Figure 17 +20 +20 +15 +15 +10 +10 Crosstalk VDD=5V, RL=8ohm, BTL +5 +5 d B r A to B -9 0 d B r +0 +0 A A -5 -5 -10 -10 -15 -15 -20 20 50 100 200 500 1k 2k 5k 10k 20k -20 20 Figure 18 Base Response vs. Frequency VDD=5V, RL=8ohm, BTL Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 50 100 200 500 1k 2k 5k 10k 20k Hz Hz Figure 19 Treble Response vs. Frequency VDD=5V, RL=8ohm, BTL 10 IS31AP4832 +20 +15 +10 +5 d B r +0 A -5 -10 -15 -20 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 20 Bass and Treble Response vs. Frequency VDD=5V, RL=8ohm, BTL TIMING DIAGRAMS Figure 21 Figure 22 I2C Bus Format I2C Timing Diagram See Electrical Characteristics section for timing specifications Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 11 IS31AP4832 TRUTH TABLES SOFTWARE SPECIFICATION Chip Address MSB LSB 1 0 0 0 0 0 0 0 Data Bytes (Brief Description) MSB LSB Function 0 0 1 X D3 D2 D1 D0 Bass Control 0 1 0 X D3 D2 D1 D0 Treble Control 1 1 1 X D3 D2 D1 D0 General Control Bass Control MSB LSB Level (dB) 0 0 1 X 0 0 0 0 −12 0 0 1 X 0 0 0 1 −10 0 0 1 X 0 0 1 0 −8 0 0 1 X 0 0 1 1 −6 0 0 1 X 0 1 0 0 −4 0 0 1 X 0 1 0 1 −2 0 0 1 X 0 1 1 0 0 0 0 1 X 0 1 1 1 2 0 0 1 X 1 0 0 0 4 0 0 1 X 1 0 0 1 6 0 0 1 X 1 0 1 0 8 0 0 1 X 1 0 1 1 10 0 0 1 X 1 1 0 0 12 X 0 1 1 0 Bass Control is Flat Bass Control Power Up State Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 12 IS31AP4832 Treble Control MSB LSB Level (dB) 0 1 0 X 0 0 0 0 −12 0 1 0 X 0 0 0 1 −10 0 1 0 X 0 0 1 0 −8 0 1 0 X 0 0 1 1 −6 0 1 0 X 0 1 0 0 −4 0 1 0 X 0 1 0 1 −2 0 1 0 X 0 1 1 0 0 0 1 0 X 0 1 1 1 2 0 1 0 X 1 0 0 0 4 0 1 0 X 1 0 0 1 6 0 1 0 X 1 0 1 0 8 0 1 0 X 1 0 1 1 10 0 1 0 X 1 1 0 0 12 X 0 1 1 0 Treble Control is Flat Treble Control Power Up State General Control MSB LSB Function 1 1 1 0 Chip On 1 1 1 1 Chip Shutdown 1 1 1 0 Speaker Enable 1 1 1 1 Speaker Disable 1 1 1 0 Stereo Enhance Off 1 1 1 1 Stereo Enhance On 1 1 1 0 Mute Disable 1 1 1 1 Mute Enable General Control Power Up State 0 0 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 0 0 0 13 IS31AP4832 APPLICATION INFORMATION LAYOUT As stated in the Grounding section, placement of ground return lines is critical for maintaining the highest level of system performance. It is not only important to route the correct ground return lines together, but also important to be aware of where those ground return lines are routed in conjunction with each other. The output load ground returns should be physically located as far as reasonably possible from low signal level lines and their ground return lines. Critical signal lines are those relating to the microphone amplifier section, since these lines generally work at very low signal levels. SUPPLY BYPASSING modified, the size of the bypass capacitor, CB, can be changed to alter the device turn-on time and the amount of “click and pop”. By increasing CB, the amount of turn-on pop can be reduced. However, the trade-off for using a larger bypass capacitor is an increase in the turn-on time for the device. Reducing CB will decrease turn-on time and increase “click and pop”. There is a linear relationship between the size of CB and the turn-on time. Some typical turn-on times for different values of CB are: Cb TON 0.1μF 50ms 1μF 130ms As with all op amps and power op amps, the IS31AP4832 requires the supplies to be bypassed to avoid oscillation. To avoid high frequency instabilities, a 0.1μF metallized-film or ceramic capacitor should be used to bypass the supplies as close to the chip as possible. For low frequency considerations, a 10μF or greater tantalum or electrolytic capacitor should be paralleled with the high frequency bypass capacitor. In order to eliminate “click and pop”, all capacitors must be discharged before turn-on. Rapid on/off switching of the device or shutdown function may cause the “click and pop” circuitry to not operate fully, resulting in increased “click and pop” noise. If power supply bypass capacitors are not sufficiently large, the current in the power supply leads, which is a rectified version of the output current, may be fed back into internal circuitry. This internal feedback signal can cause high frequency distortion and oscillation. Because the IS31AP4832 is a single supply circuit, all audio signals must be capacitor coupled to the chip to remove the 2.5 VDC bias. All audio inputs have 20kΩ input impedances, so the AC-coupling capacitor will create a high-pass filter with If power supply lines to the chip are long, larger bypass capacitors could be required. Long power supply leads have inductance and resistance associated with them that could prevent peak low frequency current demands from being met. The extra bypass capacitance will reduce the peak current requirements from the power supply lines. f−3dB = 1/(2π×20kΩ×CIN) POWER-UP STATUS On power-up or after a hard reset, the IS31AP4832 registers will be initialized with the default values listed in the truth tables. By default, the tone controls are all flat, 3D Enhance is off, and the chip is in stereo mode. CLICK-AND-POP CIRCUITRY The IS31AP4832 contains circuitry to minimize turn-on transients or “click and pops”. In this case, turn-on refers to either power supply turn-on or the device coming out of shutdown mode. When the devices turn on, the amplifiers are internally configured as unity gain buffers. An internal current source charges the bypass capacitor on the bypass pin. Both the inputs and outputs ideally track the voltage at the bypass pin. The device will remain in buffer mode until the bypass pin has reached its half supply voltage, 1/2VDD. As soon as the bypass node is stable, the device will become fully operational. Although the bypass pin current source cannot be Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 COUPLING CAPACITORS POWER AMPLIFIER The power amplifiers in the IS31AP4832 are designed to drive 8Ω or 32Ω loads at 1.2W (continuous) and 90mW (continuous), respectively, with 1% THD+N. As shown in the Typical Performance Characteristics, the power amplifiers typically drive 4Ω loads at 350mW, but with a slight increase in high-frequency THD. As discussed above, these outputs should be AC-coupled to the output load. BRIDGE CONFIGURATION EXPLANATION As shown in Figure 1, the IS31AP4832 consists of two pairs of operational amplifiers, forming a two-channel (channel A and channel B) stereo amplifier. External feedback resistors Rf and input resistors Ri set the closed-loop gain of Amp A (NOUTA) and Amp B (NOUTA) whereas two internal 20kΩ resistors set Amp A’s (POUTA) and Amp B’s (POUTA) gain at 1. The IS31AP4832 drives a load, such speaker, connected between the two amplifier outputs, NOUTA and POUTA. Figure 1 shows that Amp A’s (NOUTA) output serves as Amp A’s (POUTA) input. This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between NOUTA and 14 IS31AP4832 POUTA and driven differentially (commonly referred to as “bridge mode”). This results in a differential gain of AVD = 2×(Rf/Ri) (1) Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. This produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing channel A’s and channel B’s outputs at half-supply. This eliminates the coupling capacitor that single supply, single ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. I2C INTERFACE The IS31AP4832 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: clock and data. The clock line is uni-directional. The data line is bi-directional (open-collector) with a pull-up resistor (typically 10kΩ).The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31AP4832. The timing diagram for the I2C is shown in Figure 22. The data is latched in on the stable high level of the clock and the data line should be held high when not in use. The timing diagram is broken up into six major sections: The “start” signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the clock level is high. After the last bit of the address is sent, the master checks for the IS31AP4832’s acknowledge. The master releases the data line high (through a pull-up resistor). Then the master sends a clock pulse. If the IS31AP4832 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not low, then the master should send a “stop” signal (discussed later) and abort the transfer. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 After the data byte is sent, the master must generate another acknowledge seeing if the IS31AP4832 received the data. If the master has more data bytes to send to the IS31AP4832, then the master can repeat the previous two steps until all data bytes have been sent. The “stop” signal ends the transfer. To signal “stop”, the data signal goes high while the clock signal is high. 3D AUDIO ENHANCEMENT The IS31AP4832 has a 3D audio enhancement effect that helps improve the apparent stereo channel separation when, because of cabinet or equipment limitations, the left and right speakers are closer to each other than optimal. An external RC network is required to enable the effect. The amount of the effect is set by the 5kΩ resistor. A 220nF capacitor is used to reduce the effect at frequencies below 140Hz. Increasing the value of the capacitor will decrease the low cutoff frequency at which the Stereo Enhanced effect starts to occur as shown below F(–3dB) = 1/2π R3D×C3D Decreasing the resistor size will make the 3D effect more pronounced and decreasing the capacitor size will raise the cutoff frequency for the effect. TONE CONTROL RESPONSE Bass and treble tone controls are included in the IS31AP4832. The tone controls use two external capacitors for each stereo channel. Each has a corner frequency determined by the value of C1 (connected between loop out and tone in) and C2 (connected between tone out and loop in) and internal resistors in the feedback loop of the internal tone amplifier. Typically, C1 = C2 and for 100 Hz and 10kHz corner frequencies, C1 = C2 = 2.2nF. Altering the ratio between C1 and C2, changes the midrange gain. For example, if C1 = 2(C2), then the frequency response will be flat at 20Hz and 20kHz, but will have a 6dB peak at 1kHz. With C = C1 = C2, the treble turn-over frequency is nominally fTT = 1/(2πC(56kΩ)) and the bass turn-over frequency is nominally fBT = 1/(2πC(113.3kΩ)), when maximum boost is chosen. The inflection points (the frequencies where the boost or cut is within 3dB of the final value) are, for treble and bass respectively, fTI = 1/(2πC(7.1kΩ)) fBI = 1/(2πC(631.7kΩ)) Increasing the values of C1 and C2 decreases the 15 IS31AP4832 turnover and inflection frequencies: i.e., the Tone Control Response Curves shown in Typical Performance Section will shift left when C1 and C2 are increased and shift right when C1 and C2 are decreased. With C1 = C2 = 0.0022μF, 2dB steps are achieved at 100Hz and 10kHz. Changing C1 and C2 to 0.001μF shifts the 2dB step frequency to 220Hz and 25kHz. If the tone control capacitors’ size is decreased these frequencies will increase. With C1 = C2 = 0.0033μF the 2dB steps take place at 68Hz and 7.6kHz. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 16 IS31AP4832 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 23 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 17 IS31AP4832 TAPE AND REEL INFORMATION Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 18 IS31AP4832 PACKAGE INFORMATION QFN-28 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/29/2011 19