TRIQUINT TGF2960-SD

TGF2960-SD
0.5 Watt DC-5 GHz Packaged HFET
Key Features
•
Frequency Range: DC-5 GHz
Nominal 900 MHz Application Board Performance:
• TOI: 40 dBm
• 28 dBm Psat, 27 dBm P1dB
• Gain: 19 dB
• Input Return Loss: -10 dB
• Output Return Loss: -5 dB
• Bias: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V
(Typical)
• Package Dimensions: 4.5 x 4 x 1.5 mm
900 MHz Application Board
Performance
Primary Applications
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
•
•
•
•
•
Cellular Base Stations
WiMAX
Wireless Infrastructure
IF & LO Buffer Applications
RFID
Product Description
The TGF2960-SD is a high performance 1/2-watt
Heterojunction GaAs Field Effect Transistor
(HFET) housed in a low cost SOT89 surface
mount package.
The device’s ideal operating point is at a drain bias
of 8 V and 100 mA. At this bias at 900 MHz when
matched into 50 ohms using external components,
this device is capable of 19 dB of gain, 28 dBm of
saturated output power, and 40 dBm of output IP3.
Evaluation boards at 900 MHz, 1900 MHz and
2100 MHz available on request.
RoHS and Lead-Free compliant.
Datasheet subject to change without notice.
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2012 © Rev B
1
TGF2960-SD
Table I
Absolute Maximum Ratings 1/
Symbol
Parameter
Vd-Vg
Value
Notes
Drain to Gate Voltage
17 V
Vd
Drain Voltage
9V
Vg
Gate Voltage Range
-5 to 0 V
Id
Drain Current
390 mA
Ig
Gate Current Range
Pin
2/
2/
-2.4 to 17.8 mA
Input Continuous Wave Power
26 dBm
2/
1/
These ratings represent the maximum operable values for this device. Stresses beyond those listed
under “Absolute Maximum Ratings” may cause permanent damage to the device and / or affect
device lifetime. These are stress ratings only, and functional operation of the device at these
conditions is not implied.
2/
Combinations of supply voltage, supply current, input power, and output power shall not exceed the
maximum power dissipation listed in Table IV.
Table II
Recommended Operating Conditions
Symbol
1/
Parameter 1/
Typical Value
Vd
Drain Voltage
8V
Idq
Drain Current
100 mA
Id
Drain Current at Psat
130 mA
Vg
Gate Voltage
-1.0 V
See assembly diagram for bias instructions.
2
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TGF2960-SD
Table III
Electrical Performance
Test conditions unless otherwise specified: fin = 900 MHz, 25°C; Vd = 8V, Idq = 100
mA, Vg = -1.0 Typical; See test circuit for 900 MHz operation
SYMBOL
PARAMETER
MIn
Nom
UNIT
18
19
dB
Gain
Small Signal Gain
P1dB
Output Power @ 1dB Compression
25.5
27
dBm
OTOI
3rd Order Output Intercept Point 1/
37
40
dBm
1/ 900 and 910 MHz, 16 dBm output power per tone
3
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May 2012 © Rev B
TGF2960-SD
Table IIIa
RF Characterization Table
Bias: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V, typical
SYMBOL
PARAMETER
TEST CONDITIONS
NOMINAL
UNITS
NOTES
Gain
Small Signal Gain
900 MHz
1900 MHz
2100 MHz
19
16
15
dB
1/
2/
3/
IRL
Input Return Loss
900 MHz
1900 MHz
2100 MHz
-10
-10
-10
dB
1/
2/
3/
ORL
Output Return Loss
900 MHz
1900 MHz
2100 MHz
-5
-6
-6
dB
1/
2/
3/
Psat
Saturated Output
Power
900 MHz
1900 MHz
2100 MHz
28
28
28
dBm
1/
2/
3/
P1dB
Output Power @ 1dB
Compression
900 MHz
1900 MHz
2100 MHz
27
27
27
dBm
1/
2/
3/
TOI
Output TOI
900 MHz
1900 MHz
2100 MHz
40
39
39
dBm
1/
4/
5/
NF
Noise Figure
900 MHz
1900 MHz
2100 MHz
3.7
4.3
4.3
dB
1/
2/
3/
1/
Using 900 MHz Application Board
2/
Using 1900 MHz Application Board tuned for maximum output power
3/
Using 2100 MHz Application Board tuned for maximum output power
4/
Using 1900 MHz Application Board tuned for maximum TOI (reduces output power reduced by 1 dB)
5/
Using 2100 MHz Application Board tuned for maximum TOI (reduces output power reduced by 1 dB)
4
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May 2012 © Rev B
TGF2960-SD
Table IV
Power Dissipation and Thermal Properties
Parameter
Test Conditions
Value
Maximum Power Dissipation
Tbaseplate = 70°C
Pd = 1.37 W
Tchannel = 175°C
Tm = 8.77E+06 Hrs
Thermal Resistance, θjc
Vd = 8 V
Id = 100 mA
Pd = 0.8 W
Tbaseplate = 85°C
θjc = 77 (°C/W)
Tchannel = 146.5°C
Tm = 2.06E+08 Hrs
Thermal Resistance, θjc
at Psat
Vd = 8 V
Id =130 mA
Pout = 27 dBm
Pd = 0.54 W
Tbaseplate = 85°C
θjc = 77 (°C/W)
Tchannel = 126°C
Tm = 2.48E+09 Hrs
Mounting Temperature
See ‘Typical Solder Reflow Profiles’ Table
Storage Temperature
-65 to 150°C
5
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TGF2960-SD
Gmax, Max Stable Gain, K factor
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
6
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TGF2960-SD
Measured Data 900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
7
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May 2012 © Rev B
TGF2960-SD
Measured Data 900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
8
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May 2012 © Rev B
TGF2960-SD
Measured Data 900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
9
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May 2012 © Rev B
TGF2960-SD
Measured Data 1900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
10
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May 2012 © Rev B
TGF2960-SD
Measured Data 1900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
11
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May 2012 © Rev B
TGF2960-SD
Measured Data 1900 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
(Tuned for Max IP3, P1dB reduced by 1 dB)
(Tuned for Max Pout)
12
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May 2012 © Rev B
TGF2960-SD
Measured Data 2100 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
13
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May 2012 © Rev B
TGF2960-SD
Measured Data 2100 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
14
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2012 © Rev B
TGF2960-SD
Measured Data 2100 MHz Application Board
Bias conditions: Vd = 8 V, Idq = 100 mA, Vg = -1.0 V Typical
(Tuned for Max IP3, P1dB reduced by 1 dB)
(Tuned for Max Pout)
15
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May 2012 © Rev B
TGF2960-SD
Electrical Schematic
2
1
2
3
Pin
Signal
1
RF In (Gate)
2
Gnd (Source)
3
RF Out (Drain)
Bias Procedures
Bias-up Procedure
ƒ
Vg set to -2.5 V
ƒ
Vd set to +8 V
ƒ
Adjust Vg more positive until Idq is 100 mA. This will be ~ Vg = -1.0 V
ƒ
Apply RF signal to input
Bias-down Procedure
ƒ
Turn off RF signal at input
ƒ
Reduce Vg to -2.5V. Ensure Id ~ 0 mA
ƒ
Turn Vd to 0 V
ƒ
Turn Vg to 0 V
16
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Mechanical Drawing
TGF2960-SD
Units: Millimeters
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.
17
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TGF2960-SD
Evaluation Board
L2 R1 Gnd
Vg
Q1
Vd
C5
C7
C9
C6
C8
C10
RF IN
L3
C2
RF OUT
C4
L4
(900 MHz Only)
D / λ (900 MHz)
D / λ (1900 & 2100 MHz)
C1 R2
C3 L1
Evaluation Board Schematic
Vg
Vd
C6 C8 C10
C5 C7 C9
R1
RF IN
Z0 = 50Ω
C3
L1
L2
C1
R2
L3
Q1
L4
(900
MHz
Only)
D/λ
C4
C2
RF OUT
Z0 = 50Ω
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2012 © Rev B
18
TGF2960-SD
Evaluation Board Bill of Materials
Ref Des
Value for Freq (MHz)
Description
900
1900
2100
L1
4.7 nH
1.2 nH
1.5 nH
0603 ACCU-L AVX Inductor
C1
22 pF
1.2 pF
1.2 pF
0603 ACCU-P AVX Capacitor
C2
0.7 pF
0.6 pF
0.6 pF
0603 ACCU-P AVX Capacitor
D
18.8 mm
14.2 mm
5.8 mm
Physical Location for C2
D
18.8 mm
14.2 mm
5.8 mm
Physical Location for C2 for maximum
power
λ
[email protected]
GHz
[email protected]
GHz
[email protected]
GHz
50 Ohm Transmission Line Length D
for maximum power
D
18.8 mm
17.2 mm
9.6 mm
Physical Location for C2 for maximum
TOI
λ
[email protected]
GHz
[email protected]
GHz
[email protected]
GHz
50 Ohm Transmission Line Length D
for maximum TOI
L2, L3
50 nH
L4
1.2 nH
--
0805 Inductor
--
0603 ACCU-L AVX Inductor
C3,C4
150 pF
0603 Capacitor
C5, C6
0.1 μF
0603 Capacitor
C7, C8
0.01 μF
0603 Capacitor
C9, C10
1000 pF
0603 Capacitor
R1
50 Ohms
0805 1/8 Watt Resistor
R2
11 Ohms
3 Ohms
5.1 Ohms
0805 1/8 Watt Resistor
Q1
--
TriQuint TGF2960-SD Packaged FET
(PCB)
--
28 mil thick GETEK
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2012 © Rev B
19
TGF2960-SD
Recommended Assembly Diagram
2.6 mm Ø CLEARANCE HOLE
FOR 2-56 SOCKET HEAD CAP SCREW (2/)
7.6 X 7.6 mm COPPER AREA (3/)
ARRAY OF VIAS (1/)
4.6 mm Ø SOLDERMASK
SOT-89 PACKAGE OUTLINE
KEEPOUT FOR 2-56 LOCKWASHER (4/)
1
2
3
Assembly Notes
1/ The lowest possible thermal and electrical resistance for Pin 2 is critical for optimal performance. The array
of vias under Pin 2 should be as small and as dense as the PC board fabrication permits. 0.30 mm diameter
vias on 0.60 mm center to center spacing is recommended.
2/ Mounting screws in the vicinity of the package improve heat transfer to the chassis or to a heat spreader
located on the backside of the PC board. Shown are clearance holes and solder mask keepout zone for a 256 socket head cap screw. Use of a split lockwasher and proper torque on the screw will prevent
compression damage to the PC board.
3/ Use of 1 oz copper (min) in the PC board construction is recommended.
4/ For lowest thermal resistance, solder mask must be removed where the copper traces on the PC board
contact the heat spreader. In this example, this would be a) front and backsides of the PC board around the
2-56 screw and b) front of the PC board around package pin 2.
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2012 © Rev B
20
TGF2960-SD
Recommended Surface Mount Package Assembly
Proper ESD precautions must be followed while handling packages.
Clean the board with acetone. Rinse with alcohol. Allow the circuit to fully dry.
TriQuint recommends using a conductive solder paste for attachment. Follow solder paste and reflow oven
vendors’ recommendations when developing a solder reflow profile. Typical solder reflow profiles are listed
in the table below.
Hand soldering is not recommended. Solder paste can be applied using a stencil printer or dot placement.
The volume of solder paste depends on PCB and component layout and should be well controlled to
ensure consistent mechanical and electrical performance.
Clean the assembly with alcohol.
Typical Solder Reflow Profiles
Reflow Profile
SnPb
Pb Free
Ramp-up Rate
3 °C/sec
3 °C/sec
Activation Time and
Temperature
60 – 120 sec @ 140 – 160 °C
60 – 180 sec @ 150 – 200 °C
Time above Melting Point
60 – 150 sec
60 – 150 sec
Max Peak Temperature
240 °C
260 °C
Time within 5 °C of Peak
Temperature
10 – 20 sec
10 – 20 sec
Ramp-down Rate
4 – 6 °C/sec
4 – 6 °C/sec
Ordering Information
Part
Package Style
TGF2960-SD, TAPE AND REEL
SOT-89, TAPE AND REEL
21
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May 2012 © Rev B