TS3DV642 www.ti.com SCDS343 – MAY 2013 12-Channel 1:2 MUX/DEMUX with1.8V Compatible Control and Power-Down Mode Check for Samples: TS3DV642 FEATURES APPLICATIONS • • • • • • • 1 • • • • • • • Switch Type: 2:1 or 1:2 Differential Bandwidth (–3dB) – Port A – 6.9 GHz Typical – Port B – 7.5 GHz Typical Ron – Port A – 6.5 Ω Typical – Port B – 8.2 Ω Typical Con: 4 pF Typ VCC Range, 2.6 V–4.5 V I/O Voltage range, 0 V–5 V Special Features – IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V) ESD Performance – 2 kV Human Body Model (A114B, Class II) – 1 kV Charged Device Model (C101) 42-pin QFN Package (9 x 3.5 mm, 0.5 mm Pitch) HDMI 1.4/DVI 1.0 Signal Switching DisplayPort 1.2 Signal Switching General Purpose TMDS Signal Switching General Purpose LVDS Signal Switching General Purpose High Speed Signal Switching DESCRIPTION The TS3DV642 is a 12 channels 1:2 or 2:1 bidirectional multiplexer/demultiplexer. The TS3DV642 operates from a 2.6 to 4.5 V supply, making it suitable for battery-powered applications. It offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of up to 7.5 GHz. The device provides the high bandwidth necessary for HDMI and DisplayPort applications. The TS3DV642 offers a power-down mode, in which all channels become high-Z and the device operates with minimal power. TYPICAL APPLICATION DIAGRAM TS3DV642 Primary HDMI Source Sideband Channel xxxxx xxxxx xxxxx xxxxx Graphic Display Processor Secondary Source Sideband Channels: DDC, CEC &HPD Channel Video Imaging HDMI Receiver Processor Secondary HDMI Source TS3DV621 Primary Source Sideband Channels: DDC, CEC &HPD Data Figure 1. Typical 2:1 HDMI Demux Application ORDERING INFORMATION TA –40°C to 85°C PACKAGE QFN – RUA Tape and Reel ORDERABLE PART NUMBER TOP-SIDE MARKING TS3DV642RUAR SD642A0 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TS3DV642 SCDS343 – MAY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN DESCRIPTION VCC 39 SDA_B 40 SCL_B 41 SDA_A 42 SCL_A PIN 1 I/O Type NAME NUMBER VCC 1 Power DESCRIPTION Supply Voltage GND PowerPad GND SEL1 16 I Ground Select Input 1 SEL2 17 I Select Input 2 Output Enable EN 2 I 38 D0+A D0+A 38 I/O Port A, Lane 0, +ve signal D0–A 37 I/O Port A, Lane 0, –ve signal D1+A 36 I/O Port A, Lane 1, +ve signal D1-A 35 I/O Port A, Lane 1, –ve signal D2+A 34 I/O Port A, Lane 2, +ve signal D2–A 33 I/O Port A, Lane 2,–ve signal EN 2 37 D0-A SCL 3 36 D1+A SDA 4 35 D1-A D0+ 5 34 D2+A D3+A 32 I/O Port A, Lane 3, +ve signal D0- 6 33 D2-A D3–A 31 I/O Port A, Lane 3, –ve signal SCL_A 42 I/O Port A, DDC Clock D1+ 7 32 D3+A SDA_A 41 I/O Port A, DDC Data D1- 8 31 D3-A HPD_A 19 I/O Port A, Hot Plug Detects NC 9 30 NC CEC_A 18 I/O Port A, Consumer Electronics Control D2+ 10 29 D0+B D0+B 29 I/O Port B, Lane 0, +ve signal D0–B 28 I/O Port B, Lane 0, –ve signal D2- 11 28 D0-B D1+B 27 I/O Port B, Lane 1, +ve signal D1–B 26 I/O Port B, Lane 1, –ve signal GND D2+B 25 I/O Port B, Lane 2, +ve signal D3- 13 26 D1-B D2–B 24 I/O Port B, Lane 2,–ve signal HPD 14 25 D2+B D3+B 23 I/O Port B, Lane 3, +ve signal CEC 15 24 D2-B SEL1 16 23 SEL2 17 22 2 HPD_B 21 D1+B CEC_B 20 27 HPD_A 19 12 CEC_A 18 D3+ D3–B 22 I/O Port B, Lane 3, –ve signal SCL_B 40 I/O Port B, DDC Clock D3+B SDA_B 39 I/O Port B, DDC Data D3-B HPD_B 21 I/O Port B, Hot Plug Detects CEC_B 20 I/O Port B, Consumer Electronics Control D0+ 5 I/O Common Port, Lane 0, +ve signal D0– 6 I/O Common Port, Lane 0, –ve signal D1+ 7 I/O Common Port, Lane 1, +ve signal D1– 8 I/O Common Port, Lane 1, –ve signal D2+ 10 I/O Common Port, Lane 2, +ve signal D2– 11 I/O Common Port, Lane 2, –ve signal D3+ 12 I/O Common Port, Lane 3, +ve signal D3– 13 I/O Common Port, Lane 3,–ve signal SCL 3 I/O Common Port, DDC Clock SDA 4 I/O Common Port, DDC Data HPD 14 I/O Common Port, Hot Plug Detects CEC 15 I/O Common Port, Consumer Electronics Control NC 9, 30 NC No Connect Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 TS3DV642 www.ti.com SCDS343 – MAY 2013 LOGIC DIAGRAM D0+ D0+A D0- D0-A D1+ D1+A D1- D1-A D2+ D2+A D2- D2-A D3+ D3- D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B SCL SCL_A SDA SDA_A HPD HPD_A CEC CEC_A SCL_B SDA_B HPD_B CEC_B SEL1 SEL2 Control Logic EN Table 1. Functional Table EN SEL1 SEL2 L X X Switch Disabled. All Channel Hi-Z. FUNCTION H L L D0+/D0– to D0+A/D0–A ON. All the other channels Hi-Z. H L H D0+/D0– to D0+B/D0–B ON. All the other channels Hi-Z. H H L Channel A Enabled. Channel B Hi-Z. H H H Channel B Enabled. Channel A Hi-Z. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 3 TS3DV642 SCDS343 – MAY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 5.5 V VI/O Analog voltage range (2) (3) (4) All I/O –0.5 5.5 V VIN Digital input voltage range (2) (3) SEL1, SEL2,EN –0.5 5.5 V II/OK Analog port diode current VI/O < 0 –50 mA IIK Digital input clamp current VIN < 0 –50 mA II/O On-state switch current (5) θJA Package thermal impedance (6) Tstg Storage temperature range (1) (2) (3) (4) (5) (6) –128 RUA package –65 128 mA TBD °C/W 150 °C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VI/O Input/Output voltage TA Operating free-air temperature (1) MIN MAX UNIT 2.6 4.5 0 5.5 V –40 85 °C V All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ELECTRICAL CHARACTERISTICS TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX 6.5 9.5 Ω 6 9.5 Ω UNIT PORT A D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = –40 mA RON ON-state resistance RON(flat) (3) ON-state resistance flatness All I/O VCC = 3 V, VI/O = 1.5 V and VCC, II/O = –40 mA 1.5 ΔRON (4) On-state resistance match between highspeed channels D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = –40 mA 0.4 IOFF Leakage under power off All outputs SCL, SDA, HPE, CEC Ω 1 Ω ±10 µA 8.2 10.5 Ω 6 10.5 Ω VCC = 0 V, VI/O = 0 to 3.6 V, VIN = 0 V to 5.5 V PORT B D0 to D3 RON ON-state resistance RON(flat) (3) ON-state resistance flatness ΔRON (4) On-state resistance match between highspeed channels IOFF Leakage under power off All outputs (1) (2) (3) (4) 4 SCL, SDA, HPE, CEC VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = -40 mA All I/O VCC = 3 V, VI/O = 1.5 V and VCC, II/O = –40 mA 1.5 D0 to D3 VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = –40 mA 0.4 VCC = 0 V, VI/O = 0 V to 3.6 V, VIN = V to 5.5 V Ω 1 Ω ±10 µA VI, VO, II, and IO refer to I/O pins, VIN refers to the control inputs All typical values are at VCC = 3.3V (unless otherwise noted), TA = 25°C RON(FLAT) is the difference of RON in a given channel at specified voltages. ΔRON is the difference of RON from center port to any other ports. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 TS3DV642 www.ti.com SCDS343 – MAY 2013 ELECTRICAL CHARACTERISTICS (continued) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX UNIT DIGITAL INPUTS (SEL1, SEL2, EN) VIH High-level control input voltage SEL1, SEL2, EN 1.4 3.6 V VIL Low-level control input voltage SEL1, SEL2, EN 0 0.5 V IIH Digital input high leakage current SEL1, SEL2, EN VCC = 3.6 V , VIN = VDD ±10 µA IIL Digital input low leakage current SEL1, SEL2, EN VCC = 3.6 V, VIN = GND ±10 µA SUPPLY ICC VCC supply current VCC = 3.6 V, II/O = 0, Normal Operation Mode, EN = H ICC, PD VCC supply current in power-down mode VCC = 3.6 V, II/O = 0, EN = L 50 µA 6 µA SWITCHING CHARACTERISTICS over recommended operation free-air temperature range, VCC = 3.3 V± 0.3 V (unless otherwise noted) PARAMETER tON (2) tSWITCH (3) TEST CONDITIONS Switch turn-on time All I/O See Figure 2 Switching time between channels All I/O See Figure 3 MIN TYP (1) tpd Propagation Delay D0 to D3 Port B Inter-pair Skew tSKEW Intra-pair Skew (1) (2) (3) SCL, SDA, HPD, CEC Port A µs µs 30 30 See Figure 4 ps 40 SCL, SDA, HPD, CEC 30 Port A Port B UNIT 100 20 D0 to D3 Port A MAX 2 2 D0 to D3 ps 2 Port B 6 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. tON is the time it takes the output to recover after enabling switches tSWITCH is the time it takes for the output to recover after the state is changed DYNAMIC CHARACTERISTICS Over recommended operation free-air temperature range, VCC = 3.3V ± 0.3V (unless otherwise noted) PARAMETER TEST CONDITIONS CIN Digital input capacitance f = 1 MHz, VIN = 0 V Coff Switch OFF capacitance Con Switch ON capacitance Xtalk Differential Crosstalk OISO Differential Off Isolation IL Insertion Loss BW Differential Bandwidth Port A (–3 dB) Port B (1) MIN TYP (1) MAX UNIT 6 pF f = 1 GHz, VI/O = 0 V, Output is open, Switch is OFF 0.3 pF f = 1 GHz, VI/O = 0 V, Output is open, Switch is ON 0.5 pF RL = 50 Ω at 1.7 GHz (See Figure 5) –40 RL = 50 Ω at 2.7 GHz (See Figure 6) -40 RL = 50 Ω at 1.7 GHz (See Figure 6) –23 RL = 50 Ω at 2.7 GHz (See Figure 6) -28 dB dB Port A at DC –0.75 dB Port B at DC –1 dB RL = 50 Ω, All channels (See Figure 7) 6.9 RL = 50 Ω, All channels (See Figure 7) 7.5 GHz All Typical Values are at VCC = 3.3V (unless otherwise noted), TA = 25°C. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 5 TS3DV642 SCDS343 – MAY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL 50Ω CL 4pF VCOM VCC *CL includes probe, cable, and board capacitance Port A VCOM 2.6V CL Port B + RL EN 50% 0 EN CL RL tON VOH Switch Output Control 50% VOL Input Figure 2. Switch Turn-On Time (tON) VCC RL 50Ω CL 4pF VCOM VCC *CL includes probe, cable, and board capacitance Port A VCOM CL Port B + SEL1/SEL2 CL RL 2.6V SEL1/ SEL2 RL 50% 0 tON Switch Output Control Input VOH 50% VOL Figure 3. Switching Time Between Channels (tSWITCH) 3V Input 50% 50% 0 tPLH Output tpd = (tPLH + tPLH) / 2 tPLH 50% VOH 50% VOL Figure 4. Propagation Delay (tpd) 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 TS3DV642 www.ti.com SCDS343 – MAY 2013 PARAMETER MEASUREMENT INFORMATION (continued) VDD Network Analyzer TS3DV642 RS RT VS RT Channel ON VOUT SEL = H or L RS = RT = 50Ω NC VS RT SEL GND VS = -10dBm (200mV at 50Ω Load) VDC_BIAS = 1 V RT Control Input Figure 5. Crosstalk (Xtalk) VCC Network Analyzer TS3DV642 RS VOUT+ RT VS RS RT VOUT- VS SEL GND RT Channel OFF SEL = H or L RS = RT = 50Ω VS = -10dBm (200mV at 50Ω Load) VDC_BIAS = 1 V RT Control Input Figure 6. Differential Off-Isolation (OISO) VDD VOUT+ Network Analyzer TS3DV642 RS VS RT VOUT- RS VS RT GND Channel ON SEL = H or L RS = RT = 50Ω VS = -10dBm (200mV at 50Ω Load) VDC_BIAS = 1 V RT RT Control Input Figure 7. Differential Bandwidth (BW) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 7 TS3DV642 SCDS343 – MAY 2013 www.ti.com TYPICAL CHARACTERISTICS Figure 8. Differential S21 vs Frequency for Port A Figure 9. Differential S21 vs Frequency for Port B 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 TS3DV642 www.ti.com SCDS343 – MAY 2013 TYPICAL CHARACTERISTICS (continued) 0 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 ±10 ±20 ±30 dB ±40 ±50 ±60 ±70 ±80 ±90 ±100 Frequency (Hz) C001 Figure 10. XTALK Port A 0 100000 1000000 10000000 100000000 1E+09 1E+10 -20 dB -40 -60 -80 -100 -120 Frequency (Hz) C002 Figure 11. XTALK Port B Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 9 TS3DV642 SCDS343 – MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 100000 1000000 10000000 100000000 1E+09 1E+10 -10 -20 -30 dB -40 -50 -60 -70 -80 -90 -100 Frequency (Hz) C003 Figure 12. OIRR Port A 0 100000 1000000 10000000 100000000 1E+09 1E+10 -20 dB -40 -60 -80 -100 -120 Frequency (Hz) C004 Figure 13. OIRR Port B 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TS3DV642 PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) TS3DV642A0RUAR ACTIVE Package Type Package Pins Package Drawing Qty WQFN RUA 42 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-2-260C-1 YEAR (4/5) SD642A0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TS3DV642A0RUAR Package Package Pins Type Drawing WQFN RUA 42 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 16.4 Pack Materials-Page 1 3.8 B0 (mm) K0 (mm) P1 (mm) 9.3 1.0 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3DV642A0RUAR WQFN RUA 42 3000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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