PRELIMINARY W215B Notebook PC System Frequency Generator for K6 Processors Features Table 1. Pin Selectable Frequency • Generates system clocks for CPU, IOAPIC, SDRAM, PCI, USB plus 14.318 MHz (REF0:1) • MODE input pin selects optional power management input control pins (reconfigures pins 26 and 27) • Two fixed outputs separately selectable as 24-MHz or 48-MHz (default = 48-MHz) • VDDQ3 = 3.3V±5%, VDDQ2 = 3.3V±5% • Uses external 14.318-MHz crystal • Available in 48-pin TSSOP (6.1-mm) • 10Ω CPU output impedance 95/100_SEL Block Diagram CPU, SDRAM Clocks (MHz) PCI Clocks 0 95.0 CPU/3 1 100.0 CPU/3 Pin Configuration VDDQ3 REF0 X1 X2 REF1 XTAL OSC PLL Ref Freq VDDQ2 IOAPIC VDDQ2 CPU1 www.DataSheet4U.com MODE I/O Control CPU2 Stop Output Control CPU3 VDDQ3 SDRAM0 SDRAM1 SDRAM2 95/100_SEL SDRAM3 PLL 1 SDRAM4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W215B CPU0 CPU_2.5# REF1 REF0 GND X1 X2 MODE VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND 95/100_SEL Reserved Reserved VDDQ3 48/24MHZ 48/24MHZ GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 CPU_2.5# VDDQ2 IOAPIC PWR_DWN# GND CPU0 CPU1 VDDQ2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# VDDQ3 SDRAM5 SDRAM6/CPUSTOP# SDRAM7/PCISTOP# PCI_F PCI0 Stop Output Control PCI1 PCI2 Power Down Control PWR_DWN# PCI3 PCI4 PCI5 PLL2 48/24MHZ 48/24MHZ Cypress Semiconductor Corporation Document #: 38-07222 Rev. *A* • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 15, 2002 PRELIMINARY W215B Pin Definitions Pin No. Pin Type CPU0:3 42, 41, 39, 38 O CPU Outputs 0 through 3: These four CPU outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI0:5 9, 11, 12, 13, 14, 16 O PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 8 O Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. 36, 35, 33, 32, 30, 29 O SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM6/ CPU_STOP# 27 I/O SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6. Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2–3 CPU clock latency). Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM7/ PCI_STOP# 26 I/O SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7. PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI clock following PCI_STOP# state change. Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. IOAPIC 45 O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 22, 23 O 48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device power-up. Either or both can be changed to 24 MHz through use of the serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied to VDDQ3 REF0:1 2, 1 O Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than REF1 and should be used for driving ISA slots. CPU_2.5# 47 I Set to logic 1 for 3.3V CPU I/O. 95/100_SEL 18 I 95- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selections). X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Pin Name SDRAM0:5 www.DataSheet4U.com 48/24MHz Document #: 38-07222 Rev. *A* Pin Description Page 2 of 14 PRELIMINARY W215B Pin Definitions Pin Name Pin No. Pin Type PWR_DWN# 44 I Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). MODE 6 I Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins. VDDQ3 7, 15, 21, 25 28, 34, 48 P Power Connection: Power supply for PCI0:5, REF0:1, and 48-/24-MHz output buffers. Connected to 3.3V supply. VDDQ2 46, 40 P Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to 3.3V supply. 3, 10, 17, 24, 31, 37, 43 G Ground Connection: Connect all ground pins to the common system ground plane. 19, 20 I Reserved Pins: Connect to Logic 1. GND Reserved Pin Description www.DataSheet4U.com Document #: 38-07222 Rev. *A* Page 3 of 14 www.DataSheet4U.com PRELIMINARY W215B Absolute Maximum Ratings[1] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDDQ3 Supply Current (3.3V) CPU0:3 = 100 MHz Outputs Loaded[2] 150 mA IDDQ2 Supply Current (3.3V) CPU0:3 = 100 MHz Outputs Loaded[2] 80 mA Logic Inputs VIL Input Low Voltage 0.8 V VIH Input High Voltage IIL Input Low Current[3] 10 µA IIH Input High Current[3] 10 µA 50 mV 2.0 V Clock Outputs VOL Output Low Voltage IOL = 2 mA VOH Output High Voltage IOH = –1 mA IOL Output Low Current IOH Output High Current 3.1 V CPU0:3 VOL = 1.5V 140 mA SDRAM0:7 VOL = 1.5V 110 mA PCI_F, PCI0:5 VOL = 1.5V 110 mA IOAPIC VOL = 1.5V 95 mA REF0 VOL = 1.5V 75 mA REF1 VOL = 1.5V 70 mA 48/24MHZ VOL = 1.5V 70 mA CPU0:3 VOL = 1.5V 120 mA SDRAM0:7 VOL = 1.5V 95 mA PCI_F, PCI0:5 VOL = 1.5V 95 mA IOAPIC VOL = 1.5V 95 mA REF0 VOL = 1.5V 80 mA REF1 VOL = 1.5V 62 mA 48/24MHZ VOL = 1.5V 60 mA Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 3. W215B logic inputs have internal pull-up devices (not CMOS level). Document #: 38-07222 Rev. *A* Page 4 of 14 PRELIMINARY W215B DC Electrical Characteristics (continued) TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5% Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[4] CLOAD Load Capacitance, Imposed on External Crystal[5] CIN,X1 X1 Input Capacitance[6] VDDQ3 = 3.3V 1.65 V 14 pF 28 pF Pin X2 unconnected Pin Capacitance/Inductance CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Except X1 and X2 Notes: 4. X1 input threshold voltage (typical) is VDDQ3/2. 5. The W215B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). AC Electrical Characteristics (Lump Load Model) TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V) fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5% AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. Test Point www.DataSheet4U.com FTG *20pF for CPU, REF1, IOAPIC, 24MHz & 48MHz *30pF for SDRAM & PCI CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 10 ns f Frequency, Actual Determined by PLL divider ratio 100 MHz tH High Time Duration of clock cycle above 2.4V 5 ns tL Low Time Duration of clock cycle below 0.4V 5 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* 50 10 Ω Page 5 of 14 www.DataSheet4U.com PRELIMINARY W215B SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 10 ns f Frequency, Actual Determined by PLL divider ratio 100 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 tD Duty Cycle Measured on rising and falling edge at 1.5V 45 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.5V tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1 50 4 V/ns 4 V/ns 55 % 500 ps 100 ps 1.5 ns 3 ms Ω 16 PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns f Frequency, Actual Determined by PLL divider ratio 33.3 MHz tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate 1 4 V/ns tF Output Fall Edge Rate 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.5V tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* 45 50 1 15 55 % 500 ps 250 ps 4 ns 3 ms Ω Page 6 of 14 www.DataSheet4U.com PRELIMINARY W215B I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter Description Test Condition/Comments f Frequency, Actual tR Output Rise Edge Rate tF Output Fall Edge Rate tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 1 1 45 50 Unit MHz 4 V/ns 4 V/ns 55 % 1.5 ms Ω 15 REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.318 Unit f Frequency, Actual tR Output Rise Edge Rate 1 4 V/ns tF Output Fall Edge Rate 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 45 50 MHz 55 % 1.5 ms Ω 16 REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Max. 14.318 Unit Frequency, Actual tR Output Rise Edge Rate 0.5 2 V/ns tF Output Fall Edge Rate 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* Frequency generated by crystal oscillator Typ. f 45 25 MHz 55 % 1.5 ms Ω Page 7 of 14 PRELIMINARY W215B 48-/24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit m/n PLL Ratio 57/17 tR Output Rise Edge Rate 0.5 2 V/ns tF Output Fall Edge Rate 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 45 50 Ω 25 AC Electrical Characteristics (Transmission Line Model) TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3±5% AC clock parameters are tested and guaranteed over stated operating conditions using the stated transmission line load at the clock output. 22 Ohm 6 inches 60 Ohm trace www.DataSheet4U.com FTG CPU Clock Outputs, CPU0:3 (Test Load: R = 33Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 10 ns f Frequency, Actual Determined by PLL divider ratio 100 MHz tH High Time Duration of clock cycle above 2.4V 5 ns tL Low Time Duration of clock cycle below 0.4V 5 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* 50 10 Ω Page 8 of 14 www.DataSheet4U.com PRELIMINARY W215B SDRAM Clock Outputs, SDRAM0:7 (Test Load: R = 22Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 10 ns f Frequency, Actual Determined by PLL divider ratio 100 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 tD Duty Cycle Measured on rising and falling edge at 1.5V 45 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.5V tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1 50 4 V/ns 4 V/ns 55 % 250 ps 100 ps 850 ps 3 ms Ω 16 PCI Clock Outputs, PCI0:5 (Test Load: R = 22Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns f Frequency, Actual Determined by PLL divider ratio 33.3 MHz tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate 1 4 V/ns tF Output Fall Edge Rate 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.5V tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* 45 50 1 15 55 % 250 ps 250 ps 4 ns 3 ms Ω Page 9 of 14 www.DataSheet4U.com PRELIMINARY W215B I/O APIC Clock Output (Test Load: R = 33Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments f Frequency, Actual tR Output Rise Edge Rate tF Output Fall Edge Rate tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 1 1 45 50 Unit MHz 4 V/ns 4 V/ns 55 % 1.5 ms Ω 15 REF0 Clock Output (Test Load: R = 33Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. 14.318 Unit f Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 50 MHz 55 % 1.5 ms Ω 16 REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Max. 14.318 Unit Frequency, Actual tR Output Rise Edge Rate 0.5 2 V/ns tF Output Fall Edge Rate 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07222 Rev. *A* Frequency generated by crystal oscillator Typ. f 45 25 MHz 55 % 1.5 ms Ω Page 10 of 14 PRELIMINARY W215B 48-/24-MHz Clock Output (Test Load: R = 33Ω; C = 22 pF) CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit m/n PLL Ratio 57/17 tR Output Rise Edge Rate 0.5 2 V/ns tF Output Fall Edge Rate 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 45 50 25 Ω Ordering Information Ordering Code Package Name W215B X Package Type 48-pin TSSOP (6.1 mm) www.DataSheet4U.com Document #: 38-07222 Rev. *A* Page 11 of 14 PRELIMINARY W215B Layout Example +2.5V Supply +3.3V Supply FB FB VDDQ2 VDDQ3 0.005 µF 10 µF G G C1 G C2 C4 G G VDDQ3 5Ω C5 G G C6 0.005 µF G G 1 G 2 3 4 5 G 6 7 V 8 G 9 10 G 11 12 13 14 G 15 V 16 G 17 18 19 20 G 21 22 23 24 G C2 48 47 V 46 G 45 44 43 42 G 41 V 40 G 39 38 37 36 G 35 VDDQ3 V Core 34 G 33 32 G 31 30 G 29 V 28 G 27 26 V 25 G G G G W215B www.DataSheet4U.com 10 µF C1 C3 G G G FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) C1 & C3 = 10–22 µF C2 & C4 = 0.005 µF G = VIA to GND plane layer C5 = 47 µF C6 = 0.1 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors Document #: 38-07222 Rev. *A* Page 12 of 14 PRELIMINARY W215B Package Diagram 48-Pin Small Shrink Outline Package (TSSOP, 6.1 mm) www.DataSheet4U.com Document #: 38-07222 Rev. *A* Page 13 of 14 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W215B Document Title: W215B Notebook PC System Frequency Generator for K6 Processors Document Number: 38-07222 REV. ECN NO. Issue Date Orig. of Change ** 110487 10/21/01 SZV Change from Spec number: 38-00886 to 38-07222 *A 122839 12/15/02 RBI Added power-up requirements to maximum ratings information. Description of Change www.DataSheet4U.com Document #: 38-07222 Rev. *A* Page 14 of 14