Warp Enterprise™ Verilog CPLD Software
• Verilog (IEEE 1364) high-level language compilers
with the following features:
• VHDL or Verilog timing model output for use with
third-party simulators
• Active-HDL™ Sim Release 4.1 timing simulation from
— Designs are portable across multiple devices
and/or EDA environments
— Graphical waveform simulator
— Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level design
— Ability to compare waveforms and highlight differences before and after a design change
— Support for functions and libraries facilitating modular design methodology
— Support for reduction and conditional operators,
blocking and non-blocking procedural assignments,
while loops and integers
• Several design entry methods support high-level and
low-level design descriptions:
— Graphical HDL Block Diagram editor with a library of
blocks and a text-to-block conversion utility from Aldec
— Aldec Active-HDL™ FSM graphical Finite State
Machine editor
— Behavioral Verilog (IF...THEN...ELSE; CASE...)
— Boolean
— Graphical entry and modification of all waveforms
— Ability to probe internal nodes
— Display of inputs, outputs, and high impedance (Z)
signals in different colors
— Automatic clock and pulse creation
— Support for buses
— Unlimited simulation time
• Architecture Explorer™ analysis tool and Dynamic
Timing Simulator for PSI and Delta39K devices:
— Graphical representation of exactly how your design
will be implemented on your specific target device
— Zoom from the device level down to the macrocell
— Determine the timing for any path and view that path
on a graphical representation of the chip
— Structural Verilog
— Designs can include multiple entry methods (but
only one HDL) in a single design.
• Language Assistant library of Verilog templates
• Flow Manager Interface to keep track of complex
• UltraGen™ Synthesis and Fitting Technology:
— Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device.
• Static Timing Report for all devices
• Source-Level Behavioral Simulation and Debugger
from Aldec
• Testbench Generation
• C3ISR Programming Cable
• Delta39K\Ultra37000 prototype board with a
CY37256V 160-pin TQFP device and a CY39100V
208-pin device
• On-line documentation and help
— User-selectable speed and/or area optimization on a
block-by-block basis
Functional Description
— Perfectly integrated synthesis and fitting
Warp Enterprise™ is an integration of the Warp Professional™ CPLD Development package with additional sophisticated EDA software features from Aldec. In addition to
accepting IEEE 1364 Verilog text and graphical finite state
machines for design entry, Warp Enterprise Verilog provides a
graphical HDL block diagram editor with a library of graphical
HDL blocks pre-optimized for Cypress devices. Plus, it
provides a utility to convert HDL text into graphical HDL blocks.
Warp Enterprise synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel® hex file for the desired
PLD or CPLD (see Figure 1). For simulation, Warp Enterprise
provides a timing simulator, a source-level behavioral
simulator, as well as VHDL and Verilog timing models for use
with third party simulators. Warp Enterprise also provides the
designer with important productivity tools such as a testbench
generation wizard and the Architecture Explorer graphical
analysis tool.
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
• Ability to specify timing constraints for all of the
Delta39K and PSI devices
• Support for all Cypress Programmable Logic Devices
— PSI™ (Programmable Serial Interface)
— Delta39K™ CPLDs
— Ultra37000™ CPLDs
— FLASH370i™ CPLDs
— MAX340™ CPLDs
— Industry standard PLDs (16V8, 20V8, 22V10)
Cypress Semiconductor Corporation
Document #: 38-03045 Rev. *C
3901 North First Street
San Jose, CA 95134
Revised August 19, 2003
HDL Blocks
State Machine
The Verilog language also allows users to define their own
functions. User-defined functions allow users to extend the
capabilities of the language and build reusable files of tested
routines. Verilog provides control over the timing of events or
processes. It has constructs that identify processes as either
sequential, concurrent, or a combination of both. This feature
is essential when describing the interaction of complex state
Verilog is a rich programming language. Its flexibility reflects
the nature of modern digital systems and allows designers to
create accurate models of digital designs. Because it is not a
verbose language it is easy to learn and compile. In addition,
models created in Verilog can readily be transported to other
EDA Environments. Warp Enterprise Verilog supports IEEE
1364 Verilog including loops, reduction and conditional
A Verilog Design Example
Design Entry
VHDL, Verilog
Simulation Models
Figure 1. Warp® Design Flow
Verilog Compiler
Verilog is a powerful, industry-standard language for behavioral design entry and simulation, and is supported by all major
vendors of EDA tools. It allows designers to learn a single
language that is useful for all facets of the design process.
Verilog offers designers the ability to describe designs at many
different levels. At the highest level, designs can be entered
as a description of their behavior. This behavioral description
is not tied to any specific target device. As a result, simulation
can be done very early in the design to verify correct functionality, which significantly speeds the design process.
The Warp syntax for Verilog includes support for intermediate
level entry modes such as state tables and Boolean entry. At
the lowest level, designs can be described using gate-level
descriptions. Warp Enterprise gives the designer the flexibility
to intermix all of these entry modes.
In addition, Verilog allows you to design hierarchically, building
up entities in terms of other entities. This feature allows you to
work either “top-down” (designing the highest levels of the
system and its interfaces first, then progressing to greater and
greater detail) or “bottom-up” (designing elementary building
blocks of the system, then combining these to build larger and
larger parts) with equal ease.
Because this languages is an IEEE standard, multiple vendors
offer tools for design entry and simulation at both high and low
levels and synthesis of designs to different silicon targets. The
use of device-independent behavioral design entry gives
users the freedom to easily migrate to high volume technologies. The wide availability of Verilog tools provides complete
vendor independence as well. Designers can begin their
project using Warp Enterprise for Cypress CPLDs and
convert to high volume ASICs using the same Verilog behavioral description with industry-standard synthesis tools.
Document #: 38-03045 Rev. *C
Warp Enterprise descriptions specify:
• The behavior or structure of a design.
• the mapping of signals in a design to the pins of
a PLD/CPLD (optional).
The part of a Warp Enterprise description that specifies the
behavior or structure of the design is called a module. The
module declares the design’s interface signals (i.e., defines
what external signals the design has, and what their directions and types are).
The module portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the module specifies a signal name, a direction
and a data type. In addition, the module declaration specifies
a name by which the entity can be referenced in other
modules. This section shows code segments from four sample
design files. The top portion of each example features the
module declaration.
Behavioral Description
The module portion of a design file specifies the function of the
design. As shown in Figure 1, multiple design-entry methods
are supported in Warp Enterprise. A behavioral description
in Verilog often includes well known constructs such as
IfºElse, and Case statements. Here is a code segment from
a simple state machine design (soda vending machine) that
uses behavioral Verilog to implement the design:
MODULE drink (nickel, dime, quarter, clock,
returnDime, returnNickel,
INPUT nickel, dime, quarter, clock;
OUTPUT returnDime,returnNickel,giveDrink;
REG returnDime, returnNickel, giveDrink;
PARAMETER zero = 0, five = 1, ten = 2,
fifteen = 3, twenty = 4, twentyfive = 5
owedime = 6;
REG[1:0] drinkStatus;
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giveDrink = 0;
returnDime = 0;
returnNickel = 0;
4’b100X: BEGIN
zero: BEGIN
IF (nickel)
drinkStatus = five;
ELSE IF (dime)
drinkStatus = ten;
ELSE IF (quarter)
drinkStatus = twentyfive;
five: BEGIN
IF (nickel)
drinkStatus = ten;
ELSE IF (dime)
drinkStatus = fifteen;
ELSE IF (quarter)
drinkStatus = zero;
giveDrink = 1;
default: BEGIN
ASSIGN s=temp;
Boolean Equations
A second design-entry method available to Warp Enterprise
users is Boolean equations. Figure 2 displays a schematic of a
simple one-bit half adder. The following code describes how
this one-bit half adder can be implemented in Warp Enterprise
with Boolean equations:
// Several states are omitted in this
// example. The omitted states are ten
// fifteen, twenty, and twentyfive.
owedime: BEGIN
returnDime = 1;
drinkStatus = zero;
default: BEGIN
// This makes sure that the state
// machine resets itself if
// it somehow gets into an undefined state.
drinkStatus = zero;
Verilog is not a strongly typed language. The simplicity and
readability of the following code is increased by use of the
CASEX. The CASEX command accepts “Don’t Cares” and
chooses the branch depending on the value of the expression.
MODULE sequence (clk, s);
INPUT clk;
REG temp;
REG[3:0] count;
4’b00XX: BEGIN
4’b01XX: BEGIN
Document #: 38-03045 Rev. *C
Figure 2. One-Bit Half Adder
MODULE half_adder(x, y, sum, carry);
INPUT x, y;
OUTPUT sum, carry;
ASSIGN sum = x^y;
ASSIGN carry = x&y;
Structural Verilog
While all of the design methodologies described thus far are
high-level entry methods, structural Verilog provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 3 displays the schematic of a simple three-bit shift register
and the following code shows how this design can be described
in Warp Enterprise using structural Verilog.
MODULE shifter3 (clk, x, q0, q1, q2);
INPUT clk, x;
OUTPUT q0, q1, q2;
WIRE q0, q1, q2;
REG q0_temp, q1_temp, q2_temp;
DFF d1(x,clk,q0_temp);
DFF d2(q0_temp,clk,q1_temp);
DFF d3(q1_temp,clk,q2_temp);
ASSIGN q0 = q0_temp;
ASSIGN q1 = q1_temp;
ASSIGN q2 = q2_temp;
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Figure 3. Three-Bit Shift Register Circuit Design
All of the design-entry methods described can be mixed as
desired so long as only one HDL is used. Verilog have the
ability to combine both high- and low-level entry methods in a
single file. The flexibility and power of Verilog allow users of
Warp Enterprise to describe designs using whatever method
is appropriate for their particular design.
Finite State Machine Editor
Aldec’s Active-HDL™ FSM finite state machine editor, allows
graphic design entry through the use of graphical state
diagrams. A design may be represented graphically using
state diagrams and data flow logic. This tool will automatically
generate the HDL code of the design.
HDL Block Diagram Editor
The HDL block diagram editor lets you represent portions of
your code with graphical symbols. This representation allows
you to view the high-level structure of your complex designs
and lets you copy and paste entire modules of your design
within or between designs. The editor comes with a library of
HDL blocks optimized for Cypress devices. Warp Enterprise
comes with utility that converts HDL text into these blocks.
Language Assistant
The language assistant is a library of language templates that
you can browse and automatically insert into your HDL text.
They provide syntax and structure and give examples to aid
users who are new using a particular HDL.
Flow Manager
The flow manager is a special interface that helps you keep
track of your complex projects. It arranges the tools as part of
the logical flow the designer takes through a project and
remembers what steps have been completed on which
Source-Level Simulation
Warp Enterprise’s source-level behavioral simulator helps you
catch problems with your code early in the design process by
letting you simulate a design before synthesis. The tool lets
you graphically watch inputs and outputs, gives you timing
information and allows you to step through your code line by
Document #: 38-03045 Rev. *C
Once the Verilog description of the design is complete, it is
compiled using Warp Enterprise. Although implementation is with
a single command, compilation is actually a multistep process as
shown in Figure 1. The first part of the compilation process is the
same for all devices. The input description is synthesized to a logical
representation of the design. Warp synthesis is unique in that the
input languages support device-independent design descriptions.
Competing programmable logic compilers require very specific and
device-dependent information in the design description.
Warp synthesis is based on UltraGen technology. This
technology allows Warp Enterprise to infer adders,
subtractors, multipliers, comparators, counters and shifters
from the behavioral descriptions. Warp Enterprise then
replaces these operators internally with an architecturespecific circuit. This circuit or “module” is also pre-optimized
for either area or speed. Warp Enterprise uses the appropriate
implementation based on user directives.
The second step of compilation is an iterative process of
optimizing the design and fitting the logic into the targeted
device. Logical optimization in Warp Enterprise is accomplished
using Espresso algorithms. The optimized design is automatically
fed to the Warp Enterprise fitter for targeting a PLD or CPLD. This
fitter supports the automatic or manual placement of pin assignments as well as automatic selection of D or T flip-flops. After optimization and fitting, Warp Enterprise creates a JEDEC or Intel hex file
for the specified PLD or CPLD.
Automatic Error Tracking
Warp Enterprise features automatic error location that allows
problems to be diagnosed and corrected in seconds. Errors
from compilation are displayed immediately in a window. If the
user highlights a particular error, Warp Enterprise will automatically open the source code file and highlight the offending line
in the entered design. If the device fitting process includes
errors, a window will again describe them. A detailed report file
is generated indicating the resources required to fit the input
design and any problems that occurred in the process.
Timing Simulation
The Aldec Active-HDL Sim post-fitting timing simulator
provides timing simulation for PLDs/CPLDs and features interactive waveform viewing as well as graphical creation and
editing of all waveforms. The simulator also provides the ability
to probe internal nodes, and automatically generate clocks
and pulses. The version in Warp Enterprise has the ability to
compare waveforms and highlight differences before and after
a design change. In Warp Enterprise there is no maximum
simulation time. To use the timing simulator in Warp Enterprise
Verilog you must use a Verilog netlist.
Warp Enterprise Verilog can also output standard VHDL or
Verilog timing models that all third-party simulators can use to
perform functional and timing verifications of a synthesized
Architecture Explorer
The Architecture Explorer graphically displays how the design
will be implemented on the chip. It provides a view of the entire
device to show what memory elements and logic clusters have
been used for what part of the design. This gives the designer
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an idea of what resources are free. The Architecture Explorer
allows you to zoom in multiple times. At maximum zoom it
displays the logic gate implementation in each macrocell. The
Architecture Explorer is available for PSI and Delta39K
Timing Analyzer
The Timing Analyzer gives the time across any path as well as
the breakdown of what steps are causing the timing delays.
This tool does not simply display the general specification for
the target device but a worst-case simulation of the actual path
being taken through the device. When you highlight a path on
the timing analyzer, the source and destination of that path are
displayed on the Architecture Explorer. The timing analyzer
graphical interface is also available for PSI and Delta39K
devices. However, for other devices the same information is
available in a report file.
Cypress’s FLASH370i, Ultra37000, and Delta39K In-System
Reprogrammable™ (ISR™) devices can be programmed on
board with an ISR programmer. For PSI and Delta39K devices
Warp Enterprise produces an Intel hex file. The ISR
programmer converts this file into STAPL and programs the
device. For Ultra37000 and FLASH370i devices, Warp Enterprise produces a JEDEC file. For Ultra37000, the ISR
programmer converts this file into JAM/STAPL and programs
the device. For FLASH370i, the JEDEC file is used directly to
program the device.
Warp Enterprise comes with a C3ISR Programming Cable and
a Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin TQFP device.
The JEDEC and Intel hex files produced by Warp Enterprise
can also be used with any qualified third party programmer to
program Cypress CPLDs.
For more information on Cypress’s ISR software, see the ISR
Programming Kit (CY3900i) data sheet.
Warp® Software System Requirements
IBM PC or equivalent (Pentium® class recommended)
32 Mb of RAM (64 Mb recommended)
110 Mb Disk Space
CD-ROM drive
Windows® 98, Windows NT® 4.0, Windows XP
Warp Enterprise for Verilog hardware key
Internet access to download upgrades
ISR Software PC System Requirements
• IBM PC or compatible running Windows 98, Windows 98
Second Edition, Windows ME, Windows NT 4.0 Service
Pack 5 or later, or Windows 2000 Service Pack 1 or later
• One free parallel port
• Minimum of 32 MB of RAM
• Approximately 30 MB free hard disk space
Product Ordering Information
Product Code
Warp Enterprise Verilog CPLD software for
Warp Enterprise includes:
• Cypress Lab CD-ROM with Warp Enterprise, ISR
software, on-line documentation (Getting Started Manual,
User’s Guide, HDL Reference Manual, Databook) and
other Cypress software
• C3ISR Programming Cable
• Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin TQFP
Intel and Pentium are registered trademarks of Intel Corporation. Windows and Windows NT are registered trademarks of
Microsoft Corporation. Solaris is a trademark of Sun Microsystems Corporation. Warp is a registered trademark, and Warp
Professional, Warp Enterprise, UltraGen, Ultra37000, Delta39K, PSI, MAX340, ISR, In-System Reprogrammable, and
FLASH370i are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-03045 Rev. *C
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© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document History Page
Document Title: CY3138 Warp Enterprise™ Verilog CPLD Software
Document Number: 38-03045
ECN NO. Issue Date
Orig. of
Description of Change
Change from Spec number: 38-01032 to 38-03045
Update product code, remove references to Windows95
Added timing constraints, Windows XP and Internet Access
Removed Quantum38K from all pages
Document #: 38-03045 Rev. *C
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