CYS25G0101DX SONET OC-48 Transceiver Features Functional Description ■ SONET OC-48 operation ■ Bellcore and ITU jitter compliance ■ 2.488 GBaud serial signaling rate ■ Multiple selectable loopback or loop through modes ■ Single 155.52 MHz reference clock ■ Transmit FIFO for flexible data interface clocking ■ 16-bit parallel-to-serial conversion in transmit path ■ Serial-to-16-bit parallel conversion in receive path ■ Synchronous parallel interface ❐ LVPECL compliant ❐ HSTL compliant Transmit Path New data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out to the high speed differential line driver at a rate of 2.488 Gbits/second. Receive Path ■ Internal transmit and receive phase-locked loops (PLLs) ■ Differential CML serial input ❐ 50 mV input sensitivity ❐ 100Ω Internal termination and DC restoration ■ Differential CML serial output ❐ Source matched for 50Ω transmission lines (100Ω differential transmission lines) ■ Direct interface to standard fiber optic modules ■ Less than 1.0W typical power ■ 120-pin 14 mm × 14 mm TQFP ■ Standby power saving mode for inactive loops ■ 0.25µ BiCMOS technology ■ Pb-free packages available Cypress Semiconductor Corporation Document Number: 38-02009 Rev. *K The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance. • As serial data is received at the differential line receiver, it is passed to a clock and data recovery (CDR) PLL that extracts a precision low jitter clock from the transitions in the data stream. This bit rate clock is used to sample the data stream and receive the data. Every 16-bit times, a new word is presented at the receive parallel interface along with a clock. Parallel Interface The parallel I/O interface supports high speed bus communications using HSTL signaling levels to minimize both power consumption and board landscape. The HSTL outputs are capable of driving unterminated transmission lines of less than 70 mm and terminated 50Ω transmission lines of more than twice that length. The CYS25G0101DX Transceiver’s parallel HSTL I/O can also be configured to operate at LVPECL signaling levels. This is done externally by changing VDDQ, VREF and creating a simple circuit at the termination of the transceiver’s parallel output interface. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 27, 2007 CYS25G0101DX Logic Block Diagram (155.52 MHz) TXCLKI TXD[15:0] FIFO_ERR TXCLKO (155.52 MHz) RXCLK (155.52 MHz) REFCLK± RXD[15:0] FIFO_RST 16 16 Input Register Output Register TX PLL X16 ÷16 Shifter FIFO ÷16 Recovered Bit-Clock TX Bit-Clock Shifter RX CDR PLL Retimed Data Lock-to-Ref LOOPTIME DIAGLOOP Lock-to-Data/ Clock Control Logic LINELOOP LOOPA OUT± Document Number: 38-02009 Rev. *K PWRDN LOCKREF SD LFI RESET IN± Page 2 of 17 CYS25G0101DX Clocking The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated Timing Source) reference clock. The low jitter of the CDR PLL allows loop timed operation of the transmit data path meeting all Bellcore and ITU jitter requirements. Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power. System or Telco Bus Figure 1. CYS25G0101DX System Connections SONET Data Processor 16 Transmit Data Interface Host Bus Interface Document Number: 38-02009 Rev. *K Receive Data Interface 16 CYS25G0101DX TXD[15:0] TXCLKI FIFO_RST FIFO_ERR TXCLKO REFCLK± 2 155.52 MHz BITS Time Reference RXD[15:0] RXCLK Data & Clock Direction Control LOOPTIME DIAGLOOP LOOPA LINELOOP Status and System Control RESET PWRDN LOCKREF LFI IN+ IN– SD OUT– OUT+ Serial Data Serial Data RD+ RD– SD TD– TD+ Optical XCVR Optical Fiber Links Page 3 of 17 CYS25G0101DX Pin Configuration The pin configuration for 120-pin Thin Quad Flatpack follows. [1, 2] O UT– O UT+ VCCQ VSSQ VCCQ NC NC VSSQ NC VSSQ VCCQ NC NC NC 104 103 102 101 100 99 98 96 95 94 93 92 91 97 CM_SER 107 VCCQ VSSQ 108 105 IN– 109 106 VCCQ IN+ 110 VCCQ VSSQ 111 VSSQ \NC* 113 112 RXCN1 114 115 RXCN2 VCCQ \NC* RXCP1 116 118 117 VSSQ \NC* RXCP2 119 NC VCCQ VSSQ REFCLK+ REFCLK– NC LO OPTIME PW RDN VSSN VCCN VSSN TXCLKO VSSN VDDQ TXD TXD TXD TXD VCCQ VSSQ VCCN VSSN TXD TXD TXD TXD TXD TXD TXD TXD VREF VCC N VSSN TXCLKI TXD TXD TXD TXD FIFO_RST FIFO_ERR VSSN VCC N VSSN VDDQ RXD RXD RXD RXD VD DQ RXD RXD RXD VC CQ RXD NC 74 73 72 71 70 69 68 67 66 65 64 63 62 61 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSSN NC 25 26 27 28 29 30 31 VSSQ NC 17 18 19 20 21 22 23 24 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 CYS25G0101DX VCCQ NC VSSN SD LOCKREF R XD R XD R XD R XD VSSN VDDQ R XD R XD R XD R XD VSSN VDDQ RXCLK VSSN VDDQ NC NC NC Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSSQ LFI RESET DIAG LOOP LINELOO P LOOPA VSSN VCCN VSSN 120 Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration Notes 1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of the device. 2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices. Document Number: 38-02009 Rev. *K Page 4 of 17 CYS25G0101DX Pin Descriptions CYS25G0101DX OC-48 SONET Transceiver Pin Name I/O Characteristics Signal Description Transmit Path Signals TXD[15:0] HSTL inputs, Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI↑. TXD is the most sampled by TXCLKI↑ significant bit (the first bit transmitted). TXCLKI HSTL Clock input Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of the clock cycle. TXCLKO HSTL Clock output Transmit Clock Output. Divide by 16 of the selected transmit bit rate clock. It is used to coordinate byte wide transfers between upstream logic and the CYS25G0101DX. VREF Input Analog Reference Reference Voltage for HSTL Parallel Input Bus. VDDQ/2. Receive Path Signals RXD[15:0] HSTL output, synchronous Parallel Receive Data Output. These outputs change following RXCLK↓. RXD is the most significant bit of the output word and is received first on the serial interface. RXCLK HSTL Clock output Receive Clock Output. Divide by 16 of the bit rate clock extracted from the received serial stream. RXD [15:0] is clocked out on the falling edge of the RXCLK. CM_SER Analog Common Mode Termination. Capacitor shunt to VSS for common mode noise. RXCN1 Analog Receive Loop Filter Capacitor (Negative). RXCN2 Analog Receive Loop Filter Capacitor (Negative). RXCP1 Analog Receive Loop Filter Capacitor (Positive). RXCP2 Analog Receive Loop Filter Capacitor (Positive). Device Control and Status Signals REFCLK± Differential LVPECL input Reference Clock. This clock input is used as the timing reference for the transmit and receive PLLs. A derivative of this input clock is used to clock the transmit parallel interface. The reference clock is internally biased enabling for an AC coupled clock signal. LFI LVTTL output Line Fault Indicator. When LOW, this signal indicates that the selected receive data stream is detected as invalid by either a LOW input on SD or by the receive VCO operated outside its specified limits. RESET LVTTL input Reset for all logic functions except the transmit FIFO. LOCKREF LVTTL input Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. SD LVTTL input Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. The SD needs to be connected to an external optical module to indicate a loss of received optical power. FIFO_ERR LVTTL output Transmit FIFO Error. When HIGH, the transmit FIFO has either under or overflowed. When this occurs, the FIFO’s internal clearing mechanism clears the FIFO within nine clock cycles. In addition, FIFO_RST is activated at device power up to ensure that the in and out pointers of the FIFO are set to maximum separation. FIFO_RST LVTTL input Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation. FIFO_RST is activated at device power up to ensure that the in and out pointers of the FIFO are set to maximum separation. When the FIFO is reset, the output data is a 1010... pattern. PWRDN LVTTL input Device Power Down. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated. Note 3. VREF equals to (VCC – 1.33V) if interfacing to a parallel LVPECL interface. Document Number: 38-02009 Rev. *K Page 5 of 17 CYS25G0101DX CYS25G0101DX OC-48 SONET Transceiver (continued) Pin Name I/O Characteristics Signal Description Loop Control Signals DIAGLOOP LVTTL input Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery. It is then presented at the RXD[15:0] outputs. LINELOOP LVTTL input Line Loopback Control. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT± line driver is generated in the transmit shifter. LOOPA LVTTL input Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT± line driver is controlled by LINELOOP. LOOPTIME LVTTL input Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock. OUT± Differential CML output Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50Ω transmission lines or commercial fiber optic transmitter modules. IN± Differential CML input Differential Serial Data Input. This differential input accepts the serial data stream for deserialization and clock extraction. Serial I/O Power VCCN Power +3.3V supply (for digital and low speed IO functions) VSSN Ground Signal and power ground (for digital and low speed IO functions) VCCQ Power +3.3V quiet power (for analog functions) VSSQ Ground Quiet ground (for analog functions) VDDQ Power +1.5V supply for HSTL outputs CYS25G0101DX Operation The CYS25G0101DX is a highly configurable device designed to support reliable transfer of large quantities of data using high speed serial links. It performs necessary clock and data recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. CYS25G0101DX also provides various loopback functions. CYS25G0101DX Transmit Data Path Operating Modes The transmit path of the CYS25G0101DX supports 16-bit wide data paths. Phase Align Buffer Data from the input register is passed to a phase align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase align buffer takes place when the FIFO_RST input is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase, relative to TXCLKO, is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK (that is, ±180°). This time shift allows the delay path of the character clock (relative to REFLCK) to change due to operating voltage and temperature not affecting the desired operation. FIFO_RST is an asynchronous input. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, the transmit FIFO has either under or overflowed. The FIFO is externally reset to clear the error indication; or if no action is taken, the internal clearing mechanism clears the FIFO in nine clock cycles. When the FIFO is being reset, the output data is 1010. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a 155.52 MHz external clock at the REFCLK input. It multiplies that clock by 16 to generate a bit rate clock for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies is listed in Table 7 on page 11. The REFCLK phase noise limits to meet SONET compliancy are shown in Figure 6 on page 13. The REFCLK± input is a standard LVPECL input. Note 4. VDDQ equals VCC if interfacing to a parallel LVPECL interface. Document Number: 38-02009 Rev. *K Page 6 of 17 CYS25G0101DX Serializer The parallel data from the phase align buffer is passed to the Serializer that converts the parallel data to serial data. It uses the bit rate clock generated by the Transmit PLL clock multiplier. TXD is the most significant bit of the output word and is transmitted first on the serial interface. Serial Output Driver The Serial Interface Output Driver makes use of high performance differential Current Mode Logic (CML) to provide a source matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard LVPECL drivers and are capable of driving AC coupled optical modules or transmission lines. CYS25G0101DX Receive Data Path Serial Line Receivers A differential line receiver, IN±, is available for accepting the input serial data stream. The serial line receiver inputs accommodate high wire interconnect and filtering losses or transmission line attenuation (VSE > 25 mV, or 50 mV peak-to-peak differential). It can be AC coupled to +3.3V or +5V powered fiber optic interface modules. The common mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Lock to Data Control Line Receiver routed to the clock and data recovery PLL is monitored for: ■ status of signal detect (SD) pin ■ status of LOCKREF pin. This status is presented on the Line Fault Indicator (LFI) output, that changes asynchronously in the cases in which SD or LOCKREF go from HIGH to LOW. Otherwise, it changes synchronously to the REFCLK. Clock Data Recovery The extraction of a bit rate clock and recovery of data bits from received serial stream is performed by a Clock Data Recovery (CDR) block. The clock extraction function is performed by high performance embedded phase-locked loop (PLL) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit rate clock to the transitions in the selected serial data stream. CDR accepts a character rate (bit rate * 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit rate), to improve PLL acquisition time and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR attempts to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL tracks REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK must be within ±100 ppm of Document Number: 38-02009 Rev. *K the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. For systems using multiple or redundant connections, the LFI output can be used to select an alternate data stream. When an LFI indication is detected, external logic toggles selection of the input device. When such a port switch takes place, it is necessary for the PLL to reacquire lock to the new serial stream. External Filter The CDR circuit uses external capacitors for the PLL filter. A 0.1 µF capacitor needs to be connected between RXCN1 and RXCP1. Similarly a 0.1 µF capacitor needs to be connected between RXCN2 and RXCP2. The recommended packages and dielectric material for these capacitors are 0805 X7R or 0603 X7R. Deserializer The CDR circuit extracts bits from the serial data stream and clocks these bits into the Deserializer at the bit clock rate. The Deserializer converts serial data into parallel data. RXD is the most significant bit of the output word and is received first on the serial interface. Loopback Timing Modes CYS25G0101DX supports various described in the following sections. loopback modes, as Facility Loopback (Line Loopback with Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high speed serial receive data (IN±) is presented to the high speed transmit output (OUT±) after retiming. In Facility Loopback mode, the high speed receive data (IN±) is also converted to parallel data and presented to the low speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low-speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback with Retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN±. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (Non-retimed Data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and the receive bit rate clock is used for the transmit side shifter. Reset Modes ALL logic circuits in the device are reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset. Page 7 of 17 CYS25G0101DX Power Down Mode DC Input Voltage ................................... –0.5V to VCC + 0.5V CYS25G0101DX provides a global power down signal PWRDN. When LOW, this signal powers down the entire device to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. Static Discharge Voltage........................................... > 1100V (MIL-STD-883, Method 3015) LVPECL Compliance Power supply sequencing is not required if you are configuring VDDQ=3.3V and all power supplies pins are connected to the same 3.3V power supply. The CYS25G0101DX HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLKI are made LVPECL compliant by setting VREF (reference voltage of a LVPECL signal) to VCC – 1.33V. To emulate an LVPECL signal on the receiver side, set the VDDQ to 3.3V and the transmission lines needs to be terminated with the Thévenin equivalent of Zο at LVPECL ref. The signal is then attenuated using a series resistor at the driver end of the line to reduce the 3.3V swing level to an LVPECL swing level (see Figure 10). This circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO, and RXCLK. The voltage divider is calculated assuming the system is built with 50Ω transmission lines. Maximum Ratings Latch up Current..................................................... > 200 mA Power Up Requirements Power supply sequencing is required if you are configuring VDDQ=1.5V. Power is applied in the following sequence: VCC (3.3) followed by VDDQ (1.5). Power supply ramping may occur simultaneously as long as the VCC/VDDQ relationship is maintained. Operating Range Range Ambient Temperature Commercial 0°C to +70°C Industrial VDDQ VCC 1.4V to 1.6V 3.3V ± 10% –40°C to +85°C 1.4V to 1.6V 3.3V ± 10% Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C VCC Supply Voltage to Ground Potential ........–0.5V to +4.2V VDDQ Supply Voltage to Ground Potential ......–0.5V to +4.2V DC Voltage Applied to HSTL Outputs in High Z State ..................................... –0.5V to VDDQ + 0.5V DC Voltage Applied to Other Outputs in High Z State ....................................... –0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW) ................. 30 mA Table 1. DC Specifications—LVTTL Parameter Description Test Conditions Min Max Unit 0.4 V –20 –90 mA LVTTL Outputs VOHT Output HIGH Voltage VCC = Min, IOH = –10.0 mA VOLT Output LOW Voltage VCC = Min, IOL = 10.0 mA IOS Output Short Circuit Current VOUT = 0V 2.4 V LVTTL Inputs VIHT Input HIGH Voltage Low = 2.1V, High = VCC + 0.5V 2.1 VCC – 0.3 V VILT Input LOW Voltage Low = –3.0V, High = 0.8 –0.3 0.8 V IIHT Input HIGH Current VCC = Max, VIN = VCC 50 µA IILT Input LOW Current VCC = Max, VIN = 0V –50 µA Input Capacitance VCC = Max, at f = 1 MHz 5 pF Capacitance CIN Document Number: 38-02009 Rev. *K Page 8 of 17 CYS25G0101DX Table 2. DC Specifications—Power Parameter Description Test Conditions Typ Max Unit 300 347 mA 5 mA Max Unit Power ICC1 Active Power Supply Current ISB Standby Current Table 3. DC Specifications—Differential LVPECL Compatible Inputs (REFCLK) The DC Specifications—Differential LVPECL Compatible Inputs (REFCLK) follow.  Parameter Description Test Conditions Min VINSGLE Input Single-ended Swing 200 600 mV VDIFFE Input Differential Voltage 400 1200 mV VIEHH Highest Input HIGH Voltage VCC – 1.2 VCC – 0.3 V VIELL Lowest Input LOW Voltage VCC – 2.0 VCC – 1.45 V IIEH Input HIGH Current VIN = VIEHH Max. 750 µA IIEL Input LOW Current VIN = VIELL Min. µA –200 Capacitance CINE Input Capacitance 4 pF Table 4. DC Specifications—Differential CML The DC Specifications—Differential CML follow.  Parameter Description Test Conditions Min Max Unit Transmitter CML compatible Outputs VOLC Output LOW Voltage (VCC Referenced) 100Ω differential load VCC – 0.5 VCC – 0.15 100Ω differential load VCC – 1.2 VCC – 0.7 VDIFFOC Output Differential Swing 100Ω differential load 560 1600 mV VSGLCO Output Single-ended Voltage 100Ω differential load 280 800 mV VOHC Output HIGH Voltage (VCC Referenced) V V Receiver CML compatible Inputs VINSGLC Input Single-ended Swing 25 1000 mV VDIFFC Input Differential Voltage 50 2000 mV VICHH Highest Input HIGH Voltage VICLL Lowest Input LOW Voltage VCC 1.2 V V Figure 3. Differential Waveform Definition V (+ ) V SGL V (-) VD 0 .0 V V D IF F = V (+ )-V (-) 5. See Figure 3 for differential waveform definition. Document Number: 38-02009 Rev. *K Page 9 of 17 CYS25G0101DX Table 5. DC Specifications—HSTL Parameter Description Test Conditions Min Max Unit HSTL Outputs VOHH Output HIGH Voltage VCC = min, IOH= –4.0 mA VDDQ – 0.4 V VOLH Output LOW Voltage VCC = min, IOL= 4.0 mA 0.4 V IOSH Output Short Circuit Current VOUT = 0V 100 mA HSTL Inputs VIHH Input HIGH Voltage VREF + 0.13 VDDQ + 0.3 –0.3 VREF – 0.1 V VILH Input LOW Voltage IIHH Input HIGH Current VDDQ = max, VIN = VDDQ 50 µA IILH Input LOW Current VDDQ = max, VIN = 0V –40 µA Input Capacitance VDDQ = max, at f = 1 MHz 5 pF V Capacitance CINH AC Waveforms VICHH 3.0V 3.0V Vth = 1.4V GND 2.0V 2.0V 0.8V 0.8V 80% Vth = 1.4V < 1 ns < 1 ns 20% VICLL < 150 ps (a) LVTTL Input Test Waveform VIEHH 80% 80% 80% Vth = 0.75V 20% 20% < 150 ps (b) CML Input Test Waveform VIHH Vth = 0.75V 80% 20% VIHL < 1 ns < 1 ns 80% 20% 20% VIELL < 1.0 ns < 1.0 ns (d) LVPECL Input Test Waveform (c) HSTL Input Test Waveform AC Test Loads 1.5V 3.3V R1 OUTPUT R1 = 330Ω R2 = 510Ω CL ≤ 10 pF (Includes fixture and probe capacitance) OUT+ CL (a) TTL AC Test Load Document Number: 38-02009 Rev. *K RL = 100Ω R2 OUT– RL (b) CML AC Test Load R1 OUTPUT R1 = 100Ω R2 = 100Ω CL ≤ 7 pF (Includes fixture and probe capacitance) CL R2 (c) HSTL AC Test Load Page 10 of 17 CYS25G0101DX AC Specifications Table 6. AC Specifications—Parallel Interface Parameter Description Min Max Unit tTS TXCLKI Frequency (must be frequency coherent to REFCLK) 154.5 156.5 MHz tTXCLKI TXCLKI Period 6.38 6.47 ns tTXCLKID TXCLKI Duty Cycle 40 60 % tTXCLKIR TXCLKi Rise Time 0.3 1.5 ns tTXCLKIF TXCLKi Fall Time 0.3 1.5 tTXDS Write Data Setup to ↑ of TXCLKI 1.5 tTXDH Write Data Hold from ↑ of TXCLKI tTOS TXCLKO Frequency 154.5 156.5 MHz tTXCLKO TXCLKO Period 6.38 6.47 ns tTXCLKOD TXCLKO Duty Cycle 43 57 % ns ns 0.5 ns tTXCLKOR TXCLKO Rise Time 0.3 1.5 ns tTXCLKOF TXCLKO Fall Time 0.3 1.5 ns tRS RXCLK Frequency 154.5 156.5 MHz tRXCLK RXCLK Period 6.38 6.47 ns tRXCLKD RXCLK Duty Cycle 43 57 % tRXCLKR RXCLK Rise Time 0.3 1.5 ns tRXCLKF RXCLK Fall Time 0.3 1.5 ns tRXDS Recovered Data Setup with reference to ↑ of RXCLK 2.2 tRXDH Recovered Data Hold with reference to ↑ of RXCLK 2.2 tRXPD Valid Propagation Delay –1.0 1.0 ns Min Max Unit ns ns Table 7. AC Specifications—REFCLK The AC Specifications—REFCLK follow.  Parameter Description tREF REFCLK Input Frequency 154.5 156.5 MHz tREFP REFCLK Period 6.38 6.47 ns tREFD REFCLK Duty Cycle tREFT REFCLK Frequency Tolerance — (relative to received serial data) 35 65 % –100 +100 ppm tREFR tREFF REFCLK Rise Time 0.3 1.5 ns REFCLK Fall Time 0.3 1.5 ns Max Unit Table 8. AC Specifications–CML Serial Outputs Parameter Description Min Typical tRISE CML Output Rise Time (20–80%, 100Ω balanced load) 60 170 ps tFALL CML Output Fall Time (80–20%, 100Ω balanced load) 60 170 ps Notes 6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal. 7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in Figure 6. 8. +20 ppm is required to meet the SONET output frequency specification. Document Number: 38-02009 Rev. *K Page 11 of 17 CYS25G0101DX Table 9. Jitter Specifications Parameter tTJ-TXPLL tTJ-RXPLL Description Min  Typical Max Unit Total Output Jitter for TX PLL (p-p) 0.03 0.04 UI Total Output Jitter for TX PLL (rms)[9, 11] 0.007 0.008 UI Total Output Jitter for RX CDR PLL (p-p) 0.035 0.05 UI Total Output Jitter for RX CDR PLL (rms)[9, 11] 0.008 0.01 UI Jitter Waveforms The Jitter Transfer Waveform of CYS25G0101DX follows. . Figure 4. Jitter Transfer Waveform of CYS25G0101DX The Jitter Tolerance Waveform of CYS25G0101DX follows.  Figure 5. Jitter Tolerance Waveform of CYS25G0101DX Notes 9. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter. 10. Typical values are measured at room temperature and the Max values are measured at 0° C. 11. This device passes the Bellcore specification from -10° C to 85° C. 12. The bench jitter measurements are performed using an Agilent Omni bert SONET jitter tester. Document Number: 38-02009 Rev. *K Page 12 of 17 CYS25G0101DX Figure 6. CYS25G0101DX Reference Clock Phase Noise Limits CYS25G0101DX Reference Clock Phase Noise Limits -75 -85 Phase Noise (dBc) -95 -105 -115 -125 -135 -145 -155 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) Switching Waveforms Transmit Interface Timing tTXCLKI tTXCLKIDH tTXCLKIDL TXCLKI t TXDS tTXDH TXD[15:0] tTXCLKO tTXCLKODL tTXCLKODH TXCLKO Receive Interface Timing Document Number: 38-02009 Rev. *K Page 13 of 17 CYS25G0101DX Typical IO Terminations Figure 7. Serial Input Termination CY S25G0101DX Limiting Amp 0.1 µ F Zo=50 Ω IN+ OUT+ 100 Ω OUT– IN– Zo=50 Ω 0.1 µF Figure 8. Serial Output termination  Optical Module CY S25G0101DX 0.1 µ F Zo=50 Ω IN+ OUT+ 100 Ω OUT– IN– Zo=50 Ω 0.1 µF Figure 9. TXCLKO/ RXCLK Termination CY S25G0101DX FRAMER VDDQ=1.5V Zo=50 Ω HSTL OUTPU T 100 Ω HSTL INPUT 100 Ω Figure 10. RXD[15:0] Termination CY S25G0101DX FRAMER Zo=50 Ω HSTL OUTPU T HSTL INPUT Figure 11. LVPECL Compliant Output Termination VDDQ=3.3V RXD[15;0], RXCLK, TXCLKO OUTPUT FRAMER VDDQ=3.3V 137 Ω Zo=50 Ω 80.6Ω LVPECL INPUT 121 Ω CY S25G0101DX Note 13. Serial output of CYS25G0101DX is source matched to 50Ω transmission lines (100Ω differential transmission lines). Document Number: 38-02009 Rev. *K Page 14 of 17 CYS25G0101DX Figure 12. AC Coupled Clock Oscillator Termination Clock Oscillator Zo=50 Ω LVPEC L OUTPUT 130 Ω 82 Ω Zo=50 Ω CY S25G0101DX VCC VCC 0.1uF VCC 130 Ω 82 Ω Refcloc k I nter nall y Biased 0.1uF Figure 13. Clock Oscillator Termination Clock Oscillator Zo=50 Ω LVPEC L OUTPUT Document Number: 38-02009 Rev. *K 130 Ω 82 Ω Zo=50 Ω CY S25G0101DX VCC VCC 130 Ω 82 Ω Reference Cloc k Input Page 15 of 17 CYS25G0101DX Ordering Information Speed Ordering Code Package Name Package Type Operating Range Standard CYS25G0101DX-ATC AT120 120-pin TQFP Commercial Standard CYS25G0101DX-ATXC AT120 120-pin Pb-Free TQFP Commercial Standard CYS25G0101DX-ATI AT120 120-pin TQFP Industrial Standard CYS25G0101DX-ATXI AT120 120-pin Pb-Free TQFP Industrial Package Diagram Figure 14. 120-Pin Thin Quad Flatpack (14 × 14 × 1.4 mm) with Heat Slug AT120 51-85116-** Document Number: 38-02009 Rev. *K Page 16 of 17 CYS25G0101DX Document History Document Title: CYS25G0101DX SONET OC-48 Transceiver Document Number: 38-02009 REV. ECN NO. Issue Date Orig. of Change ** 105847 03/22/01 SZV Change from Specification number: 38-00894 to 38-02009. *A 108024 06/20/01 AMV Changed Marketing part number. *B 111834 12/18/01 CGX Updated power specification in features and DC specifications section. Changed pinout for compatibility with CYS25G0102DX in pin diagram and descriptions. Verbiage added or changed for clarity in pin descriptions section. Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise time corrected to 0.3 nSec min CML and LVPECL input waveforms updated in test load and waveform section. Diagrams replaced for clarity Figures 1-10. Added two Refclock diagrams Figures 9 and 10. *C 112712 02/06/02 TME Updated temperature range, static discharge voltage, and max total RMS jitter. *D 113791 04/24/02 CGX Updated the single ended swing and differential swing voltage for Receiver CML compatible inputs. Created a separate table showing peak to peak and RMS jitter for both TX PLL and RX PLL. *E 115940 05/22/02 TME Added Industrial temperature specification to pages 8, 11, and 15. *F 117906 09/06/02 CGX Added differential waveform definition. Added BGA pinout and package information. Changed LVTTL VIHT min from 2.0 to 2.1 volts. *G 119267 10/17/02 CGX Added phase noise limits data. Removed BGA pinout and package information. Removed references to CYS25G0102DX. Description of Change *H 121019 11/06/02 CGX Removed “Preliminary” from datasheet *I 122319 12/30/02 RBI Added power up requirements to Maximum Ratings information *J 124438 02/13/03 WAI Revised power up requirements *K 1309983 07/27/07 IUS/SFV Added Pb-free logo Added Pb-free parts to the Ordering Information: CYS25G0101DX-ATXC, CYS25G0101DX-ATXI © Cypress Semiconductor Corporation, 2001 - 2007. The information contained herein is subject to change without notice. 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