CY29351 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer Features • • • • • • • • • • • • • • Functional Description Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2.5% max Output duty cycle variation 9 Clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9351 Industrial temperature range: –40°C to +85°C 32-Pin 1.0-mm TQFP package The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Functional Table. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. REF_SEL PLL_EN TCLK VSS QA VDDQB QB VSS 30 29 28 27 26 25 REF_SEL 31 SELA PLL_EN 32 Pin Configuration Block Diagram TCLK 13 14 15 16 VSS QD3 VDDQD QD2 QC0 C Y29351 12 ÷4 / ÷8 24 23 22 21 20 19 18 17 QD4 QB 1 2 3 4 5 6 7 8 11 ÷4 / ÷8 A VD D FB_IN SELA SELB SELC SELD A VSS PE CL_C LK VDD FB_IN SELB QA 9 LPF ÷2 / ÷4 10 VCO 200 500 MHz OE# Phase Detector PECL_CLK# PECL_CLK QC0 VD D Q C QC1 VS S QD0 VD D Q D QD1 VS S QC1 SELC OE# ÷4 / ÷8 QD0 QD1 SELD QD2 QD3 QD4 Cypress Semiconductor Corporation Document #: 38-07475 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 26, 2004 CY29351 Pin Definitions[1] Pin Name I/O Type 8 PECL_CLK I, PU LVPECL LVPECL reference clock input 9 PECL_CLK# I, PU/PD LVPECL LVPECL reference clock input. Weak pull-up to VDD/2. I, PD Description 30 TCLK 28 QA O LVCMOS Clock output bank A LVCMOS LVCMOS/LVTTL reference clock input 26 QB O LVCMOS Clock output bank B 22, 24 QC(1,0) O LVCMOS Clock output bank C 12, 14, 16, 18, 20 QD(4:0) O LVCMOS Clock output bank D 2 FB_IN I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 10 OE# I, PD LVCMOS Output enable/disable input. See Table 2. 31 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 32 REF_SEL I, PD LVCMOS Reference select input. See Table 2. I, PD LVCMOS Frequency select input, Bank (A:D). See Table 2. 3, 4, 5, 6 SEL(A:D) 27 VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clock[2,3] 23 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks[2,3] 15, 19 VDDQD Supply VDD 2.5V or 3.3V Power supply for bank D output clocks[2,3] 1 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL[2,3] 11 VDD Supply VDD 2.5V or 3.3V Power supply for core, inputs, and bank A output clock[2,3] 7 AVSS Supply Ground Analog ground 13, 17, 21, 25, 29 VSS Supply Ground Common ground Table 1. Frequency Table Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) Feedback Output Divider VCO ÷2 Input Clock * 2 100 MHz to 200 MHz ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 95MHz ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 47.5MHz 100 MHz to 190MHz Table 2. Function Table Control Default 0 REF_SEL 0 PCLK 1 PLL_EN 1 Bypass mode, PLL disabled. The input clock connects to the output dividers PLL enabled. The VCO output connects to the output dividers OE# 0 Outputs enabled Outputs disabled (three-state), VCO running at its minimum frequency SELA 0 ÷ 2 (Bank A) ÷ 4 (Bank A ) SELB 0 ÷ 4 (Bank B) ÷ 8 (Bank B) TCLK SELC 0 ÷ 4 (Bank C) ÷ 8 (Bank C) SELD 0 ÷ 4 (Bank D) ÷ 8 (Bank D) Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins. Document #: 38-07475 Rev. *A Page 2 of 8 CY29351 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD DC Supply Voltage –0.3 5.5 V VDD DC Operating Voltage Functional 2.375 3.465 V VIN DC Input Voltage Relative to VSS –0.3 VDD + 0.3 V DC Output Voltage Relative to VSS –0.3 VDD + 0.3 V – VDD ÷ 2 V Functional 200 – mA VOUT VTT Output termination Voltage LU Latch-up Immunity RPS Power Supply Ripple Ripple Frequency < 100 kHz – 150 mVp-p TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – +150 °C ØJC Dissipation, Junction to Case Functional 42 °C/W ØJA Dissipation, Junction to Ambient Functional 105 °C/W ESDH FIT ESD Protection (Human Body Model) Failure in Time 2000 – Manufacturing test Volts 10 ppm DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Min. Typ. Max. Unit VIL Input Voltage, Low LVCMOS – – 0.7 V VIH Input Voltage, High LVCMOS 1.7 – VDD+0.3 V VPP Peak-Peak Input Voltage LVPECL 250 – 1000 mV VCMR Common Mode Range[4] LVPECL 1.0 – VDD – 0.6 V Low[5] VOL Output Voltage, VOH Output Voltage, High[5] IOL = 15mA IOH = –15mA – – 0.6 V 1.8 – – V IIL Input Current, Low[6] VIL = VSS – – –100 µA IIH Input Current, High[6] VIL = VDD – – 100 µA IDDA PLL Supply Current AVDD only – 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD – – 7 mA Dynamic Supply Current Outputs loaded @ 100 MHz – 180 – mA Outputs loaded @ 200 MHz – 210 – IDD CIN ZOUT Input Pin Capacitance – 4 – pF Output Impedance 14 18 22 Ω Min. Typ. Max. Unit DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS – – 0.8 V VIH Input Voltage, High LVCMOS 2.0 – VDD + 0.3 V VPP Peak-Peak Input Voltage LVPECL 250 – 1000 mV VCMR Common Mode Range[4] LVPECL 1.0 – VDD – 0.6 V IOL = 24 mA – – 0.55 V IOL = 12 mA – – 0.30 VOL VOH Output Voltage, Low[5] Output Voltage, High[5] IOH = –24 mA 2.4 – – V Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07475 Rev. *A Page 3 of 8 CY29351 DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued) Parameter Description IIL Input Current, Low[6] [6] IIH Input Current, High IDDA PLL Supply Current IDDQ Condition VIL = VSS Min. Typ. Max. Unit – – –100 µA VIL = VDD – – 100 µA AVDD only – 5 10 mA Quiescent Supply Current All VDD pins except AVDD – – 7 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz – 270 – mA CIN Input Pin Capacitance Outputs loaded @ 200 MHz ZOUT Output Impedance AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency frefDC Input Duty Cycle VPP Peak-Peak Input Voltage VCMR – 300 – – 4 – pF 12 15 18 Ω Min. Typ. Max. Unit 200 – 380 MHz MHz [7] Condition ÷2 Feedback 100 – 190 ÷4 Feedback 50 – 95 ÷8 Feedback 25 – 47.5 Bypass mode (PLL_EN = 0) 0 – 200 25 – 75 % LVPECL 500 – 1000 mV Common Mode Range[8] LVPECL 1.2 – VDD – 0.6 V tr , tf TCLK Input Rise/FallTime 0.7V to 1.7V – – 1.0 ns fMAX Maximum Output Frequency ÷2 Output 100 – 190 MHz ÷4 Output 50 – 95 ÷8 Output 25 – 47.5 47.5 – 52.5 fMAX > 100 MHz 45 – 55 0.6V to 1.8V 0.1 – 1.0 ns TCLK to FB_IN –100 – 100 ps PCLK to FB_IN –100 – 100 DC Output Duty Cycle fMAX < 100 MHz tr , tf Output Rise/Fall times t(φ) Propagation Delay (static phase offset) % tsk(O) Output-to-Output Skew – – 150 ps tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time BW PLL Closed Loop Bandwidth (–3dB) tJIT(CC) tJIT(PER) Cycle-to-Cycle Jitter Period Jitter – – 10 ns ÷2 Feedback – 2.2 – MHz ÷4 Feedback – 0.85 – ÷8 Feedback – 0.6 – Same frequency – – 150 Multiple frequencies – – 250 Same frequency – – 100 Multiple frequencies – – 175 ps ps tJIT(φ) I/O Phase Jitter – 175 – ps tLOCK Maximum PLL Lock Time – – 1 ms Notes: 7. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). Document #: 38-07475 Rev. *A Page 4 of 8 CY29351 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [7] Parameter Description fVCO VCO Frequency fin Input Frequency Condition Min. Typ. Max. Unit 200 – 500 MHz ÷2 Feedback 100 – 200 MHz ÷4 Feedback 50 – 125 ÷8 Feedback 25 – 62.5 0 – 200 25 – 75 % Bypass mode (PLL_EN = 0) frefDC Input Duty Cycle VPP Peak-Peak Input Voltage LVPECL 500 – 1000 mV VCMR Common Mode Range[8] LVPECL 1.2 – VDD – 0.9 V tr , tf TCLK Input Rise/FallTime 0.8V to 2.0V – – 1.0 ns fMAX Maximum Output Frequency ÷2 Output 100 – 200 MHz ÷4 Output 50 – 125 ÷8 Output 25 – 62.5 DC Output Duty Cycle fMAX < 100 MHz 47.5 – 52.5 fMAX > 100 MHz 45 – 55 % tr , tf Output Rise/Fall times 0.8V to 2.4V 0.1 – 1.0 ns t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD –100 – 100 ps PCLK to FB_IN, same VDD –100 – 100 tsk(O) Output-to-Output Skew Banks at same voltage – – 150 tsk(B) Bank-to-Bank Skew Banks at different voltages – – 350 ps tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time BW PLL Closed Loop Bandwidth (–3dB) tJIT(CC) tJIT(PER) Cycle-to-Cycle Jitter Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time P u ls e G e n e ra to r Z = 50 ohm ps – – 10 ns ÷2 Feedback – 2.2 – MHz ÷4 Feedback – 0.85 – ÷8 Feedback – 0.6 – Same frequency – – 150 Multiple frequencies – – 250 Same frequency – – 100 Multiple frequencies – – 150 I/O same VDD – 175 – ps – – 1 ms Zo = 50 ohm ps ps Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V Zo = 50 ohm D iffe re n tia l P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm R T = 50 ohm VTT VTT Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V Document #: 38-07475 Rev. *A Page 5 of 8 CY29351 PECL_CLK VCMR VPP PECL_CLK VDD FB_IN VDD/2 t(φ) GND Figure 3. LVPECL Propagation Delay t(f), static phase offset VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 4. LVCMOS Propagation Delay t(φ), static phase offset VDD VDD/2 tP GND T0 DC = tP / T0 x 100% Figure 5. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Figure 6. Output-to-Output Skew, tsk(O) Ordering Information Part Number Package Type Product Flow CY29351AI 32-pin TQFP Industrial, –40°C to +85°C CY29351AIT 32-pin TQFP – Tape and Reel Industrial, –40°C to 85°C Document #: 38-07475 Rev. *A Page 6 of 8 CY29351 Package Drawing and Dimension 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07475 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY29351 Document History Page Document Title:CY29351 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer Document Number: 38-07475 Issue Date Orig. of Change 128152 07/07/03 RGL New Data Sheet 245448 See ECN RGL Re-worded Select Function Descriptions in table 2. REV. ECN No. ** *A Document #: 38-07475 Rev. *A Description of Change Page 8 of 8