a AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board EVAL-AD1896EB OVERVIEW INTEGRATED CIRCUIT FUNCTIONS The AD1896 is a 24-bit, high-performance, single-chip, second generation Asynchronous Sample Rate Converter (ASRC). The AD1896 supports sample rates up to 192 kHz with 7.75:1 downsampling and 1:8 upsampling ranges while maintaining the highest performance. In normal operation, input serial data (@ input sample rate fS_IN) in 3-wire serial format is sourced to the serial input port pins SCLK_I, LRCLK_I, and SDATA_I. The output serial data (@ output sample rate fS_out) is accessed via the output serial port pins SCLK_O, LRCLK_O, and SDATA_O. The LRCLK_I and LRCLK_O signals define the input and output sample frequency, respectively. The input and output signals are typically asynchronous with respect to each other and to the master clock, MCLK_I. AD1896 ASRC (U13) Asynchronous Sample Rate Converter The AD1896 has very flexible serial input and output data ports for glueless interconnection to audio DACs, DSPs, Digital Interface Receivers (DIR), and Digital Interface Transmitters (DIT). The AD1896 input and output serial data ports can be configured in left-justified, right-justified (16, 18, 20, and 24 bits), I2S, or TDM mode. Top-level pins are provided for controlling the data formats and other functional modes of the AD1896 without any serial programming. Other features include bypass mode, matched phase mode, group delay selection of the digital filter, mute control, and mute flag pin for an internal error flagging. Please refer to the AD1896 data sheet for the detailed product description. The overall setup of the evaluation board is described briefly including jumper settings. The AD1896 evaluation board uses a ± 9 V to ± 15 V dc source. Clean regulated 5 V and 3.3 V are generated to power the AD1896 and other on-board components. Separate 5 V supplies are used for analog and digital sections. Op amps used for the analog filtering are powered from ± 15 V. Please refer to Appendix A for the block diagram, schematics, layout plots, Bill of Materials, and PLD code. CS8414 SPDIF Receiver (U1) Receives the digital signal from an external source in SPDIF/ AES format and recovers the data and clocks. The 3-wire signals are then sourced to the AD1896 input serial port. SPDIF receiver supports sample rates up to 96 kHz. CS8404 SPDIF Transmitter (U6) Encodes the AD1896 output (3-wire format) in SPDIF format. SPDIF transmitter supports sample rates up to 96 kHz. AD1852 Stereo DAC (U12) Stereo DAC for converting the AD1896 output into stereo analog outputs. Supports up to 192 kHz sample rates unlike SPDIF transmitter. Input CPLD (U2) This PLD is used to control the input serial port signals of the AD1896. In addition, it controls SPDIF receiver and other control signals of the AD1896. Output CPLD (U3) This PLD controls the output serial port signals of the AD1896 as well as the SPDIF transmitter and stereo DAC AD1852. In addition to these components, there is a circuit that divides the master clock of the AD1896 by two or three, based on the master/slave clock mode and generates the on-board signals 256 fS, EXT256 fS, and 128 fS (Figure 9 of the AD1896EB schematic). If the AD1896 output port is operating in 768 × fS master mode, then the master clock is divided by three; and if the AD1896 output port is operating in 512 × fS master mode, then the master clock is divided by two. The 256 fS clock (for DAC) is divided by two to generate the 128 fS master clock for SPDIF transmitter. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 EVAL-AD1896EB • JP2 selects the internal interpolation ratio of the AD1852 stereo DAC (U12). Based on the sample rate, 8×, 4×, or 2× interpolation could be selected. DAC should be configured in 8×, 4×, or 2×… mode for 48 kHz, 96 kHz, or 192 kHz sample rates, respectively. The following section highlights key jumpers and switches on the evaluation board. Please refer to the AD1896 evaluation board schematic for more details. These switches and jumpers configure the AD1896 and other components, such as, SPDIF receiver, transmitter, and stereo DAC. • JP3 enables the autoMUTE feature where the AD1896 MUTE_IN will be asserted if the MUTE_OUT output from AD1896 is set high. The MUTE_OUT is set high when sample rate of LRCLK_I and LRCLK_O changes. SWITCH AND JUMPER FUNCTIONS • S1 is used to switch the mux inside the PLD (U2) between the Digital Interface Receiver (DIR), the CS8414 (U1), and the Direct Digital Input (DDI HDR3) signals. The selected signal is sourced to the input serial port of the AD1896. DIR selection works in conjunction with the Switch S2 as described below. • JP4 jumper selects between an on-board clock oscillator (12.288 MHz) and on-board third order overtone crystal oscillator (33.8688 MHz) for master clock (MCLK_I) of the AD1896. Please refer to Table IX for the maximum allowable sample rates for 76 × fS, 512 × fS, and 256 × fS master mode with 33.8688 MHz master clock. The on-board clock oscillator (12.288 MHz) is enabled only for the SLAVE mode operation of the AD1896 (Switch S4 position 7). • S2 selects between the RCA SPDIF input (J1) and the TOSLINK optical input (U4). The selected signal is sourced to SPDIF receiver and recovered SCLK_I, LRCLK_I, and SDATA_I signals drive the input serial port of the AD1896. • 10-pin header HDR1(TDM_IN) is used to input the TDM_IN data from the SHARC DSP board. • S3 is used to select the different input interface format of the AD1896 input serial data. Total of six input serial modes are possible: LJ, I2S, RJ-24, RJ-20, RJ-18, and RJ-16. Refer to the Digital Audio Input Signals section for the configuration Table IV. Note that the input logic PLD (U2) reads the S3 selection and controls the AD1896 and SPDIF receiver CS8414 accordingly. • 10-pin header HDR2 (TDM_OUT) is used to receive the TDM_OUT data from the AD1896 to SHARC DSP board. • 10-pin header HDR3 (DDI) is used to drive the input serial port signals SCLK_I, LRCLK_I, and SDATA_I in 3-wire format from an external source. • S4 selects the master/slave mode of the input and output serial ports of the AD1896. Refer to Table II for the mode selection settings. In the slave operation, the corresponding SCLK and LRCLK signals are externally provided by the target system. In the master mode, these two signals are internally generated from the MCLK_I signal at 768 × f S, 512 × fS, or 256 × fS rate. In MASTER MODE operation, maximum sample rate for MASTER PORT is limited to 96 kHz. • 10-pin header HDR5 (DDO) is used to drive the output serial port signals SCLK_O, LRCLK_O and SDATA_O in 3-wire format from an external source. LEDS • DS1 (VERF) is illuminated when Validity+Error flag output on SPDIF receiver CS8414 goes high, indicating problems with SPDIF receiver or missing audio signal to the SPDIF receiver. • S5 resets the AD1896 and other components. • DS2 (PREEMP) indicates the pre-emphasized data to the SPDIF receiver. • S6 activates the BYPASS function of the AD1896 where the input serial data is bypassed to the output serial port without any signal processing. • DS3 (3.3 V) is illuminated when 3.3 V dc supply is present to power up the VDD_CORE of the AD1896. • S7 is used to MUTE the AD1896 output serial data as well as the AD1852 stereo DAC. • DS4 (AVDD = 5 V) is illuminated when analog supply to the stereo DAC AD1852 is present. • S8 selects between SHORT or LONG group delay for the AD1896. • DS5 (RIGHT channel) and DS6 (LEFT channel) DAC ZERO STATUS LEDs are illuminated when no input signal is present to the stereo DAC AD1852 (U12). • JP1 jumper is used to select output interface format and word width of the AD1896 output serial data. Refer to the Digital Audio Output Signals section for configuration Tables V and VI. Again, the output logic PLD (U3) decodes the JP1 signals and configures the AD1852 DAC and CS8404 SPDIF transmitter to match the output data format of the AD1896. • DS7 (AUDIO) is illuminated when the SPDIF receiver CS8414 is receiving audio data. SHARC® is a registered trademark of Analog Devices, Inc. –2– REV. 0 EVAL-AD1896EB S8 GRPDLYS 1 28 MMODE_2 MCLK_I 2 27 MMODE_1 MCLK_O 3 26 MMODE_0 JP4 CRYSTAL OSC./EXTERNAL CLK SDATA_I 4 DDI-HDR3, SPDIF-J1, TOSLINK-U4 25 SCLK_O SCLK_I 5 24 LRCLK_O LRCLK_I 6 VDD_IO 7 AD1896 22 VDD_CORE 21 DGND BYPASS 9 20 TDM_IN TDM IN HEADER HDR1 SMODE_IN_0 10 19 SMODE_OUT_0 SMODE_IN_1 11 18 SMODE_OUT_1 SMODE_IN_2 12 17 WLNGTH_OUT_0 S5 RESET 13 16 WLNGTH_OUT_1 S7 MUTE_IN 14 S3 (8-POSITION SWITCH) DDO-HDR5, SPDIF-J2, TDM_OUT-HDR2 23 SDATA_O DGND 8 S6 S4 (8-POSITION SWITCH) JP1 (4-POSITION JUMPER) 15 MUTE_OUT Figure 1. Key Jumpers and Switches on the Evaluation Board Table I. Pinout Table for 10-Pin Header Connectors Pin HDR1 (TDM_IN) HDR2 (TDM_OUT) HDR3 (DDI) HDR5 (DDO) 1 3 5 7 2, 4, 6, 8, 10 5 V (O) TDM_I (I) SCLK_O (I/O) LRCLK_O (I/O) GND 5 V (O) SDATA_O (O) SCLK_O (I/O) LRCLK_O (I/O) GND 5 V (O) SDATA_I (I) LRCLK_I (I/O) SCLK_I (I/O) GND 5 V (O) SDATA_O (O) SCLK_O (I/O) LRCLK_O (I/O) GND input sample rate up to 192 kHz is possible (input port in slave mode) and set by an external source. All input serial data formats and master/slave clock modes are supported. DIGITAL AUDIO INPUT SIGNALS Input serial port of the AD1896 can be driven in various ways using this evaluation board. 1. RCA phone jack (J1) or TOSLINK (U4) optical connector can be used to input the AES/EBU or SPDIF signal to the SPDIF receiver CS8414 (U1). SPDIF receiver generated SCLK_I, LRCLK_I, and SDATA_I signals drive the input serial port of the AD1896. SPDIF input is supported only when the AD1896 serial input port is in SLAVE mode (Switch S4 position 3 to 7) and supports all input serial data formats except RJ-24 bit and RJ-20 bit (Switch S3 positions 2, 3). The SPDIF receiver limits input sample rates to 96 kHz. 2. Alternatively, an external data header (HDR3) can be used to directly source all three signals SCLK_I, LRCLK_I, and SDATA_I from an external source. Unlike SPDIF receiver, SCLK_I and LRCLK_I signals of the input serial port are bidirectional signals. Logic levels on pins MMODE_ [2:0] control the direction of these signals. When the input serial port is in master mode, these signals are generated by the AD1896; whereas, in the slave mode these signals are provided by an external source. MMODE_[2:0] pins are set by the 8-position Switch S4. Tables II and III show the master/slave clock mode corresponding to each switch position. Input data format, such as, I2S, LJ, or RJ is set by the logic levels on SMODE_IN_[2:0] pins as shown in Table IV. Set the 8-position Switch S3 on the evaluation board for the proper input data format. Table II. Input and Output Serial Port Modes S4 Switch Position 7 6 5 4 3 2 1 0 MMODE_[2:0] 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Master/Slave Modes 0 1 0 1 0 1 0 1 Both Serial Ports are in Slave Mode *Output Serial Port is Master with 768 fS_OUT *Output Serial Port is Master with 512 fS_OUT *Output Serial Port is Master with 256 fS_OUT Matched Phase Mode *Input Serial Port is Master with 768 fS_IN *Input Serial Port is Master with 512 fS_IN *Input Serial Port is Master with 256 fS_IN *In MASTER MODE operation, maximum sample rate for Master Port is limited to 96 kHz. REV. 0 –3– EVAL-AD1896EB Table III. Master/Slave Mode Configuration Switch SW4 fS_IN fS_OUT Input Header (HDR3) SCLK_I LRCLK_I Output Header (HDR5) SCLK_O LRCLK_O MCLK_I [MHz] Jumper JP4 Short 0 1 2 3 4 5 6 7 132.3 kHz 66.15 kHz 44.1 kHz Not Used Set Externally Set Externally Set Externally Set Externally Set Externally Set Externally Set Externally Not Used 132.3 kHz 66.15 kHz 44.1 kHz Set Externally Output Output Output Input Input Input Input Input Input Input Input Input Output Output Output Input 33.8688 33.8688 33.8688 33.8688 33.8688 33.8688 33.8688 33.8688 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 Output Output Output Input Input Input Input Input Input Input Input Input Output Output Output Input Table IV. Input Interface Formats S3 Switch Position 0 1 2 3 4 5 6 7 SMODE_IN_[2:0] 2 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 Input Interface Format Left Justified I2S Right Justified, 24 Bits Right Justified, 20 Bits Right Justified, 18 Bits Right Justified, 16 Bits Not Used Not Used control the direction of these signals. Please refer to Table II for the switch position S4 setting to control the Master/Slave mode of the output serial port. The output interface mode, such as I 2 S, LJ, RJ, and TDM mode, is set by the pins SMODE_OUT_[2:0]. Also, the output port has two more pins WLNGTH_OUT_[1:0] to set the output word width to 24, 20, 18, or 16 bits. The logic levels on SMODE_OUT_ [1:0] and WLNGTH_OUT_ [1:0] pins allow different serial output data formats. As shown in Tables V and VI, set the jumpers one and two of JP1 for the word width and three and four of JP1 for the output data format. DIGITAL AUDIO OUTPUT SIGNALS Similar to the input serial port, output serial data (SDATA_O, SCLK_O, and LRCLK_O signals) can be accessed in three different ways using this evaluation board. 1. Refer to Figure 8. Direct digital output header (HDR5) or, alternatively, TDM_OUT header (HDR2) can be used to monitor the output serial data of the AD1896 (SDATA_O signal) in the digital form. HDR5 provides LRCLK_O, SCLK_O, and SDATA_O in 3-wire interface format; whereas, HDR2 should be used in TDM mode to interface the TDM output data to the SHARC DSP board. 2. SPDIF output through connector J2, which is generated by the SPDIF transmitter CS8404. In this case, SCLK_O, LRCLK_O, and SDATA_O from AD1896 are encoded in the SPDIF signal. Similar to the SPDIF receiver, the output sample rates above 96 kHz are not possible due to the transmitter functionality. Note that SPDIF output is supported only for the output port in 768 fS_OUT, 512 fS_OUT, and 256 fS_OUT master mode (Switch S4 positions 4, 5, 6). Table V. Output Interface Formats JP1[4:3] 00 01 10 11 3. RCA jack J6 and J7 provide stereo LEFT and RIGHT analog output signals from AD1852 DAC. Refer to Figure 10. Interpolation ratio of the DAC needs to be set based on the sample rate and set by jumper JP2. DAC analog output is supported only when the AD1896 output port is configured in 768 f S_OUT, 512 fS_OUT, and 256 fS_OUT master mode (Switch S4 positions 4, 5, 6). SCLK_O and LRCLK_O signals of output serial port are bidirectional signals. Logic levels on pins MMODE_ [2:0] –4– SMODE_OUT_[1:0] 1 0 0 0 1 1 0 1 0 1 Interface Format Left-Justified (LJ) I2 S TDM Mode Right-Justified (RJ) Table VI. Output Signal Word Width JP1[2:1] 00 01 10 11 WLNGTH_OUT_[1:0] 1 0 0 0 1 1 0 1 0 1 Word 24 Bits 20 Bits 18 Bits 16 Bits REV. 0 EVAL-AD1896EB DEFAULT CONFIGURATION enabled for SLAVE mode only (Switch S3 position 7). The evaluation board contains 12.288 MHz (U15) clock oscillator. The operating and quiescent currents for the ± 12 V dc supplies are listed below. The default configuration of this evaluation board is highlighted in Tables VII and VIII. The AD1896 is configured in 24-bit input and output data format, with input serial ports in slave mode and output serial port in (768 fS) master mode. In this configuration, input serial port needs to be driven by an external system, such as, Audio Precision, for the slave mode operation. An on-board third overtone crystal oscillator at 33.8688 MHz clocks the AD1896. Since the output serial port is configured in 768 f S master mode and the AD1896 is clocked by 33.8688 MHz clock, the output sample rate will be 44.1 kHz for this configuration. The maximum input sample rate for this case can be up to 192 kHz based on the requirement that the AD1896 master clock must be higher than 138 times the maximum input or output sample rate. The AD1896 can be clocked by secondary on-board clock oscillator (U15) by first inserting the desired clock oscillator in socket U15 and then switching the clock source selection from on-board crystal to clock oscillator (U15) by jumper JP4; however, clock oscillator is +12 V Quiescent Current –12 V Quiescent Current +12 V Normal Operation Current –12 V Normal Operation Current AD1896 AP1 TRANSMITTER SCLK_I SCLK ~250 mA ~5 mA ~300 mA–360 mA ~5 mA AP2 RECEIVER SCLK_O SCLK LRCLK LRCLK_I LRCLK_O LRCLK SDATA SDATA_I SDATA_O SDATA Figure 2. Input and Output Serial Port Direction in Default Configuration Table VII. Default Jumper/Switch Settings DAC Interpolation Ratio Select (JP2) Clock Source (JP4) Group Delay (S8) Bypass Mode (S6) Mute (S7) Position 6 Position 1, 2 Shorted Position 2, 3 Shorted Pushed Up Pushed Down Pushed Down Output Port Master, 768 fS_OUT 48 kHz Sample Rate 33.8688 MHz Crystal Oscillator Short Off Off Input Mode (S3) Output Mode (JP1) Master/Slave Mode (S4) Position 0 Position 1, 2, 3, 4 Shorted LJ-24 Bits LJ-24 Bits Table VIII. Default Evaluation Board Configuration Input Output Master/Slave Mode (S3) Mode (JP1) Mode (S4) LJ X LJ-24 X Both Ports in SLAVE Mode Input Source (HDR3, HDR1, J1, U4) DIRECT INPUT Output Source (HDR2, HDR5, J2) X SPDIF I2 S I2S-24 O_MAS_768 X TDM_IN RJ-24 RJ-24 O_MAS_512 SPDIF RJ-20 RJ-20 O_MAS_256 TOSLINK RJ-18 RJ-18 MATCHED PHASE Group Delay (S8) RJ-16 RJ-16 I_MAS_768 Short X Enable TDM I_MAS_512 Long Disable DIRECT OUTPUT Clock Source (JP4) 96/48 X On-Board X 33.8688 MHz Crystal 192/48 X External 256 fS Clock TDM_OUT Bypass Mode (S6) I_MAS_256 REV. 0 X DAC Interpolation Ratio Select (JP2) –5– Automute Enable (JP3) X Mute (S7) Enable X Enable Disable Disable X EVAL-AD1896EB DEFAULT SETUP AD1852 DAC U12 256fS LEFT OUT MCLK_I SCLK_I fS_IN fS_OUT SET EXTERNALLY 44.1kHz INPUT DATA: DIRECT DIGITAL INPUT HEADER HDR3 (DDI) LRCLK_I RIGHT OUT SDATA_I OUTPUT DATA: DIRECT DIGITAL OUTPUT HEADER HDR5 (DDO) AD1896 U13 SCLK_I SCLK SCLK SCLK_O LRCLK LRCLK_I LRCLK_O LRCLK SDATA SDATA_I SDATA_O SDATA MCLK_I MCLK_O 1 2 3 JUMPER JP4 CS8404 DIT U6 SDATA_I 33.868MHz CRYSTAL LRCLK_I SPDIF OUTPUT SCLK_I 128fS MCLK_I CLOCK DIVIDER 256fS 128fS Figure 3. Default Setup (Refer to Figure 5 for Detailed Setup) TYPICAL PERFORMANCE Typical performance of the AD1896 for 44.1 kHz:48 kHz (asynchronous) sample rate is listed below. 1. 2. 3. 4. DNR, No Filter DNR, A-Weighted THD+N, No Filter Frequency Response –139 dBFS, 20 Hz to 20 kHz (–60 dBFS) –142 dBFS, 20 Hz to 20 kHz (–60 dBFS) –120 dBFS, 20 Hz to 20 kHz (0 dBFS) ± 0.015 dB, 20 Hz to 20 kHz (0 dBFS) Table IX. MCLK_I Frequencies for Common Sample Rates in Master Mode MCLK_I Frequency (MHz) 512 fS 768 fS Sample Rate (kHz) 256 fS 44.100 48.000 96.000 11.289600 12.288000 24.576000 EXTERNAL 192 kHz CLOCK GENERATOR CIRCUIT 22.579200 24.576000 33.868800 ATTACHMENTS Appendix A An external circuit can be used to generate the 192 kHz clock signals (SCLK, LRCLK) using on-board 128 fS clock oscillator (U15) running at 24.576 MHz. Please refer to Figure 4 for the schematic and instructions on how to connect the external circuit to the AD1896EB. In general, external SCLK and LRCLK can be used for converting the audio input data to 192 kHz rate by connecting SCLK to SCLK_O (DDO_SCLK_O, HDR5 on the AD1896EB) and LRCLK to LRCLK_O (DDO_LRCLK_O, HDR5 on the AD1896EB). On-board SPDIF transmitter CS8404 (U6) does not support sample rates above 96 kHz. 1. External 192 kHz Clock Generator Circuit 2. AD1896 Evaluation Board Block Diagram, Schematics, and Layout Plots 3. Bill of Materials 4. PLD Code FURTHER INFORMATION Ordering Information Order number is EVAL-AD1896EB For Application Questions or Technical Support Contact Analog Devices’ Central Applications Department at 1-781-937-1428 for assistance. –6– REV. 0 EVAL-AD1896EB 5V 5V U2 J1 CLR LD ENT BCLK ENP MCLK 24.576MHz LRCLK CLK RCO D0 Q0 D1 Q1 D2 Q2 D3 Q3 BCLK 12.288MHz MCLK HEADER10 DDO DIRECT DIGITAL OUTPUT HEADER 74AC161 U3 NOTES 1. REPLACE U15, 12.288MHz OSCILLATOR WITH 24.576MHz 2. SET S3, I/P IF MODE TO 1 FOR I2S 3. SET S4, MASTER/SLAVE MODE TO 7 4. JUMPER JP4, MCLK_SRCE PINS 1 AND 2 5. JUMPER JP1, O/P I/F MODE POSITIONS 1, 2, AND 4 FOR 24-BIT I2S OUTPUT 6. JUMPER JP2, SELECT POSITION 1 ONLY FOR 192kHz DAC OPERATION 7. SET S1 TO DIR 8. SET S2 TO SELECT COAX OR OPTICAL INPUT CLR LD ENT ENP CLK RCO D0 Q0 D1 Q1 D2 Q2 D3 Q3 LRCLK 192kHz 74AC161 Figure 4. 192 kHz Clock Generator for AD1896EB REV. 0 –7– –8– RESET S5 15V INPUT RESET GENERATOR 3 3 DIR CS8414 REGULATOR MASTER/SLAVE CLOCK MODE (S4) INPUT INTERFACE MODE (S3) (LJ/I2S/RJ) INPUT SIGNAL SOURCE (S1) (DIR/DDI) TOSLINK 256fS 3 3 3V/5V IODVDD 5V DVDD 4 3 I/F MODE DATA RESET 5V AVDD 5V DVDD SWITCH S2 SPDIF IN (J1) DIRECT DIGITAL INPUT (HDR3) TDM INPUT (HDR1) 3 OSCILLATOR 5V DVDD TDM_IN VERF PRE-EMPHASIS AUDIO MODE 768fS 512fS 3.3V DVDD 2 MUTE (S7) ASRC AD1896 3/5 IODVDD 2, 3 PROG DVDR 256fS 3 RESET Y1 33MHz (3rd OT) I/F MODE DATA SPDIF STATUS INPUT INTERFACE PLD MACH 4 5V DVDD BYPASS (S6) NOT USED (S8) 2 3 256fS 256fS RESET MUTE DATA (DDIO) (DAC) ZEROL AD1852 DAC 5V AVDD 2 2 128fS SPDIF OUT (J2) ZEROR DAC RIGHT (J7) DAC LEFT (J6) OUTPUT WORDLENGTH (JP1) (16/18/20/24 BITS) OUTPUT INTERFACE MODE (JP1) (LJ/I2S/TDM/RJ) RESET DIRECT DIGITAL OUTPUT (HDR5) TDM OUTPUT (HDR2) NOTES DIGITAL DATA INTERFACE SIGNALS 1. /2 SCLK_0, LRCLK_0 2. /3 BCLK, LRCLK, SDATA 3. /4 MCLK, BCLK, LRCLK, SDATA 3 3 5V DVDD DIT CS8404A DATA 256fS 3 I/F MODE 3 DATA 5V DVDD 2 MODE OUTPUT INTERFACE PLD MACH 4 (DIT) 256fS 128fS RESET 3 M/S MODE I/F MODE 4 DATA 5V DVDD 3 EVAL-AD1896EB Figure 5. Evaluation Board Block Diagram REV. 0 EVAL-AD1896EB SAMPLE RATE CONVERTER 96-040C.SCH INPUT INTERFACE 96-020C.SCH TDO-2 RESET EXT256fS TDM-IN SCLK-O LRCLK-O SCLK-I LRCLK-I TDM-I SDATA-I SCLK-I LRCLK-I RESET IMODE0 IMODE1 IMODE2 WDLEN0 WDLEN1 OMODE0 OMODE1 CMODE0 CMODE1 CMODE2 SCLK-O LRCLK-O DIV2/DIV3 OSC-EN SLVCLK0 SLVCLK1 TDI-2 TCK TMS DEEMP SDATA-I CMODE0 CMODE1 CMODE2 IMODE0 IMODE1 IMODE2 OUTPUT INTERFACE 96-030C.SCH 128fS TDI-2 TCK TMS CMODE2 CMODE1 CMODE0 SCLK-O LRCLK-O SDATA-O TDO-2 RESET SDATA LRCLK BCLK EXT256fS SLVCLK0 SLVCLK1 OSC-EN DIV2/DIV3 IDPM0 IDPM1 OMODE0 OMODE1 WDLEN0 WDLEN1 SDATA-O MUTE 128fS EXT256fS 256fS MONITOR DAC 96-050C.SCH IDPM0 IDPM1 SDATA LRCLK BCLK MCLK DEEMP MUTE RESET POWER SUPPLIES AND POWER CONNECTIONS 96-060C.SCH UNLESS OTHERWISE NOTED 1.0 1.1 1.2 1.3 ALL RESISTOR VALUES ARE EXPRESSED IN OHMS. ALL RESISTORS ARE 1%, 1/10 W, THICK FILM TYPES. ALL MF RESISTORS ARE 0.1%, 1/10 W, METAL FILM TYPES. R, K, AND M ARE USED INSTEAD OF A DECIMAL POINT IN RESISTOR VALUES. 2. ALL RESISTOR NETWORKS ARE 5%, 1/16 W TYPES WITH THEIR VALUES EXPRESSED IN OHMS. 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 ALL CAPACITOR VALUES ARE EXPRESSED IN FARADS. U, N, AND P ARE USED INSTEAD OF A DECIMAL POINT IN CAPACITOR VALUES. ALL 100N BYPASS CAPACITORS ARE 20%, 50 V, Z5U, CERAMIC MONOLITHIC TYPES. ALL NON-ELECTROLYTIC CAPACITORS ARE 10%, 50 V, X7R, CERAMIC MONOLITHIC TYPES. ALL NP0 CAPACITORS ARE 5%, 50 V, CERAMIC MONOLITHIC TYPES. ALL MY CAPACITORS ARE 5%, 50 V, METALLIZED POLYESTER TYPES. ALL PPS CAPACITORS ARE 5%, 50 V, METALLIZED PPS FILM TYPES. ALL PC CAPACITORS ARE 5%, 50 V, METALLIZED POLYCARBONATE TYPES. ALL ELECTROLYTIC CAPACITORS ARE 20%, 10 V (OR HIGHER), ALUMINUM ELECTROLYTE TYPES. ALL TA CAPACITORS ARE 20%, 10 V (OR HIGHER), TANTALUM ELECTROLYTE TYPES. 4. FOR COMPLETE INFORMATION ON ANY COMPONENT, PLEASE SEE THE ASSOCIATED BILL OF MATERIALS. 5. ALL NET NAMES PRECEDED BY/ARE ACTIVE LOW SIGNALS. Figure 6. Evaluation Board REV. 0 –9– TDM I/O HDR1 –10– R7 75 C63 47pF C62 47pF R8 3.4k R43 100 C66 47pF C65 47pF C67 47pF R44 100 HDR 5 2 R42 100 EXT256fS DDI-BCLK DDI-LRCLK DDI-SDATA C64 47pF R41 100 3 6 6 3 DPDT 5 2 C28 68nF DDI M3 M2 M1 M0 R9 475 DVDD PREEMP AUDIO VERF R1 10k DVDD C1 10nF C1 10nF SPDIF / DDI INPUT SELECT S1 1 4 2 5 DPDT OPTICAL / COAX INPUT SELECT S2 4 1 C9 100nF R40 100 R39 100 DVDD DIRECT DIGITAL INPUT (DDI) HDR3 CONSUMER SPDIF INPUT J1 RCA TORX173 SHIELD SHIELD GND GND OUT VCC SPDIF OPTICAL INPUT U4 600Z FB3 HDR 4 2 VCC DVDD LRCLK-O SCLK-O TDM-I 6 U1A CE/F2 CD/F1 CC/F0 CB/E2 CA/E1 CO/E0 VERF CBL ERF U C MCK SCK FSYNC SDATA 74HC04 U5D 9 CS8414 CS12/FCK M3 M2 M1 M0 RXN RXP FILT SEL 74HC04 U5C 5 74HC04 U5B 3 74HC04 8 4 2 PREEMP AUDIO VERF R11 392 R38 392 392 DEEMP RED PREAMP DS2 RED AUDIO DS7 RED VERF CS8414 SIGNAL STATUS DVDD DS1 R10 U5A 1 M3 M2 M1 M0 DIR-SCK DIR-FSYNC DIR-SDATA TST2 C10 100nF TCK I/O14 I/O13 I/O12 4 OCTAL C TST1 M4A5-64/32 I/O15 I/O11 I/O16 I/O9 I/O10 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK1/I1 I/O27 I/O28 CLK0/I0 I/O29 TCK I/O30 TMS I/O31 TDI DVDD TDO U2A TCK TMS TDO-2 TDI-2 HDR 5 2 AD1895 INPUT MODE SELECT S3 1 0 2 6 2 4 TDO-2 TDI TMS ISP PORT HDR4 DDI-BCLK DDI-LRCLK DDI-SDATA OCTAL 4 C MASTER / SLAVE CLOCK RATIO SELECT S4 1 0 2 6 2 4 IMODE2 IMODE1 IMODE0 SDATA-I LRCLK-I SCLK-I RESET CMODE2 CMODE1 CMODE0 EVAL-AD1896EB Figure 7. Evaluation Board REV. 0 REV. 0 –11– Figure 8. Evaluation Board I/O13 I/O11 I/O12 WDLEN1 M4A5-64/32 I/O14 I/O10 WDLEN0 I/O15 I/O16 I/O17 I/O18 I/O19 I/O9 I/O21 I/O4 CMODE0 OMODE1 I/O22 I/O3 CMODE1 I/O8 I/O23 I/O2 CMODE2 I/O7 I/O24 I/O1 IDPM1 SDATA-O I/O25 I/O0 IDPM0 OMODE0 I/O26 CLK1/I1 I/O20 I/O27 CLK0/I0 I/O5 I/O28 TCK TCK I/O6 I/O29 TMS TMS LRCLK-O I/O30 TDI TDI-2 SCLK-O I/O31 TDO TDO-2 U3A TST9 SLVCLK0 SLVCLK1 DIV2/DIV3 OSC-EN HDR 4 2 OUTPUT MODE SELECT JP1 WDLNGTH-0 WDLNGTH-1 OPMODE-0 OPMODE-1 BCLK LRCLK SDATA SPST RESET S5 DVDD 128fS EXT256fS HDR 4X2 TDM OUTPUT HDR2 1 3 VCC C14 100nF CS8404 U8 TXN TXP ADM811TART 2 4 DVDD CBL/SBC GND RESET MR RST TRNPT/FC1 C1/FC0 C6/C2 C7/C3 EM1/C8 EM0/C9 C9/C15 PRO C/SBF U V M2 M1 M0 MCK SCK FSYNC SDATA U6A HDR 5 2 DVDD DIRECT DIGITAL OUTPUT (DDO) HDR5 DVDD R16 332 RESET R17 90.0 T1 8 6 5 SC937-02 4 2 1 SPDIF OUT J2 RCA EVAL-AD1896EB SPDT 3 3 SPDT 2 1 BYPASS S6 2 1 NOT USED S8 R5 10k SPDT MUTE BYPASS R6 10k –12– HDR 3 1 1 2 3 MCLK SOURCE JP4 3 2 1 MUTE S7 R4 10k DVDD 2 CMODE2 CMODE2 1 DVDD 10 JP3 2 4 1 VDD U15 OSC8 GND OUT EN HDR 2 1 MUTE ENABLE OSC-EN R37 10k 1 74AHC02 9 8 U14C MUTE-O MUTE-I U14A MCLK-O 5 8 DVDD C59 100nF MUTE C57 1nF NP0 L1 1.8H 2 3 U16B 4 SD Q Q 6 5 2Y 74HC153 A 2G 2C3 2C2 2C1 2C0 1G 1C3 1C2 1C1 1Y U19A 1C0 B MCLK/3 MCLK/2 MCLK 1 74AHC74 CD CLK D U17A SLVCLK0 3 2 4 DVDD SLVCLK1 C55 22pF NP0 74AHCT04 R46 10k DVDD C56 15pF NP0 U16A 74AHCT04 1 33M8688Hz Y1 SCLK-O LRCLK-O LRCLK-O AD1896 SDATA-O SCLK-0 R36 47.5 TST6 TST7 TST8 SDATA-O MCLK-I RESET BYPASS 74AHC02 3 CMODE1 CMODE1 RESET CMODE0 CMODE0 NC OMODE0 OMODE1 WDLEN1 WDLEN1 OMODE0 WDLEN0 WDLEN0 OMODE1 IMODE1 IMODE2 IMODE1 IMODE2 TDM-I IMODE0 TDM-I LRCLK-I LRCLK-I IMODE0 SDATA-I SCLK-I SCLK-I U13A SDATA-I TST3 TST4 TST5 U16C 10 13 12 U16F 74AHCT04 13 Q 8 9 8 74AHCT04 9 SPARE U16D R45 22.1 74AHC74 CD CLK Q U18B SD 10 DVDD 74AHCT04 11 6 74AHCT04 5 D 8 9 CD Q 13 74AHC74 Q U17B SD 10 CLK D U16E 11 12 DVDD 11 12 DIV2/DIV3 3 2 4 Q 6 5 EXT256fS 256fS 128fS 1 74AHC74 CD Q U18A SD CLK D 5 U14B U14D 74AHC02 12 11 74AHC02 6 13 4 EVAL-AD1896EB Figure 9. Evaluation Board REV. 0 REV. 0 FIgure 10. Evaluation Board –13– RESET DEEMP MUTE CLATCH CCLK CDATA 24 PD/RST 9 DEEMP 23 MUTE 3 4 5 27 SDATA 25 26 L/RCLK BCLK 2 MCLK SDATA LRCLK BCLK 256FS U12A AD1852 21 IDPM0 20 IDPM1 10 7 6 96/48 192/48 NC 2 4 HDR 2 2 1 3 SELECT JP2 R3 10k IDPM0 IDPM1 R2 10k DVDD U5E 12 10 13 12 16 17 C25 100nF FILTB FILTR 19 14 22 ZEROL 8 ZEROR OUTR– OUTR+ OUTL– OUTL+ 74HC04 13 U5F 74HC04 11 + C38 15F TA C26 100nF DS6 RED ZERO LEFT R15 392 DDD + C39 15F TA R14 392 DS5 RED ZERO RIGHT C27 100nF R23 2.8k R22 2.8k R21 2.8k R20 2.8k R25 3.01k R29 1.5k C46 1nF NP0 C45 1nF NP0 R27 3.01k R30 1.5k R31 1.5k R26 3.01k C44 1nF NP0 C43 1nF NP0 R28 1.5k R24 3.01k OP275 U11B OP275 U11A C49 270pF NP0 3 2 C50 270pF NP0 C48 270pF NP0 5 6 C47 270pF NP0 1 7 R33 549 R32 549 C52 2.2nF PPS C51 2.2nF PPS R35 53.6k RIGHT OUTPUT J7 RCA R34 53.6k LEFT OUTPUT J6 RCA EVAL-AD1896EB –14– BINDING POST (BLUE) –15VDC CR2 J5 DL4001 DVDD C11 100nF CR4 1SMB15AT3 TA BINDING POST (GREEN) GND J4 BINDING POST (YELLOW) +15VDC CR1 J3 DL4001 C33 47F TA FB6 600Z FB9 600Z C15 100nF + C36 15F TA 4 5 7 8 GND SD IN IN AVEE 4 5 7 8 GND SD IN IN NR ERR OUT OUT ADP3303-3.3 U9 NR ERR OUT OUT ADP3303-5 U10 3 6 2 1 3 6 2 1 4 C16 100nF C3 OPEN C40 100F + C35 47F TA D3V3 ANALOG GROUND + DS3 RED 3.3V R12 392 DS4 RED 5VA R13 392 + C32 47F TA DVDD C13 100nF AVDD DIGITAL GROUND R19 715 R18 243 C19 100nF C4 OPEN + C37 15F TA 1 ADJ VIN +VOUT U7 LM317MDT C12 100nF 3 + C42 100F + C41 100F AVCC C17 100nF + C20 100nF FB5 600Z FB7 600Z C18 100nF FB8 600Z CR3 1SMB15AT3 + C34 15V 15F TA FB4 600Z C29 100nF C5 100nF DVDD 22 VA+ GND 7 14 VCC C70 100nF C23 100nF OP275 U11C C24 100nF 74AHC02 U14E DVDD AVEE 4 V– V+ AVCC 8 38 VCC GND 7 14 VCC C58 100nF 38 VCC GND 7 C69 100nF 74AHC74 U16C DVDD C22 100nF AVDD FB10 600Z AD1852 U12B 14 VCC C68 100nF 74HC04 U3B 18 AVDD GND 7 14 VCC DVDD C31 GND 7 14 VCC C60 100nF GND 8 7 VDD 74AHC74 U18C DVDD C53 100nF DVDD 100nF GND 18 CS8404 U6B 19 VD+ DVDD D3V3 C54 100nF GND 8 74HC153 U19B 16 VCC C61 100nF AD1896 U13B DVDD GND 21 22 VCORE C8 100nF M4-64/32 U2B DVDD GND GND GND GND 17 6 39 28 16 VCC DVDD DGND AGND AGND 1 11 15 28 DVDD DVDD 74AHCT04 U16G DVDD C21 100nF C30 100nF C7 100nF M4-64/32 U3B DVDD DGND 8 CS8414 U1B 7 VD+ C6 100nF DVDD FB2 600Z GND GND GND GND 17 6 39 28 16 VCC DVDD AGND 21 FB1 600Z EVAL-AD1896EB Figure 11. Evaluation Board REV. 0 EVAL-AD1896EB Figure 12. Audio ASRC Figure 13. Component Side REV. 0 –15– EVAL-AD1896EB Figure 14. Ground Planes Figure 15. Power Planes –16– REV. 0 EVAL-AD1896EB Figure 16. Bottom Layer REV. 0 –17– EVAL-AD1896EB BILL OF MATERIALS Item Qty Ref Detail Title Mfr P/N Mfr Name LH99321 Rev 0 AD1852JRS AD1895YRS ADM811TART ADP3303AR-3.3 ADP3303AR-5 CS8404A-CS CS8414-CS LM317MDT M4A5-64/32-10VC OP275GS 74AHC02 74AHC74 74AHCT04 74HC14 74HC153 SC937-02 22R1 Ω 47R5 Ω 75R0 Ω 90R9 Ω 100 Ω 243 Ω 332 Ω 392 Ω PCB FAB AD1895 Evaluation IC DAC Stereo 24-Bit 192kS/s SSOP-28 IC Async Sample Rate Converter SSOP-28 IC Reset Generator SOT-143 Voltage Regulator 3 V 3 SO-8 Voltage Regulator 5 V SO-8 IC Digital Audio Transmitter 96 kHz SOIC-24L IC Digital Audio Receiver 96 kHz SOIC-28L Voltage Regulator Pos Adj DPAK IC PLD CMOS ISP TQFP44 IC OPAMP Dual Bipolar/JFET SO-8 IC Quad 2-Input NOR SO-14 IC Dual D Flip-Flop SO-14 IC Hex Inverter SO-14 IC Hex Schmitt Trigger Inverter SO-14 IC Dual 4-Input MUX SO-14 Transformer Signal AES/EBU Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 LH99321 Rev 0 AD1852JRS AD1895YRS ADM811TART ADP3303AR-3.3 ADP3303AR-5 CS8404A-CS CS8414-CS LM317MDT M4A5-64/32-10VC OP275GS 74AHC02D SN74AHC74D SN74AHCT04D MM74HC14M M74HC153M SC937-02 ERJ-6ENF22.1 ERJ-6ENF47.5 ERJ-6ENF75.0 ERJ-6ENF90R9 ERJ-6ENF1000 ERJ-6ENF2430 ERJ-6ENF3320 ERJ-6ENF3920 Prototype Circuits, Inc. Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Crystal Semiconductor Crystal Semiconductor Motorola Lattice Analog Devices, Inc. Philips Texas Instruments Texas Instruments Fairchild ST Microelectronics Scientific Conversion, Inc. Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic 475 Ω 549 Ω 715 Ω 1.5 kΩ 2.8 kΩ 3.01 kΩ 3.4 kΩ 10 kΩ Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 Chip Resistor 1% 100 mW Thick Film 0805 ERJ-6ENF4750 ERJ-6ENF5490 ERJ-6ENF7150 ERJ-6ENF1501 ERJ-6ENF2801 ERJ-6ENF3011 ERJ-6ENF3401 ERJ-6ENF1002 Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic 53.6 kΩ 15 pF 22 pF 47 pF 270 pF 1 nF Chip Resistor 1% 100 mW Thick Film 0805 Chip Capacitor 5% 50 V NP0 Ceramic 0805 Chip Capacitor 5% 50 V NP0 Ceramic 0805 Chip Capacitor 5% 50 V NP0 Ceramic 0805 Chip Capacitor 5% 50 V NP0 Ceramic 0805 Chip Capacitor 5% 50 V NP0 Ceramic 0805 ERJ-6ENF5362 ECU-V1H150JCN ECU-V1H220JCN ECU-V1H470JCG ECU-V1H271JCG ECU-V1H102JCX Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic 2.2 nF 10 nF 68 nF 100 nF Chip Capacitor 5% 50 V PPS Film 0805 Chip Capacitor 10% 50 V X7R Ceramic 0805 Chip Capacitor 10% 50 V X7R Ceramic 0805 Chip Capacitor 10% 50 V X7R Ceramic 0805 ECH-U1H222JB5 ECU-V1H103KBG ECJ-2YB1H683K ECJ-2YB1H104K Panasonic Panasonic Panasonic Panasonic 15 µF Chip Capacitor 20% 20 V Tantalum 7343 ECS-T1DD156R Panasonic 47 µF Chip Capacitor 20% 10 V Tantalum 7343 ECS-T1AD476R Panasonic 100 µF 33M8688 Hz SMD Capacitor 20% 25 V Aluminum CASE-F SMD Crystal HCM49 Panasonic Citizen FB1–FB10 L1 DS1–DS7 600Z 1.8 µs Red Chip Ferrite Bead 600 Ω @100 MHz 0805 Chip Inductor 20% 0R82 Ω RLP167 Chip LED 1206LED EEV-FC1E101P HCM49-33.8688 MABJT HZ0805E601R ELJ-FA1R8KF CMD15-21VRD/TR8 2 2 2 CR1, CR2 CR3, CR4 J1, J2 DL4001 1SMB15AT3 Black Insert Chip Diode 50 V 1A SOD-87 Chip Transient Suppressor 15 V 600 W SMB Connector RCA Female Right Angle CTP-021 DL4001 1SMB15AT3 CTP-021-A-S-BLK 54 1 J6 White Insert Connector RCA Female Right Angle CTP-021 CTP-021-A-S-WHT 55 1 J7 Red Insert Connector RCA Female Right Angle CTP-021 CTP-021-A-S-RED 56 57 58 1 1 1 JP3 JP2 JP4 Header 2 1 Header 2 2 Header 3 1 Connector 2P 2 1 Male 100ctr SIP2 Connector 4P 2 2 Male 100ctr HDR2X2 Connector 3P 3 1 Male 100ctr HDR3X1 2340-6111TN 2380-6121TN 2340-6111TN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 1 1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 1 1 1 1 6 1 1 7 26 27 28 29 30 31 32 33 1 2 1 4 4 4 1 8 34 35 36 37 38 39 2 1 1 6 4 5 40 41 42 43 2 2 1 35 44 5 45 3 46 47 3 1 U12 U13 U8 U9 U10 U6 U1 U7 U2, U3 U11 U14 U17, U18 U16 U5 U19 T1 R45 R36 R7 R17 R39–R44 R18 R16 R10–R15, R38 R9 R32, R33 R19 R28–R31 R20–R23 R24–R27 R8 R1–R6, R37, R46 R34, R35 C56 C55 C62–C67 C47–C50 C43–C46, C57 C51, C52 C1, C2 C28 C5–C27, C29–C31, C53, C54, C58–C61, C68–C70 C34, C36– C39 C32, C33, C35 C40–C42 Y1 48 49 50 10 1 7 51 52 53 –18– Steward Panasonic Chicago Miniature Lamp, Inc. Microsemi ON Semiconductor Connect-Tech Products, Products, Inc. Connect-Tech Products, Products, Inc. Connect-Tech Products, Products, Inc. 3M 3M 3M REV. 0 EVAL-AD1896EB BILL OF MATERIALS (continued) Item Qty Ref Detail Title Mfr P/N Mfr Name 59 3 Header 4 2 Connector 8P 4 2 Male 100ctr HDR4X2 2380-6121TN 3M 60 2 Header 5 2 Connector 10P 5 2 Male 100ctr HDR5X2 2380-6121TN 3M 61 1 HDR1, HDR2, JP1 HDR3, HDR5 HDR4 Header 5 2 1 1 2 2 1 3 1 1 1 1 4 51138-44624 30310-6002HB 1108800 SG-531P-12.288MC EG-2215 PT65526 FSM6JSMA 10SP001 TORX173 111-0107-001 111-0104-001 111-0110-001 SPCS-12 3M 62 63 64 65 66 67 68 69 70 71 72 Connector 10P 5 2 Male 100ctr Shrouded HDR5X2SHR Socket Oscillator Half Size OSC8 IC CMOS Oscillator 12.288 MHz OSC8 Switch Slide DPDT Side Act PCB Switch Rotary 8 Pos Octal Switch PB NO Momentary Tactile Switch Slide SPDT Vert Act PCB IC Fiber Optic Receiver Connector Binding Post Connector Binding Post Connector Binding Post Spacer Nylon 3/4" Snap-In REV. 0 U15 U15 S1, S2 S3, S4 S5 S6–S8 U4 J3 J4 J5 Socket 4/8 12M288 Hz EG-2215 PT65526 FSM6JSMA 10SP001 TORX173 Yellow Green Blue Spacer Snap-in –19– Aries Epson Electronics E-Switch APEM Augat Mouser Toshiba Johnson Components, Inc. Johnson Components, Inc. Johnson Components, Inc. SPC Technology EVAL-AD1896EB in_pld.abl MODULE IF_Logic TITLE 'AD1896 EVB Input Interface Logic' //=================================================================================== // FILE: input_pld.abl // REVISION DATE: 03-20-01 // REVISION BY: Chirag Patel // REVISION: 1.0 // // DESCRIPTION: // // This input interface PLD (U2) selects between the External Data Interface header // (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending // upon the SPDIF/DDI switch position (S1). When the SPDIF Receiver DIR is the selected // signal source the digital audio signals, SDATA_I, SCLK_I and LRCLK_I are derived from // the DIR output. SPDIF receiver needs the digital data in the SPDIF format in order to // generate these signals. When the external data is the selected source the digital // signals from (HDR3) are applied to the AD1896. // // // // // // Signals SCLK_I, LRCLK_I, DDI_SCLK, DDI_LRCLK, DIR_SCLK, DIR_FSYNC on the PLD are bi-directional signals. The direction of these signals are controlled by the MASTER_SLAVE MODE switch position (S4). When the AD1896 input serial port is set in the master mode, the SCLK_I and LRCLK_I are generated from the AD1896 input serial port. On the other hand, these signals are provided from the external source in the slave mode operation. // PLD also decodes the Input Interface Format Switch (S3) and sets the Interface mode pins // for both the CS8414 DIR and the AD1896 ASRC. //=================================================================================== LIBRARY 'MACH'; DECLARATIONS // IF_Logic DEVICE 'M4-64/32-15VC'; "INPUTS =========================================================================== // TDI, TCK, TMS pin 4,7,26 istype 'com'; //JTAG I/P's DIR_SDATA pin 1 istype 'com'; //CS8414 DIR SDATA OUT SPDIF_DDI pin 12 istype 'com'; //SPDIF_DDI SWITCH S1 DDI_SDATA pin 22 istype 'com'; //EXTERNAL DATA INPUT DDI RESET Pin 23 istype 'com'; //Active hi reset output to AD1896 RESET_LO Pin 44 istype 'com'; //Active low reset input MS_MODE2, MS_MODE1, MS_MODE0 pin 24,25,30 istype 'com'; //MASTER/SLAVE MODE SWITCH S4 IN_MODE2,IN_MODE1,IN_MODE0 pin 18,15,14 istype 'com'; //INPUT SERIAL MODE SWITCH S3 "OUTPUTS ========================================================================= // TDO pin 29 istype 'com'; //JTAG O/P M0, M1, M2, M3 pin 8,9,10,11 istype 'com'; //SPDIF_RVR MODE SELECT SMODE_I_0, SMODE_I_1, SMODE_I_2 pin 33,32,31 istype 'com'; //INPUT SERIAL MODE FORMAT FOR AD1896 SDATA_I pin 37 istype 'com'; //SERIAL DATA INPUT TO AD1896 ASRC //IO SIGNALS DIR_FSYNC, DIR_SCLK IO'S DDI_LRCLK, DDI_SCLK SCLK IO'S FOR HDR3 LRCLK_I, SCLK_I AD1896 ASRC pin 2,3; //DIR_FYSNC AND DIR_SCLK pin 21,20; //EXTERNAL LRCLK AND pin 35,36; //LRCLK_I AND SCLK_I IO'S TO "NODES –20– REV. 0 EVAL-AD1896EB I_SDATA, ISCLK, ILRCLK node istype 'com'; //================================================================================ in_pld.abl "MACROS //INPUT SERIAL DATA FORMATS // S3 position 0, LEFT-JUSTIFIED LJ = ( IN_MODE2 & IN_MODE1 & IN_MODE0); // S3 position 1, I2S I2S = ( IN_MODE2 & IN_MODE1 & !IN_MODE0); // S3 position 2, RIGHT-JUSTIFIED 24-BITS RJ24 = ( IN_MODE2 & !IN_MODE1 & IN_MODE0); // S3 position 3, RIGHT-JUSTIFIED 20-BITS RJ20 = ( IN_MODE2 & !IN_MODE1 & !IN_MODE0); // S3 position 4, RIGHT-JUSTIFIED 18-BITS RJ18 = ( !IN_MODE2 & IN_MODE1 & IN_MODE0); // S3 position 5, RIGHT-JUSTIFIED 16-BITS RJ16 = ( !IN_MODE2 & IN_MODE1 & !IN_MODE0); // S3 positons 6,7 are not used //MASTER_SLAVE MODE MAPPING // S4 position BOTH_SLAVE // S4 position O_MAS_768 // S4 position O_MAS_512 // S4 position O_MAS_256 // S4 position MATCH_PHASE // S4 position IN_MAS_768 // S4 position IN_MAS_512 // S4 position IN_MAS_256 7, = 6, = 5, = 4, = 3, = 2, = 1, = 0, = INPUT/OUTPUT SERIAL PORTS IN SLAVE MODE (!MS_MODE2 & !MS_MODE1 & !MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX768 (!MS_MODE2 & !MS_MODE1 & MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX512 (!MS_MODE2 & MS_MODE1 & !MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX256 (!MS_MODE2 & MS_MODE1 & MS_MODE0); INPUT SERIAL PORT IN MATCHED_PHASE MODE (MS_MODE2 & !MS_MODE1 & !MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX768 (MS_MODE2 & !MS_MODE1 & MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX512 (MS_MODE2 & MS_MODE1 & !MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX256 (MS_MODE2 & MS_MODE1 & MS_MODE0); "========================================================================== EQUATIONS // AD1896 ASRC Input SMODE_I_2 = RJ24 SMODE_I_1 = RJ24 SMODE_I_0 = RJ24 Serial Port Interface Mode Select # RJ20 # RJ18 # RJ16; # RJ20; # RJ18 # I2S; // CS8414 DIR Interface Mode Select, DIR_FSYNC and DIR_SCLK are bi-directional signals. // If AD1896 input serial port is in slave mode, the CS8414 DIR RJ-24 and RJ-20 modes // are not supported. M0 = (RJ16 & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((LJ # RJ24 # RJ20 # I2S) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M1 = ((I2S # RJ18) & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256)) # (I2S & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M2 = RJ18 # RJ16; M3 = 0; REV. 0 –21– EVAL-AD1896EB in_pld.abl // IO control logic DDI_SCLK.oe = DDI_LRCLK.oe = DIR_FSYNC.oe = DIR_SCLK.oe = SCLK_I.oe = LRCLK_I.oe = DDI_SCLK DDI_LRCLK DIR_SCLK DIR_FSYNC = = = = (IN_MAS_768 (IN_MAS_768 (IN_MAS_768 (IN_MAS_768 (BOTH_SLAVE (BOTH_SLAVE # # # # # # IN_MAS_512 # IN_MAS_256); IN_MAS_512 # IN_MAS_256); IN_MAS_512 # IN_MAS_256); IN_MAS_512 # IN_MAS_256); MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); ISCLK; ILRCLK; ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S); ILRCLK; // AD1896 ASRC Input Serial port signals SCLK_I = ((LJ # RJ24 # RJ20 # RJ18 # RJ16 # I2S) & (ISCLK) & (!SPDIF_DDI)) # ((((LJ # RJ24 # RJ20) & (!ISCLK)) # ((I2S # RJ18 # RJ16) & (ISCLK))) & (SPDIF_DDI)); LRCLK_I (!SPDIF_DDI)); SDATA_I (SPDIF_DDI)); = (SPDIF_DDI & DIR_FSYNC) # (((I2S & !DDI_LRCLK) # (!I2S & DDI_LRCLK)) & = (DDI_SDATA & !SPDIF_DDI) # (((LJ#RJ24#RJ20#RJ18#RJ16#I2S)&(DIR_SDATA)) & // Internal node signals ISCLK = ((DDI_SCLK) & (BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (!SPDIF_DDI)) # ((LJ#RJ24#RJ20) & ((DIR_SCLK) & (BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI))) # ((SCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)) # ((I2S # RJ18 # RJ16) & (DIR_SCLK) & (BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI)); ILRCLK = ((DDI_LRCLK) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (!SPDIF_DDI)) # ((DIR_FSYNC) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI)) # ((LRCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); I_SDATA = (DDI_SDATA & !SPDIF_DDI) # (DIR_SDATA & SPDIF_DDI); "==================================================================================== END IF_Logic –22– REV. 0 EVAL-AD1896EB out_pld.abl //=================================================================================== MODULE IF_Logic TITLE 'AD1896 EVB Output Interface Logic' //=================================================================================== // FILE: output_pld.abl // REVISION DATE: 03-20-01 // REVISION BY: Chirag Patel // REVISION: 1.0 // DESCRIPTION: // This output interface PLD (U3) decodes output interface signals of AD1896 and sources // these signals to the DAC, DIT and external header (HDR2, HDR5). // Signals SCLK_O, LRCLK_O, DDO_SCLK and DDO_LRCLK on the PLD are bi-directional signals. // The direction of these signals are controlled by the MASTER_SLAVE MODE switch position (S4). // When the AD1896 output serial port is set in the master mode, the SCLK_O and LRCLK_O are // generated from the AD1896 output serial port. On the other hand, these signals are provided // from the external source in the slave mode operation. // // PLD also decodes the Output Interface Format and data width Jumper header (JP1) and sets // the Interface mode pins for the AD1896 ASRC, AD1852 DAC and CS8404 DIT to meet the interface // requirements of all three devices in any given mode. //=================================================================================== LIBRARY 'MACH'; DECLARATIONS // IF_Logic DEVICE 'M4-64/32-15VC'; "INPUTS =========================================================================== // TDI, TCK, TMS pin 4, 7, 26 istype 'com'; //JTAG I/P's SDATA_O pin 3 istype 'com, buffer'; MS_MODE2, MS_MODE1, MS_MODE0 pin 42, 43, 44 istype 'com'; WDLNGTH1, WDLNGTH0 pin 19, 18 istype 'com'; OPMODE1, OPMODE0 pin 21, 20 istype 'com'; "OUTPUTS ======================================================================== // TDO pin 29 istype 'com'; //JTAG O/P SMODE_O_1, SMODE_O_0 pin 9, 8 istype 'com'; WDLNGTH_O_1, WDLNGTH_O_0 pin 11, 10 istype 'com'; OSC_EN, SLVCLK1, SLVCLK0, DIV2_3 pin 14,12, 13, 15 istype 'com'; IDPM1, IDPM0 pin 41, 40 istype 'com'; DDO_SDATA pin 34 istype 'com, buffer'; SDATA_DAC_DIT pin 22 istype 'com, buffer'; LRCLK_DAC, SCLK_DAC pin 36, 35 istype 'com, buffer'; FSYNC_DIT, SCLK_DIT pin 23, 24 istype 'com, buffer'; M2,M1,M0 pin 31,32,33 ISTYPE 'com'; TST9 pin 37 istype 'com, buffer'; //IO SIGNALS SCLK_O, LRCLK_O DDO_SCLK, DDO_LRCLK pin 1, 2 istype 'com, buffer'; pin 30, 25 istype 'com, buffer'; "NODES I_SDATA, ISCLK, ILRCLK node istype 'com, buffer'; //================================================================================ out_pld.abl "MACROS REV. 0 –23– EVAL-AD1896EB //OUTPUT SERIAL DATA FORMATS // JP1[4:3] LJ // JP1[4:3] I2S // JP1[4:3] TDM // JP1[4:3] RJ 0, LEFT-JUSTIFIED = (!OPMODE1 & !OPMODE0); 1, I2S = (!OPMODE1 & OPMODE0); 2, TDM MODE = (OPMODE1 & !OPMODE0); 3, RIGHT-JUSTIFIED = (OPMODE1 & OPMODE0); // OUTPUT DATA BIT WIDTH SETTINGS // JP1[2:1] BITS_24 // JP1[2:1] BITS_20 // JP1[2:1] BITS_18 // JP1[2:1] BITS_16 0, 24-BITS = ( !WDLNGTH1 0, 20-BITS = ( !WDLNGTH1 0, 18-BITS = ( WDLNGTH1 0, 16-BITS = ( WDLNGTH1 & !WDLNGTH0); & WDLNGTH0); & !WDLNGTH0); & WDLNGTH0); // OUTPUT SERIAL DATA FORMAT MAPPING // LJ-24 BITS LJ24 = (LJ & // I2S-24 BITS I2S24 = (I2S // TDM-24 BITS TDM24 = (TDM // RJ-24 BITS RJ24 = (RJ & // RJ-20 BITS RJ20 = (RJ & // LJ-18 BITS RJ18 = (RJ & // LJ-16 BITS RJ16 = (RJ & BITS_24); & BITS_24); & BITS_24); BITS_24); BITS_20); BITS_18); BITS_16); //MASTER_SLAVE MODE MAPPING // S4 position BOTH_SLAVE // S4 position O_MAS_768 // S4 position O_MAS_512 // S4 position O_MAS_256 // S4 position MATCH_PHASE // S4 position IN_MAS_768 // S4 position IN_MAS_512 // S4 position IN_MAS_256 7, = 6, = 5, = 4, = 3, = 2, = 1, = 0, BOTH SERIAL PORT IN SLAVE MODE (!MS_MODE2 & !MS_MODE1 & !MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX768 (!MS_MODE2 & !MS_MODE1 & MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX512 (!MS_MODE2 & MS_MODE1 & !MS_MODE0); OUTPUT SERIAL PORT IN MASTER MODE FSX256 (!MS_MODE2 & MS_MODE1 & MS_MODE0); INPUT SERIAL PORT IN MATCHED_PHASE MODE (MS_MODE2 & !MS_MODE1 & !MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX768 (MS_MODE2 & !MS_MODE1 & MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX512 (MS_MODE2 & MS_MODE1 & !MS_MODE0); INPUT SERIAL PORT IN MASTER MODE FSX256 = (MS_MODE2 & MS_MODE1 & MS_MODE0); "==================================================================================== out_pld.abl –24– REV. 0 EVAL-AD1896EB EQUATIONS // AD1896 ASRC WDLNGTH_O_1 WDLNGTH_O_0 SMODE_O_1 SMODE_O_0 Output Serial Port Interface Mode and word length Select = WDLNGTH1; = WDLNGTH0; = OPMODE1; = OPMODE0; // CS8414 DIT Interface Mode Select. The chip is configured in the LJ mode when AD1896 output format are // set either RJ24, RJ20, RJ18 or RJ16. Also need to invert the incoming SCLK signal in the LJ24, RJ24, RJ20, // RJ18 and RJ16 mode to match the DIT interface requirment for DIT_SCLK. M0 = LJ; M1 = 0; M2 = I2S; // AD1852 Stereo DAC input serial Interface mode select. NOTE that the DAC requires serial programing for // RJ20, RJ18, RJ16 mode. Since AD1896 EVB does not allow serial programming of the AD1852 registers, // AD1852 will be configured in RJ24 mode when AD1896 output port is configured in RJ20, RJ18 and RJ16 mode. IDPM1 = LJ; IDPM0 = I2S; // AD1896, DIR, DIT, AD1852 MCLK control logic. Based on the Master/Slave operation of the AD1896 in/out ports, // 33.8688MHz crystal frequency will be divided by either 1, 2 or 3 and the ouput of the divider is feed into the DAC and DIT. // On-board 12.288MHz clock oscillator is enabled only when input and ouput serial ports are configured in SLAVE mode. OSC_EN SLVCLK1 SLVCLK0 DIV2_3 = = = = (BOTH_SLAVE); (O_MAS_768) # (BOTH_SLAVE); (O_MAS_512) # (BOTH_SLAVE); (!O_MAS_512) & (O_MAS_768); // IO control logic for bi-directional signals DDO_SCLK.OE DDO_LRCLK.OE SCLK_O.OE LRCLK_O.OE = = = = (O_MAS_768 # O_MAS_512 # O_MAS_256); (O_MAS_768 # O_MAS_512 # O_MAS_256); (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256); (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256); // AD1896 ASRC Output Serial port signals DDO_SDATA = SDATA_O; DDO_SCLK = ISCLK; DDO_LRCLK = ILRCLK; SCLK_O LRCLK_O = ISCLK; = ILRCLK; // DAC AND DIT SIGNALS SDATA_DAC_DIT = SDATA_O; LRCLK_DAC = ILRCLK; REV. 0 –25– EVAL-AD1896EB SCLK_DAC = ISCLK; FSYNC_DIT SCLK_DIT = ILRCLK; = ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S); // Internal node signals out_pld.abl ISCLK = ((SCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_SCLK) & (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); ILRCLK = ((LRCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (LJ # TDM # RJ24 # RJ20 # RJ18 # RJ16)) # ((!DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (I2S)); "==================================================================================== END IF_Logic –26– REV. 0 –27– –28– PRINTED IN U.S.A. C02625–0–12/01(0)