IRF IRF3546MTRPBF

 60A Dual Integrated Power Block IRF3546
The IRF3546 dual integrated Power Block copackages two pairs of high performance control and
synchronous MOSFETs and is ideal for use in highdensity two-phase synchronous buck converters. It is
optimized internally for PCB layout, heat transfer and
package inductance. Coupled with the latest
generation of IR MOSFET technology, the IRF3546
provides higher efficiency at low output voltages
required by cutting edge CPU, GPU and DDR
memory designs.
FEATURES
• Peak efficiency up to 94% at 1.2V
• Two pairs of control and synchronous
MOSFETs in a single PQFN package
• Proprietary package minimizes package
parasitic and simplifies PCB layout
• Input voltage (VIN) range of 4.5V to 21V
• Output current capability of 30A/phase
• Ultra-low Rg MOSFET technology minimizes
switching losses for optimized high frequency
performance
• Synchronous MOSFET with monolithic
integrated Schottky diode reduces dead-time
and diode reverse recovery losses
• Efficient dual side cooling
• Small 6mm x 8 mm x 0.9mm PQFN package
• Lead-free RoHS compliant package APPLICATIONS
• High frequency, low profile DC-DC converters
• Voltage Regulators for CPUs, GPUs, and DDR
memory arrays
High switching frequency enables high performance
transient response, allowing miniaturization of output
inductors, as well as input and output capacitors while
maintaining industry leading efficiency. Integrating two
phases in one package while still providing superior
efficiency and thermal performance, the IRF3546
enables smallest size solutions.
The IRF3546 uses IR’s latest generation of low
voltage MOSFET technology characterized by ultralow gate resistance (Rg, <0.5Ω) and charge that result
in minimized switching losses. The synchronous
MOSFET optimizes conduction losses and features a
monolithic integrated Schottky to significantly reduce
dead-time and diode conduction and reverse recovery
losses.
The IRF3546 is optimized specifically for CPU core
power delivery in 12V input applications like servers,
certain notebooks, GPU and DDR memory designs.
DESCRIPTION
ORDERING INFORMATION
Base Part Number
Package Type
IRF3546
PQFN 6 mm x 8 mm
1
Standard Pack
Form
Quantity
Tape and Reel
3000
www.irf.com | © 2013 International Rectifier
Orderable Part Number
IRF3546MTRPBF
May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
PINOUT DIAGRAM
Figure 1: IRF3546 Top View
FUNCTIONAL BLOCK DIAGRAM
VIN1 VIN1 VIN1 GATEH1
1
40
SW1 29
41
GATEH2 VIN2 VIN2 VIN2
15
9
7
Q1
SW1 30
16
17
21 SW2
Q3
22 SW2
SW1 31
23 SW2
SW1 32
24 SW2
SW1 33
25 SW2
IRF3546
SW1 34
SW1 35
26 SW2
27 SW2
Q4
Q2
SW1 36
28 SW2
38
39
37
8
42
18
PGND PGND GATEL1 PGND PGND GATEL2
19
20
PGND PGND
Figure 2: Block Diagram
2
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May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block TYPICAL APPLICATION
IRF3546
VIN1
1, 40, 41
C2
0.1uF
Q1
GATEH1
7
Q2
C1
10uF x2
L1
150nH
SW1
29‐36
VOUT1
C3
22uF x5
GATEL1
37
PGND
38, 39
PGND
8, 42
VIN2
15‐17
C5
0.1uF
Q3
GATEH2
9
Q4
GATEL2
18
SW2
21‐28
C4
10uF x2
L2
150nH
VOUT2
C6
22uF x5
PGND
19, 20
Figure 3: High Density Two Phase Voltage Regulator
3
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May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1, 40, 41
VIN1
High current input supply pads. Connected to Drains of Q1. Recommended operating
range is 4.5V to 21V. Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF
0402 ceramic capacitor. Place the capacitors as close as possible to VIN1 pins (40 and 41)
and PGND pins (38 and 39). The 0.1uF 0402 capacitor should be on the same side of the
PCB as the IRF3546.
2-6, 10-14
No Connect
7
GATEH1
8, 19, 20,
38, 39, 42
PGND
9
GATEH2
No connects. These pins can be connected to the VIN planes to reduce PCB trace
resistances.
Gate connection of the Channel 1 control MOSFET Q1.
High current Power Ground. Connected to Sources of Q2 and Q4. Note all pads are
internally connected in the package. Provide low resistance connections to the ground
plane and respective output capacitors.
Gate connection of the Channel 2 control MOSFET Q3.
High current input supply pads. Connected to Drains of Q3. Recommended operating
range is 4.5V to 21V. Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF
0402 ceramic capacitor. Place the capacitors as close as possible to VIN2 pins (16 and 17)
and PGND pins (19 and 20). The 0.1uF 0402 capacitor should be on the same side of the
PCB as the IRF3546.
15-17
VIN2
18
GATEL2
21-28
SW2
High Current Switch Node output for Channel 2. Connected to Source of Q3 and Drain of
Q4.
29-36
SW1
High Current Switch Node output for Channel 1. Connected to Source of Q1 and Drain of
Q2.
37
GATEL1
4
Gate connection of the Channel 2 synchronous MOSFET Q4.
Gate connection of the Channel 1 synchronous MOSFET Q2.
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May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
Parameter
VDS
Q1 and Q3 Max.
Drain-to-Source Voltage
Q2 and Q4 Max.
25
Units
V
VGS
Gate-to-Source Voltage
ID @TC = 25°C
Continuous Drain Current, VGS @ 10V
±20
ID @TC = 70°C
Continuous Drain Current, VGS @ 10V
13
16
A
IDM
Pulse Drain Current
130
160
A
EAS
Single Pulse Avalanche Energy
16
50
NOTE 1
V
20
200
NOTE 2
A
mJ
THERMAL INFORMATION
Thermal Resistance, Junction to Top (θJC_TOP)
11.3 °C/W
Thermal Resistance, Junction to PCB (pin 28) (θJB)
1.6 °C/W
Thermal Resistance (θJA)
NOTE 3
18.4 °C/W
Maximum Operating Junction Temperature
-40°C to 150°C
Maximum Storage Temperature Range
-55°C to 150°C
MSL Rating
MSL3
Reflow Temperature
260°C
Notes
1.
TJ =25°C, L =100uH, RG =50Ω, IAS =32A. 2.
TJ =25°C, L =100uH, RG =50Ω, IAS =63A.
3.
Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air.
Refer to International Rectifier Application Note AN-994 for details.
5
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May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block ELECTRICAL SPECIFICATIONS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C.
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Efficiency
Power Block per-channel Peak Efficiency
η
Note 2
94
%
Note 3
93
%
Control MOSFETs (Q1 and Q3)
Drain-to-Source On-Resistance
RDS(ON)_4.5V_25°C
VGS=4.5V, ID=13A, TJ=25°C
4.1
4.8
mΩ
Drain-to-Source On-Resistance
RDS(ON)_10V_25°C
VGS=10V, ID=27A, TJ=25°C
3.2
3.9
mΩ
Drain-to-Source Breakdown Voltage
BVDSS
VGS=0V, ID=250uA, TJ=25°C
Breakdown Voltage Temperature
Coefficient
∆BVDSS / ∆TJ
TJ=25°C -125°C, Note 1
V
0.02
V/°C
Drain-to-Source Leakage Current
IDSS
VDS=20V, VGS=0V, TJ=25°C
1
μA
Gate-to-Source Forward Leakage Current
IGSS
VGS=16V
100
nA
Gate-to-Source Reverse Leakage Current
IGSS
VGS=-16V
-100
nA
Gate Threshold Voltage
VGS(th)
VDS= VGS, ID=35uA
Gate Threshold Voltage Coefficient
∆VGS(th)
VDS= VGS, ID=35uA
-5.7
Qg
VDS= 13V, VGS=4.5V, ID=13A,
Note 1
9.7
Total Gate Charge
1.1
1.6
2.1
V
mV/°C
15
nC
Pre-Vth Gate-to-Source Charge
Qgs1
VDS= 13V, VGS=4.5V, ID=13A
2.3
nC
Post-Vth Gate-to-Source Charge
Qgs2
VDS= 13V, VGS=4.5V, ID=13A
1.8
nC
Gate-to-Drain Charge
Qgd
VDS= 13V, VGS=4.5V, ID=13A
3.1
nC
Gate Charge Overdrive
VDS= 13V, VGS=4.5V, ID=13A
2.9
nC
QSW
VDS= 13V, VGS=4.5V, ID=13A
4.9
nC
Output Charge
Qoss
VDS= 16V, VGS=0V
Gate Resistance
Rg
Switch Charge (Qgs2 +Qgd )
Turn-On Delay Time
Qgodr
13
nC
0.6
Ω
td(on)
VDD= 13V, VGS=4.5V, ID=13A,
RG=1.8 Ω
7.5
ns
tr
VDD= 13V, VGS=4.5V, ID=13A,
RG=1.8 Ω
12
ns
td
VDD= 13V, VGS=4.5V, ID=13A,
RG=1.8 Ω
6.7
ns
tf
VDD= 13V, VGS=4.5V, ID=13A,
RG=1.8 Ω
4.2
ns
Input Capacitance
Ciss
VGS= 0V, VDS=13V, f=1.0MHz
1310
pF
Output Capacitance
Coss
VGS= 0V, VDS=13V, f=1.0MHz
380
pF
Reverse Transfer Capacitance
Crss
VGS= 0V, VDS=13V, f=1.0MHz
90
pF
Diode Forward Voltage
VSD
VGS=0V, IS=13A, TJ=25°C
0.80
0.88
V
trr
TJ=25°C, IF=30A, VDD=13V,
di/dt=200A/us, Note 1
15
23
ns
Qrr
TJ=25°C, IF=30A, VDD=13V,
di/dt=200A/us, Note 1
10
15
nC
Rise Time
Turn-Off Delay Time
Fall Time
Reverse Recovery Time
Reverse Recovery Charge
25
6
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0.72
May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Synchronous MOSFETs (Q2 and Q4)
Drain-to-Source On-Resistance
RDS(ON)_4.5V_25°C
VGS=4.5V, ID=16A, TJ=25°C
1.8
2.2
mΩ
Drain-to-Source On-Resistance
RDS(ON)_10V_25°C
VGS=10V, ID=30A, TJ=25°C
1.35
1.8
mΩ
Drain-to-Source Breakdown Voltage
BVDSS
VGS=0V, ID=1mA, TJ=25°C
Breakdown Voltage Temperature
Coefficient
∆BVDSS / ∆TJ
TJ=25°C -125°C, Note 1
Drain-to-Source Leakage Current
IDSS
VDS=20V, VGS=0V, TJ=25°C
250
uA
Gate-to-Source Forward Leakage Current
IGSS
VGS=16V
100
nA
Gate-to-Source Reverse Leakage Current
IGSS
VGS=-16V
-100
nA
Gate Threshold Voltage
VGS(th)
VDS= VGS, ID=100uA
2.1
V
Gate Threshold Voltage Coefficient
∆VGS(th)
VDS= VGS, ID=1mA
Qg
VDS= 13V, VGS,=4.5V, ID=30A,
Note 1
22
Total Gate Charge
25
V
0.02
1.1
1.6
V/°C
-5.4
mV/°C
33
nC
Pre-Vth Gate-to-Source Charge
Qgs1
VDS= 13V, VGS=4.5V, ID=30A
5.1
nC
Post-Vth Gate-to-Source Charge
Qgs2
VDS= 13V, VGS=4.5V, ID=30A
3.1
nC
Gate-to-Drain Charge
Qgd
VDS= 13V, VGS=4.5V, ID=30A
6.0
nC
Gate Charge Overdrive
Qgodr
VDS= 13V, VGS=4.5V, ID=30A
6.7
nC
QSW
VDS= 13V, VGS=4.5V, ID=30A
9.1
nC
Output Charge
Qoss
VDS= 16V, VGS=0V
Gate Resistance
Rg
Switch Charge (Qgs2 +Qgd )
Turn-On Delay Time
23
nC
0.4
Ω
td(on)
VDD= 13V, VGS=4.5V, ID=16A,
RG=1.3 Ω
13
ns
tr
VDD= 13V, VGS=4.5V, ID=16A,
RG=1.3 Ω
15
ns
td
VDD= 13V, VGS=4.5V, ID=16A,
RG=1.3 Ω
16
ns
tf
VDD= 13V, VGS=4.5V, ID=16A,
RG=1.3 Ω
6.6
ns
Input Capacitance
Ciss
VGS= 0V, VDS=13V, f=1.0MHz
2880
pF
Output Capacitance
Coss
VGS= 0V, VDS=13V, f=1.0MHz
950
pF
Rise Time
Turn-Off Delay Time
Fall Time
Reverse Transfer Capacitance
Crss
VGS= 0V, VDS=13V, f=1.0MHz
Diode Forward Voltage
VSD
VGS=0V, IS=30A, TJ=25°C
0.63
0.70
0.77
V
Diode Forward Voltage
VSD
VGS=0V, IS=13A, TJ=25°C
0.54
0.60
0.66
V
trr
TJ=25°C, IF=30A, VDD=13V,
di/dt=200A/us, Note 1
23
35
ns
Qrr
TJ=25°C, IF=30A, VDD=13V,
di/dt=200A/us, Note 1
30
45
nC
Reverse Recovery Time
Reverse Recovery Charge
180
pF
Notes
1. Guaranteed by design but not tested in production
2. VIN=12V, VOUT=1.2V, ƒSW = 300kHz, L=210nH (0.29mΩ), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, 400LFM airflow, no heat sink, 25°C
ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
3. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C
ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
7
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May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
TYPICAL OPERATING CHARACTERISTICS
TA = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.
1000
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
100
10
VGS
10V
5V
4.5V
3.5V
3.3V
3V
2.8V
TOP
1
0.1
1
10
TOP
10
1
0.1
0.1
100
1
Figure 7: Q2 & Q4 Typical Output Characteristics
1000
1000
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
Figure 4: Q1 & Q3 Typical Output Characteristics
100
TOP
10
1
<=60us PULSE WIDTH
VGS
10V
5V
4.5V
3.5V
3.3V
3V
2.8V
100
TOP
10
1
<=60us PULSE WIDTH
BOTTOM 2.5V
0.1
VGS
10V
5V
4.5V
3.5V
3.3V
3V
2.8V
BOTTOM 2.5V
0.1
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
o
Figure 5: Q1 & Q3 Typical Output Characteristics @150 C
o
Figure 8: Q2 & Q4 Typical Output Characteristics @150 C
1000
ID, Drain-to-Source Current (A)
1000
ID, Drain-to-Source Current (A)
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
VDS=15V, <=60us PULSE WIDTH
100
TJ =150oC
TJ=25 oC
TJ=-40oC
10
1
0.1
VDS=15V, <=60us PULSE WIDTH
100
TJ =150oC
TJ=25oC
TJ=-40oC
10
1
0.1
1
1.5
2
2.5
3
3.5
4
VGS, Gate-to-Source Voltage (V)
Figure 6: Q1 and Q3 Typical Transfer Characteristics
VGS
10V
5V
4.5V
3.5V
3.3V
3V
2.8V
BOTTOM 2.5V
BOTTOM 2.5V
0.1
100
8
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1
1.5
2
2.5
3
3.5
4
VGS, Gate-to-Source Voltage (V)
Figure 9: Q2 and Q4 Typical Transfer Characteristics
May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block TYPICAL OPERATING CHARACTERISTICS (CONTINUE)
TA = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.
6
12
ID = 27A
8
6
TJ =125oC
4
2
ID = 30A
5
Typical R DS(on) (mΩ)
Typical R DS(on) (mΩ)
10
4
3
TJ =125oC
2
1
TJ =25oC
TJ =25oC
0
0
0
2
4
6
8
10
12
14
0
16
2
4
8
10
2.0
Typical R DS(on) (Normalized)
ID = 27A
1.8
VGS = 10V
1.6
1.4
1.2
1.0
0.8
16
ID = 30A
1.8
VGS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
-40
-20
0
20
40
60
80
100
120
140
160
-40
-20
o
0
20
40
60
80
100
120
140
TJ, Junction Temperature ( C)
Figure 11: Q1 & Q3 On-Resistance vs. Temperature
Figure 14: Q2 & Q4 On-Resistance vs. Temperature
10000
10000
VGS = 0V
Typical Capacitance (pF)
VGS = 0V
f =1MHz
Ciss
1000
Coss
Crss
100
160
o
TJ, Junction Temperature ( C)
Typical Capacitance (pF)
14
2.0
0.6
10
Ciss
f =1MHz
Coss
1000
Crss
100
1
10
100
VGS, Drain-to-Source Voltage (V)
Figure 12: Q1 & Q3 Typical Capacitance vs.
Drain-Source Voltage
12
Figure 13: Q2 & Q4 Typical On-Resistance
Figure 10: Q1 & Q3 Typical On-Resistance
Typical R DS(on) (Normalized)
6
VGS, Gate-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
9
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1
10
100
VGS, Drain-to-Source Voltage (V)
Figure 15: Q2 & Q4 Typical Capacitance vs.
Drain-Source Voltage
May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block TYPICAL OPERATING CHARACTERISTICS (CONTINUE)
TA = 25°C, no heat sink, no air flow, 4-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.
4.0
10
9
7
6
Typical R DS(on) (mΩ)
Typical R DS(on) (mΩ)
3.5
VGS = 4.5V
VGS = 6V
VGS = 7V
VGS = 8V
8
VGS = 10V
5
4
3
VGS = 4.5V
VGS = 6V
VGS = 7V
VGS = 8V
3.0
2.5
VGS = 10V
2.0
1.5
1.0
2
0.5
1
0.0
0
0
20
40
60
80
100
120
140
0
160
20
40
60
TJ = 150oC
Reverse Drain Current (A)
Reverse Drain Current (A)
120
140
160
180
200
1000
1000
o
TJ = 25 C
100
TJ = -40oC
10
1
TJ = 150 oC
TJ = 25 oC
100
TJ = -40 oC
10
1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0
1.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VSD, Source-Drain Forward Voltage (V)
VSD, Source-Drain Forward Voltage (V)
Figure 17: Q1 & Q3 Drain-Source Diode Characteristics
Figure 20: Q2 & Q4 Drain-Source Diode Characteristics
2.5
Gate Threshold Voltage VGS(th) (V)
2.5
Gate Threshold Voltage VGS(th) (V)
100
Figure 19: Q2 & Q4 Typical On-Resistance
Figure 16: Q1 & Q3 Typical On-Resistance
2.0
1.5
ID = 10mA
ID = 1mA
1.0
ID = 0.25mA
0.5
ID = 0.035mA
ID = 0.1mA
2.0
ID = 100mA
1.5
ID = 10mA
1.0
0.5
0.0
0.0
-40
-20
0
20
40
60
80
100
120
140
160
o
TJ, Junction Temperature ( C)
Figure 18: Q1 & Q3 Typical Threshold Voltage vs.
Junction Temperature
80
ID, Drain Current (A)
ID, Drain Current (A)
10
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-40
-20
0
20
40
60
80
100
120
140
160
o
TJ, Junction Temperature ( C)
Figure 21: Q2 & Q4 Typical Threshold Voltage vs.
Junction Temperature
May 29, 2013 | Final
IRF3546
60A Dual Integrated Power Block TYPICAL OPERATING CHARACTERISTICS (CONTINUE)
TA = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.
3000
Single Pulse Avalanche Energy (mJ)
Single Pulse Avalanche Energy (mJ)
400
350
300
250
ID = 5A
ID = 8.7A
200
ID = 30A
150
100
50
2500
2000
ID = 6.5A
ID = 11A
1500
ID = 30A
1000
500
0
0
25
50
75
100
125
25
150
75
100
125
150
TJ, Starting Junction Temperature ( C)
Figure 22: Q1 & Q3 Single Pulse Avalanche Energy
Figure 25: Q2 & Q4 Single Pulse Avalanche Energy
30
45
40
25
35
ID, Drain Current (A)
ID, Drain Current (A)
50
o
o
TJ, Starting Junction Temperature ( C)
20
15
10
5
30
25
20
15
10
5
0
25
50
75
100
125
0
150
25
o
50
TA , Ambient Temperature ( C)
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
100us
1ms
10
10ms
1
DC
0
TA = 25oC
TJ = 150oC
Single Pulse
0
0.01
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Figure 24: Q1 & Q3 Maximum Safe Operating Area
11
125
150
Figure 26: Q2 & Q4 Maximum Drain Current vs. Temperature
OPERATION IN THIS AREA LIMITED BY RDS(on)
100
100
o
Figure 23: Q1 & Q3 Maximum Drain Current vs. Temperature
1000
75
TA , Ambient Temperature ( C)
www.irf.com | © 2013 International Rectifier
OPERATION IN THIS AREA LIMITED BY RDS(on)
100us
100
1ms
10
10ms
1
0
0
0.01
DC
TA = 25 oC
TJ = 150oC
Single Pulse
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Figure 27: Q2 & Q4 Maximum Safe Operating Area
May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
GENERAL DESCRIPTION
PCB LAYOUT CONSIDERATION
The IRF3546 contains two pairs of integrated high
and low side N-channel MOSFETs. It is suitable for
high switching frequency operation.
PCB layout and design is important to driver
performance in voltage regulator circuits due to the
high current slew rate (di/dt) during MOSFET
switching.
The IRF3546 can be driven as two independent
power stages or as one power stage in a two-phase
interleaved converter .
APPLICATION INFORMATION
Figure 3 shows a typical two phase, high density
application circuit for the IRF3546.
SUPPLY DECOUPLING CAPACITOR
At least two 10uF 1206 ceramic capacitors and one
0.1uF 0402 ceramic capacitor are recommended for
decoupling the VIN to PGND connection of each
MOSFET pair. The 0.1uF 0402 capacitor should be
on the same side of the PCB as the IRF3546 and
next to the VIN and PGND pins. Adding additional
capacitance and use of capacitors with lower ESR
and mounted with low inductance routing will
improve efficiency and reduce overall system noise,
especially in high current applications.
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Locate all power components in each phase as
close to each other as practically possible in order to
minimize parasitics and losses, allowing for
reasonable airflow.
Input supply decoupling capacitors should be
physically located close to their respective pins.
High current paths like the gate driver traces should
be as wide and short as practically possible.
GATEL1 and GATEL2 interconnect trace inductances
should be minimized to prevent Cdv/dt turn-on of the low
side MOSFET.
The ground connection should be as close as
possible to the low-side MOSFET source.
Use of a copper plane under and around the device
and thermal vias to connect to buried copper layers
improves the thermal performance substantially.
May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
METAL AND COMPONENT PLACEMENT
• Lead land width should be equal to nominal
part lead width. The minimum lead to lead
spacing should be ≥ 0.2mm to prevent
shorting.
• Lead land length should be equal to
maximum part lead length +0.15 - 0.3 mm
outboard extension and 0 to + 0.05mm
inboard extension. The outboard extension
ensures a large and visible toe fillet, and the
inboard extension will accommodate any part
misalignment and
ensure a fillet.
• Center pad land length and width should be
equal to maximum part pad length and width.
• Only 0.30mm diameter via shall be placed in
the area of the power pad lands and
connected to power planes to minimize the
noise effect and to improve thermal
performance.
Figure 28: Metal and Component Placement
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www.irf.com | © 2013 International Rectifier
May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
SOLDER RESIST
• The solder resist should be pulled away
from the metal lead lands by a minimum
of 0.06mm. The solder resist miss-alignment
is a maximum of 0.05mm and it is
recommended that the low power signal lead
lands are all Non Solder Mask Defined
(NSMD). Therefore pulling the S/R 0.06mm
will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm
typical.
• At the inside corner of the solder resist
where the lead land groups meet, it is
recommended to provide a fillet so a solder
resist width of ≥ 0.17mm remains.
• The power land pads VIN1, VIN2, PGND,
SW1 and SW2 should be Solder Mask
Defined (SMD).
• Ensure that the solder resist in-between the
lead lands and the pad land is ≥ 0.15mm due
to the high aspect ratio of the solder resist
strip separating the lead lands from the pad
land.
Figure 29: Solder Resist
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May 29, 2013 | Final
60A Dual Integrated Power Block STENCIL DESIGN
• The stencil apertures for the lead lands
should be approximately 65% to 75% of the
area of the lead lands depending on stencil
thickness. Reducing the amount of solder
deposited will minimize the occurrence of
lead shorts. Since for 0.5mm pitch devices
the leads are only 0.25mm wide, the stencil
apertures should not be made narrower;
openings in stencils < 0.25mm wide are
difficult to maintain repeatable solder release.
• The low power signal stencil lead land
apertures should therefore be shortened in
length to keep area ratio of 65% to 75% while
centered on lead land.
IRF3546
• The power pads VIN1, VIN2, PGND, SW1
and SW2, land pad apertures should be
approximately 65% to 75% area of solder on
the center pad. If too much solder is
deposited on the center pad the part will float
and the lead lands will be open. Solder paste
on large pads is broken down into small
sections with a minimum gap of 0.2mm
between allowing for out-gassing during
solder reflow.
• The maximum length and width of the land
pad stencil aperture should be equal to the
solder resist opening minus an annular
0.2mm pull back to decrease the incidence of
shorting the center land to the lead lands
when the part is pushed into the solder paste.
Figure 30: Stencil Design
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May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
MARKING INFORMATION
Assembly Site(?)/Date(YWW)/Marking Code(?)
/
Lot Code
F3546M
?YWW?
xxxx
Figure 31: PQFN 6mm x 8mm
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www.irf.com | © 2013 International Rectifier
May 29, 2013 | Final
60A Dual Integrated Power Block IRF3546
PACKAGE INFORMATION
Figure 32: PQFN 6mm x 8mm
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www.irf.com | © 2013 International Rectifier
May 29, 2013 | Final
60A Dual Integrated PowIRblock
TM
IRF3546
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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www.irf.com | © 2013 International Rectifier
May 29, 2013 | Final