TI SN65HVD1040-HT

SN65HVD1040-HT
www.ti.com
SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
LOW-POWER CAN TRANSCEIVER WITH BUS WAKE-UP
Check for Samples: SN65HVD1040-HT
FEATURES
1
•
•
•
•
•
•
•
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours continuous
operating life at maximum rated temperature.
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•
•
Improved Drop-in Replacement for the
TJA1040
±12 kV ESD Protection
Low-Current Standby Mode with Bus Wake-up:
5 μA Typical
Bus-Fault Protection of –27 V to 40 V
Rugged Split-Pin Bus Stability
Dominant Time-Out Function
Thermal Shutdown Removed
Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Input Impedance with Low VCC
– Monotonic Outputs During Power Cycling
DeviceNet Vendor ID # 806
Down-Hole Drilling
High Temperature Environments
Vibration/Modal Analysis
Multi-Channel Data Acquisition
Acoustics/Dynamic Strain Gauges
Pressure Sensors
SN65HVD1040
TXD
GND
VCC
RXD
(1)
1
8
2
7
3
6
4
5
STB
CANH
CANL
SPLIT
Custom temperature ranges available
DESCRIPTION
The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in applications
employing a Controller Area Network (CAN). As CAN transceivers, these devices provide differential transmit and
receive capability for a CAN controller at signaling rates of up to 1 megabit per second (Mbps). (2)
Designed for operation in especially harsh environments, the device features ±12 kV ESD protection on the bus
and split pins, cross-wire, overvoltage and loss of ground protection from –27 to 40 V, a –12 V to 12 V commonmode range, and will withstand voltage transients from –200 V to 200 V according to ISO 7637.
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The
high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor
standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater
than 5 μs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may
then reactivate the device when it needs to transmit to the bus.
(2)
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
SN65HVD1040-HT
SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
www.ti.com
A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication
during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no
rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then
reset by the next rising edge on TXD.
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a
split-termination network.
The SN65HVD1040 is characterized for operation from –55°C to 210°C.
VCC
VCC
OVER
TEMPERATURE
SENSOR
3
VCC / 2
5
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DOMINANT
TIME -OUT
TXD
30 mA
1
INPUT
LOGIC
SPLIT
DRIVER
VCC
7
STB
RXD
8
4
10 mA
6
SLEEP
OUTPUT
LOGIC
MODE
CANH
CANL
MUX
WAKE UP
FILTER
BUS MONITOR
2
2
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 210°C
KGD (bare die)
SN65HVD1040SKGD1
NA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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BARE DIE INFORMATION
DIE
THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
BOND PAD THICKNESS
15 mils.
Silicon with backgrind
Floating
CuNiPd
15 microns
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Table 2. BOND PAD COORDINATES (µm)
DESCRIPTION PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
PAD SIZE X
PAD SIZE Y
TXD
1
53.64
162
137.7
246.06
84.06
84.06
GND
2
804.06
50.85
888.12
134.91
84.06
84.06
GND
3
920.07
50.85
1004.13
134.91
84.06
84.06
Vcc
4
1320.21
54.18
1404.27
138.24
84.06
84.06
Vcc
5
1431.09
54.18
1515.15
138.24
84.06
84.06
RXD
6
2148.75
164.34
2232.81
248.4
84.06
84.06
SPLIT
7
2147.4
707.49
2231.46
791.55
84.06
84.06
CANH
STB
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CANL
8
771.93
907.38
855.99
991.44
84.06
84.06
9
527.31
907.38
611.37
991.44
84.06
84.06
10
62.28
806.13
146.34
890.19
84.06
84.06
ABSOLUTE MAXIMUM RATINGS (1)
VCC
VI(bus)
IO(OUT)
–0.3 V to 7 V
Voltage range at any bus terminal (CANH, CANL, SPLIT)
–27 V to 40 V
Receiver output current
-20 mA to 20 mA
Voltage input, transient pulse (3), (CANH, CANL, SPLIT)
ESD
IEC
VI
TJ
(1)
(2)
(3)
4
VALUE
Supply voltage (2)
–200 V to 200 V
IEC Contact Discharge
(IEC 61000-4-2)
Bus terminals vs GND
±6 kV
Human body model
JEDEC Standard 22,
Test Method A114-C.01
Bus terminals vs GND
±12 kV
All pins
±4 kV
Field-Induced-Charged
Device Model
JEDEC Standard 22,
Test Method C101
All pins
±1 kV
Machine model
ANSI/ESDS5.2-1996
Bus terminals vs GND
Voltage input range (TXD, STB)
±200 V
±6 kV
–0.5 V to 6 V
Junction temperature
–55°C to 210°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6 & 7.
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
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Estimated Life (Hrs)
100000
1000
130
140
150
160
170
180
190
200
210
220
Continuous TJ (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wear out for the specific device process and design characteristics.
Figure 1. SN65HVD1040-HT Operating Life Derating Chart
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RECOMMENDED OPERATING CONDITIONS
Tj = -55°C to 125°C
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common
mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
4.75
5.25
4.75
5.25
V
–12 (1)
12
–12 (1)
12
V
2
5.25
2
5.25
V
0
0.8
0
0.8
V
–6
6
–6
6
V
–70
–2
–2
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–70
NOM
High-level output current
IOL
Low-level output current
tSS
Maximum pulse width to remain in standby
TJ
Junction temperature
Receiver
Driver
Receiver
MAX
UNIT
MIN
Driver
IOH
(1)
Tj = -55°C to 210°C
MAX
TXD, STB
NOM
mA
70
70
2
2
0.7
–55
125
–55
mA
0.7
μs
210
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
SUPPLY CURRRENT
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
Supply current,
VCC
TEST CONDITIONS
Tj = -55°C to 125°C
MIN
Tj = -55°C to 210°C
TYP
MAX
MIN
TYP
MAX
Dominant
VI = 0 V, 60 Ω Load,
STB at 0 V
50
70
50
70
Recessive
VI = VCC, STB at 0 V
6
10
6
10
Standby
STB at VCC, VI = VCC
5
12
5
50
UNIT
mA
μA
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
tloop1
tloop2
6
Total loop delay, driver input
to receiver output, Recessive
to Dominant
Total loop delay, driver input
to receiver output, Dominant
to Recessive
TEST CONDITIONS
Tj = -55°C to 125°C
MIN
TYP
90
Tj = -55°C to 210°C
MAX
MIN
230
90
TYP
MAX
450
STB at 0 V,
See Figure 10
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90
230
90
UNIT
ns
450
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO(D)
Bus output
voltage
(Dominant)
VO(R)
Bus output voltage
(Recessive)
VI = 3 V, STB at 0 V, See Figure 2
and Figure 3
VO
Bus output voltage
(Standby)
RL = 60 Ω, STB at VCC, See
Figure 2 and Figure 3
CANL
VI = 0 V, STB at 0 V, RL = 60 Ω,
See Figure 2 and Figure 3
MAX
3.4
4.5
2.9
1.75
0.8
3
2
0.1
–0.15
MIN TYP
2.9
0.8
2
Tj = -55°C to 210°C
(1)
2.5
–0.1
MIN TYP (1)
3.4
Differential output
voltage (Dominant)
VSYM
Output symmetry
(Dominant or
Recessive)
[ VO(CANH) + VO(CANL)
]
VOD(R)
Differential output
voltage (Recessive)
VI = 0 V, RL = 60 Ω, STB at 0 V,
See Figure 2 and Figure 3, and
Figure 4
1.5
VI = 0 V, RL = 45 Ω, STB at 0 V,
See Figure 2 and Figure 3
1.4
STB at 0 V, See Figure 3 and
Figure 14
VI = 3 V, RL = 60 Ω, STB at 0 V,
See Figure 2 and Figure 3
VI = 3 V, STB at 0 V, No Load
3
MAX
2.5
1.5
V
0.15
V
3
V
1.4
1.1×VCC
0.9×VCC
–0.012
0.012
–0.015
0.02
–0.5
0.05
–0.75
0.8
3
2
VCC
VCC
V
3
3
0.9×VCC
UNIT
4.6
1.75
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VOD(D)
CANH
Tj = -55°C to 125°C
3
1.2×VCC
V
V
VOC(D)
Common-mode
output voltage
(Dominant)
VOC(pp)
Peak-to-peak
common-mode output
voltage
IIH
High-level input
current, TXD input
VI at VCC
–2
2
–3
3
μA
IIL
Low-level input
current, TXD input
VI at 0 V
–50
–10
–50
–10
μA
IO(off)
Power-off TXD
Leakage current
VCC at 0 V, TXD at 5 V
600
μA
2
IOS(ss)
0.3
(1)
Output capacitance
3.1
–120
VCANL = –12 V, CANH Open, See
Figure 13
–72
0.36
–1
–130
1
–0.5
71
V
0.3
1
VCANH = 12 V, CANL Open, See
Figure 13
VCANL = 12 V, CANH Open, See
Figure 13
CO
2.3
STB at 0 V, See Figure 9
VCANH = –12 V, CANL Open, See
Figure 13
Short-circuit steadystate output current
2.3
0.36
–1.1
120
–72
1.1
mA
–0.5
71
130
See Input capacitance to ground
in RECEIVER ELECTRICAL
CHARACTERISTICS .
All typical values are at 25°C with a 5-V supply.
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time, low-to-highlevel output
tPHL
Propagation delay time, high-to-lowlevel output
TEST CONDITIONS
Tj = -55°C to 125°C
Tj = -55°C to 210°C
MIN
TYP
MAX
MIN
TYP
MAX
25
65
120
25
65
250
25
45
120
25
45
250
STB at 0 V, See Figure 5
ns
Pulse skew (|tPHL – tPLH|)
25
25
tr
Differential output signal rise time
25
25
tf
Differential output signal fall time
50
50
ten
Enable time from silent mode to
dominant
See Figure 8
tdom
Dominant time-out
See Figure 11
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tsk(p)
8
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UNIT
11
300
450
700
300
450
18
μs
700
μs
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Tj = -55°C to 125°C
TEST CONDITIONS
MIN
Tj = -55°C to 210°C
TYP
MAX
800
900
MIN
TYP
MAX
800
900
UNIT
VIT+
Positive-going
input threshold
voltage
VIT–
Negative-going
input threshold
voltage
Vhys
Hysteresis
voltage
(VIT+ – VIT–)
VIT
Input threshold
voltage
VOH
High-level output voltage
IO = –2 mA, See Figure 7
VOL
Low-level output voltage
IO = 2 mA, See Figure 7
II(off)
Power-off bus input current
CANH or CANL = 5 V,
VCC at 0 V, TXD at 0 V
IO(off)
Power-off RXD leakage current
VCC at 0 V, RXD at 5 V
CI
Input capacitance to ground,
(CANH or CANL)
TXD at 3 V, VI = 0.4 sin
(4E6πt) + 2.5 V
20
20
pF
CID
Differential input capacitance
TXD at 3 V, VI = 0.4 sin
(4E6πt)
10
10
pF
RID
Differential input resistance
TXD at 3 V, STD at 0 V
30
RIN
Input resistance, (CANH or CANL)
TXD at 3 V, STD at 0 V
15
RI(m)
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x
100%
VCANH = VCANL
–3%
STB at 0 V, See Table 3
High-speed
mode
500
650
500
650
mV
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Standby mode
STB at VCC
100
STB at VCC
500
125
70
1150
4
400
4.6
4
0.2
125
0.4
1350
4.6
V
0.2
0.55
V
5
30
μA
20
30
μA
80
30
80
30
40
15
30
40
0%
3%
–12%
0%
12%
kΩ
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
Tj = -55°C to 125°C
TEST CONDITIONS
Tj = -55°C to 210°C
TYP
MAX
MIN
TYP
MAX
60
100
130
60
100
200
45
70
130
45
70
200
ns
5.25
μs
tpLH
Propagation delay time, low-tohigh-level output
tpHL
Propagation delay time, high-tolow-level output
tr
Output signal rise time
8
8
tf
Output signal fall time
8
8
tBUS
Dominant time required on bus for
wake-up from standby (1)
(1)
STB at 0 V, TXD at 3 V,
See Figure 7
STB at VCC Figure 12
UNIT
MIN
0.7
5
1.45
The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up
condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a
wake-up.
SPLIT-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
VO
IO(stb)
Output voltage
Standby mode leakage
current
TEST CONDITIONS
–500 μA < IO < 500 μA
STB at 2 V,
–12 V ≤ VO ≤ 12 V
Tj = -55°C to 125°C
MIN
TYP
0.3×VCC
0.5×VCC
–5
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Tj = -55°C to 210°C
MAX
MIN
0.7×VCC 0.28×VCC
5
–15
TYP
MAX
0.5×VC
0.7×VC
C
C
15
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UNIT
V
μA
9
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STB-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Tj = -55°C to 125°C
MIN
TYP
Tj = -55°C to 210°C
MAX
MIN
TYP
MAX
UNIT
IIH
High level input current
STB at 2 V
–10
0
–10
0
μA
IIL
Low level input current
STB at 0 V
–10
0
–10
0
μA
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PARAMETER MEASUREMENT INFORMATION
Dominant
IO(CANH)
II
TXD
VOD
3.5 V
Recessive
RL VO(CANH)
2.5 V
VO(CANH) + VO(CANL)
2
VI
STB
VO(CANH)
1.5 V
VO(CANL)
VOC
IO(CANL)
VO(CANL)
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Figure 2. Driver Voltage, Current, and Test
Definition
CANH
0V
TXD
VOD
Figure 3. Bus Logic State Voltage Definitions
330 +1%
60 +1%
+
_
STB
CANL
−2 V 3 VTEST 3 7 V
330 +1%
Figure 4. Driver VOD Test Circuit
CANH
TXD
VI
(see Note A)
VCC
2
VI
RL = 60 W
VO
+1‘%
STB
CL = 100 pF +20%
(see Note B)
tPLH
0V
tPHL
90%
0.9 V
VO
CANH
VCC
VCC
2
10%
tr
V O(D)
0.5 V
VO(R)
tf
Figure 5. Driver Test Circuit and Voltage Waveforms
CANH
RXD
V I (CANH)
VIC =
IO
V ID
VI(CANH) + VI(CANL)
2
V I (CANL)
CANL
VO
Figure 6. Receiver Voltage and Current Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
3.5 V
CANH
1.5 V
CANL
1.5 V
IO
VI
(see NoteA)
2.4 V
2V
VI
RXD
tPLH
CL = 15 pF ±20%
(see Note B)
VO
STB
tPLH
V OH
90%
0.7 VCC
0.3 VCC
VO
10%
tf
tr
VOL
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A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6 ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 7. Receiver Test Circuit and Voltage Waveforms
Table 3. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
VOL
VOH
DUT
CANH
0V
VI
TXD
C
L
STB
CANL
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
60W ±1%
VI
VCC
50%
0V
VOH
50%
VO
ten
VOL
15 pF ±20%
Figure 8. ten Test Circuit and Voltage Waveforms
CANH
TXD
V
27 W +1%
I
CANL
STB
A.
27 W +1%
VOC(PP)
47 nF
+20%
VOC =
VO (CANH) + VO (CANL)
2
VOC
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. Peak-to-Peak Common Mode Output Voltage Test and Waveform
12
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
DUT
CANH
TXD
C
L
STB
CANL
50%
0V
tloop2
tloop1
VOH
RXD Output
50%
50%
VOL
15 pF 20%
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A.
TXD
Input
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
VCC
60 W 1%
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 10. tloop Test Circuit and Voltage Waveforms
CANH
TXD
VO
RL = 60 W +1%
VI
CL
(see Note B)
(see Note A)
VCC
VI
VO
CANL
STB
900 mV
0V
VOD(D)
500 mV
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 11. Dominant Time-Out Test Circuit and Waveform
CANH
VCC
STB
RXD
VI
IO
VI
(see Note A)
CANL
1.5 V
(see Note B)
CL
VO
0.7 s
VO
3.5 V
2.65 V
1.5 V
tBUS
VOH
400 mV
V OL
A.
For VI bit width ≤ 0.7 μs, VO = VOH. For VII bit width ≥ 5 μs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B.
CL = 15 pF includes instrumentation and fixture capacitance within ±20%.
Figure 12. tBUS Test Circuit and Waveform
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IOS
IOS(SS)
IOS(P)
CANH
TXD
200 ms
0 V or VCC
0V
STB
CANL
VIN
12 V
−12 V or 12 V
Vin
0V
10 ms
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or
0V
Vin
−12 V
Figure 13. Driver Short-Circuit Current Test and Waveform
CANH
60 W ± 1%
TXD
VI
60 W ± 1%
STB
CANL
V O (CANL)
4.7 nF
± 20%
VSYM =
+VO
VO(CANH)
(CANL)
VO (CANH)
Figure 14. Driver Output Symmetry Test Circuit
14
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
DEVICE INFORMATION
Table 4. DRIVER FUNCTION TABLE (1)
INPUTS
OUTPUTS
TXD
STB
CANH
BUS STATE
CANL
L
L
H
L
DOMINANT
H
L
Z
Z
RECESSIVE
Open
X
Z
Z
RECESSIVE
X
H or Open
Z
Z
RECESSIVE
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(1)
H = high level; L = low level; X = irrelevant; Z = high impedance
Table 5. RECEIVER FUNCTION TABLE (1)
DIFFERENTIAL INPUTS
VID = CANH - CANL
STB
OUTPUT
RXD
BUS STATE
VID ≥ 0.9 V
L
L
DOMINANT
DOMINANT
(1)
VID ≥ 1.15 V
H or Open
L
0.5 V < VID < 0.9 V
X
?
?
VID ≤ 0.5 V
X
H
RECESSIVE
Open
X
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z =
high impedance
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SN65HVD1040-HT
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DEVICE INFORMATION
Table 6. Parametric Cross Reference With the TJA1040
TJA1040
(1)
PARAMETER
HVD10xx
TJA1040 DRIVER SECTION
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
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VIH
TJA1040 BUS SECTION
Vth(dif)
Differential input voltage
Receiver VIT and recommended VID
Vhys(dif)
Differential input hysteresis
Receiver Vhys
VO(dom)
Dominant output voltage
Driver VO(D)
VO(reces)
Recessive output voltage
Driver VO(R)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
VO(dif0(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(def)
Differential input resistance
Receiver RID
Ri(cm) (m)
Input resistance matching
Receiver RI (m)
Ci(cm)
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
VO
Reference output voltage
TJA1040 RECEIVER SECTION
TJA1040 SPLIT PIN SECTION
VO
TJA1040 TIMING SECTION
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
tPD(TXD–RXD)
Prop delay TXD to RXD
Device tLOOP1 and tLOOP2
td(stb-norm)
Enable time from standby to dominant
Driver ten
TJA1040 STB PIN SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
(1)
16
From TJA1040 Product Specification, Philips Semiconductors, 2003 February 19.
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
Equivalent Input and Output Schematic Diagrams
TXD Input
RXD Output
Vcc
Vcc
15 W
4. 3 k W
Output
Input
6V
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6V
CANH Input
CANL Input
Vcc
Vcc
10 k W
10 k W
Input
20 k W
Input
10 kW
40 V
20 k W
40 V
10 k W
CANH and CANL Outputs
STB Input
Vcc
Vcc
4. 3 k W
Output
Input
40 V
6V
SPLIT Output
Vcc
2kW
Output
2k W
40 V
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TYPICAL CHARACTERISTICS
145
140
135
130
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 4.75 V
VCC = 5 V
125
VCC = 5.25 V
−40
50
45
40
35
30
25
20
15
10
5
0
0
25
70
TA − Free-Air Temperature − °C
170
165
160
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 5.25 V
155
VCC = 5 V
150
145
−40
0
25
70
125
TA − Free-Air Temperature − °C
Figure 15.
Figure 16.
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
90
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
RXD = 15 pF
80
70
60
50
40
30
20
TA = 255C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
10
0
200
400
500
600
800
Signaling Rate − kbps
1000
−10
0
1
2
3
4
5
VOCANL − Low-Level Output Voltage − V
Figure 17.
18
VCC = 4.75 V
140
125
I OL − Low-Level Output Current − mA
120
I CC − RMS Supply Current − mA
t LOOP2 − Dominant-to-Recessive Loop Time − ns
150
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
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t LOOP1− Recessive-to-Dominant Loop Time − ns
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
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Figure 18.
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
-70
-60
0
0
1
2
3
4
5
VOCANH − High-Level Output Voltage − V
15
10
5
0
6
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
VIT+
VIT−
5
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 255C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
0
−1
1
2
3
3.5
4
4.5
VCC − Supply Voltage − V
5
5.25
0.60
20
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
125
0.65
25
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
0.70
30
Figure 20.
0.75
35
Figure 19.
0.80
40
0
25
70
TA − Free-Air Temperature − °C
0.85
45
−40
VO − Receiver Output Voltage − V
I O − Differential Driver Output Current − mA
50
0.5
0.85
1
-0
S at 0 V,
RL = 60 W,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.80
-10
1
0.75
-20
VCC = 4.75 V
1.5
0.70
-30
VCC = 5.25 V
2
0.65
-40
VCC = 5 V
2.5
0.60
-50
3
Dominant Driver Differential Output Voltage − V
TA = 25 C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
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I OH − High-Level Output Current − mA
-80
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE (across VCC)
VID − Differential Input Voltage − V
Figure 21.
Figure 22.
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SN65HVD1040-HT
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TYPICAL CHARACTERISTICS (continued)
TYPICAL ELECTROMAGNETIC EMISSIONS
UP TO 50 MHZ (Peak Amplitude)
TYPICAL ELECTROMAGNETIC
IMMUNITY PERFORMANCE
80
dBm
40
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DB mV
60
20
0
0.1
Figure 23. Frequency Spectrum of Common-Mode
Emissions
20
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1
10
f − Frequency − MHz
100
1000
Figure 24. Direct Power Injection (DPI) Response vs
Frequency
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SLLSEA6A – DECEMBER 2011 – REVISED FEBRUARY 2012
APPLICATION INFORMATION
CAN Basics
The basics of arbitration require that the receiver at the sending node designate the first bit as dominant or
recessive after the initial wave of the first bit of a message travels to the most remote node on a network and
back again. Typically, this “sample” is made at 75% of the bit width, and within this limitation, the maximum
allowable signal distortion in a CAN network is determined by network electrical parameters.
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Factors to be considered in network design include the approximately 5 ns/m propagation delay of typical
twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in
a system also need to be accounted for with adjustments in signaling rate and stub and bus length. Table 7 lists
the maximum signaling rates achieved with the SN65HVD1040 with several bus lengths of category 5, shielded
twisted pair (CAT 5 STP) cable.
Table 7. Maximum Signaling Rates for Various Cable
Lengths
Bus Length (m)
Signaling Rate (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large
number of nodes requires a transceiver with high input impedance such as the HVD1040.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the Standard’s –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The HVD1040 enhances the Standard’s insurance of data
integrity with an extended –12 V to 12 V range of common-mode operation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN65HVD1040SHKQ
PREVIEW
CFP
HKQ
8
25
TBD
Call TI
Call TI
SN65HVD1040SKGD3
ACTIVE
XCEPT
KGD
0
228
TBD
Call TI
N / A for Pkg Type
(1)
(3)
Samples
(Requires Login)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1040-HT :
• Catalog: SN65HVD1040
• Automotive: SN65HVD1040-Q1
NOTE: Qualified Version Definitions:
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• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿 话 油
圳 电 石
深 系 理
联 代
业
专
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿 话 油
圳 电 石
深 系 理
联 代
业
专
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Applications
www.ti.com/audio
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amplifier.ti.com
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dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
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www.ti.com/consumer-apps
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dsp.ti.com
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www.ti.com/energy
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www.ti.com/clocks
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www.ti.com/industrial
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interface.ti.com
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www.ti.com/medical
logic.ti.com
Security
www.ti.com/security
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
Audio
Amplifiers
Logic
Power Mgmt
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
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e2e.ti.com
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