CAV24C02, CAV24C04, CAV24C08, CAV24C16 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM Description The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb respectively CMOS Serial EEPROM devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16 device on the same bus. Features • • • • • • • • • • • Automotive Temperature Grade 1 (−40°C to +125°C) Supports Standard and Fast I2C Protocol 2.5 V to 5.5 V Supply Voltage Range 16−Byte Page Write Buffer Hardware Write Protection for Entire Memory CAV Prefix for Automotive and Other Applications Requiring Site and Change Control Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VCC SCL A2, A1, A0 CAV24Cxx SDA http://onsemi.com TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 W SUFFIX CASE 751BD PIN CONFIGURATIONS SOIC (W), TSSOP (Y) CAV24C__ 16 / 08 / 04 / 02 NC / NC / NC / A0 1 8 VCC NC / NC / A1 / A1 2 7 WP NC / A2 / A2 / A2 3 6 SCL 4 5 SDA VSS (Top View) PIN FUNCTION Pin Name A0, A1, A2 Function Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground NC No Connect ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. WP VSS Figure 1. Functional Symbol © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 2 1 Publication Order Number: CAV24C02/D CAV24C02, CAV24C04, CAV24C08, CAV24C16 DEVICE MARKINGS (TSSOP−8) (SOIC−8) CSSS AYMXXX G CSSS SSS SSS SSS SSS A Y M XXX G 24CSSS AYMXXX G = Specific Device Code, where = 02H for CAV24C02 = 04K for CAV24C04 = 08K for CAV24C08 = 16K for CAV24C16 = Assembly Location = Production Year (Last Digit) = Production Month (1−9, O, N, D) = Last Three Digits of Assembly Lot Number = Pb−Free Package 24CSSS = Specific Device Code, where SSS = 02H for CAV24C02 SSS = 04K for CAV24C04 SSS = 08K for CAV24C08 SSS = 16K for CAV24C16 A = Assembly Location Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXX = Last Three Digits of Assembly Lot Number G = Pb−Free Package Table 1. ABSOLUTE MAXIMUM RATINGS Ratings Units Storage Temperature Parameters −65 to +150 °C Voltage on any pin with respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Parameter Symbol NEND (Note 3) TDR Endurance Data Retention Min Units 1,000,000 Program / Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, fSCL = 400 kHz 1 mA ICCW Write Current Write, fSCL = 400 kHz 2 mA 5 mA 2 mA −0.5 0.3 x VCC V ISB Standby Current All I/O Pins at GND or VCC IL I/O Pin Leakage Pin at GND or VCC TA = −40°C to +125°C VIL Input Low Voltage VIH Input High Voltage A0, A1, A2 and WP 0.7 x VCC VCC + 0.5 V SCL and SDA 0.7 x VCC 5.5 V VOL Output Low Voltage VCC > 2.5 V, IOL = 3 mA 0.4 V http://onsemi.com 2 CAV24C02, CAV24C04, CAV24C08, CAV24C16 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Parameter Symbol CIN (Note 4) SDA Pin Capacitance IWP (Note 5) WP Input Current Conditions Max Units VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF 6 pF VIN < VIH, VCC = 5.5 V 130 mA VIN < VIH, VCC = 3.6 V 120 VIN < VIH, VCC = 2.5 V 80 VIN > VIH 2 VIN < VIH, VCC = 5.5 V 50 VIN < VIH, VCC = 3.6 V 35 VIN < VIH, VCC = 2.5 V 25 VIN > VIH 2 Other Pins IA (Note 5) Address Input Current (A0, A1, A2) Product Rev H mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 5. A.C. CHARACTERISTICS (Note 6) (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Standard Parameter Symbol FSCL tHD:STA Min Clock Frequency Max Fast Min 100 START Condition Hold Time Max Units 400 kHz 4 0.6 ms tLOW Low Period of SCL Clock 4.7 1.3 ms tHIGH High Period of SCL Clock 4 0.6 ms tSU:STA START Condition Setup Time 4.7 0.6 ms tHD:DAT Data In Hold Time 0 0 ms tSU:DAT Data In Setup Time 250 100 ns tR SDA and SCL Rise Time 1000 300 ns tF (Note 6) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (Note 6) 0.6 4.7 1.3 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs ms ms 0.9 100 100 ms ns 100 ns tSU:WP WP Setup Time 0 0 ms tHD:WP WP Hold Time 2.5 2.5 ms tWR tPU (Notes 7, 8) Write Cycle Time 5 5 ms Power−up to Ready Mode 1 1 ms 6. Test conditions according to “AC Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Drive Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Time v 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Level 0.5 x VCC Output Test Load Current Source IOL = 3 mA; CL = 100 pF http://onsemi.com 3 CAV24C02, CAV24C04, CAV24C08, CAV24C16 Power−On Reset (POR) Each CAV24Cxx* incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A CAV24Cxx device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. *For common features, the CAV24C02/04/08/16 will be referred to as CAV24Cxx. bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see AC Characteristics). During data transfer, the SDA line must remain stable while the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at 1010 (Ah). The next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. The last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension bits are assigned as illustrated in Figure 3. A2, A1 and A0 must match the state of the external address pins, and a10, a9 and a8 are internal address bits. Functional Description The CAV24Cxx supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAV24Cxx acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire http://onsemi.com 4 CAV24C02, CAV24C04, CAV24C08, CAV24C16 SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 R/W CAV24C02 1 0 1 0 A2 A1 a8 R/W CAV24C04 1 0 1 0 A2 a9 a8 R/W CAV24C08 1 0 1 0 a10 a9 a8 R/W CAV24C16 Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP (w tSU:DAT) ACK DELAY (v tAA) START Figure 4. Acknowledge Timing tF tHIGH tR tLOW tLOW SCL tSU:STA tHD:DAT tHD:SDA tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 5. Bus Timing http://onsemi.com 5 tBUF CAV24C02, CAV24C04, CAV24C08, CAV24C16 WRITE OPERATIONS Byte Write sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAV24Cxx in a single write cycle. In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAV24Cxx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAV24Cxx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (tWR), the SDA output will be tri−stated and the CAV24Cxx will not respond to any request from the Master device (Figure 7). Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAV24Cxx initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAV24Cxx is still busy with the write operation, NoACK will be returned. If the CAV24Cxx has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Page Write The CAV24Cxx writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 8). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAV24Cxx will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all BUS ACTIVITY: MASTER S T A R T Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAV24Cxx. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAV24Cxx will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAV24Cxx is shipped erased, i.e., all bytes are FFh. SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 − a 0 d7 − d 0 S T O P P S SLAVE A C K A C K Figure 6. Byte Write Sequence http://onsemi.com 6 A C K CAV24C02, CAV24C04, CAV24C08, CAV24C16 SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: MASTER S T A R T DATA BYTE n ADDRESS BYTE SLAVE ADDRESS DATA BYTE n+1 S T O P DATA BYTE n+P S P A C K SLAVE n=1 P v 15 A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 9 a7 a0 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing http://onsemi.com 7 A C K CAV24C02, CAV24C04, CAV24C08, CAV24C16 READ OPERATIONS Immediate Read address of the location it wishes to read. After the CAV24Cxx acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAV24Cxx then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11). Upon receiving a Slave address with the R/W bit set to ‘1’, the CAV24Cxx will interpret this as a request for data residing at the current byte address in memory. The CAV24Cxx will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAV24Cxx returns to Standby mode. Sequential Read If during a Read session, the Master acknowledges the 1st data byte, then the CAV24Cxx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte BUS ACTIVITY: MASTER N O S T A R T S AT CO KP SLAVE ADDRESS P S A C K SLAVE SCL D ATA BYTE 8 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS S N O S AT CO KP SLAVE ADDRESS P S A C K SLAVE A C K A C K D ATA BYTE Figure 11. Selective Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE A C K D ATA BYTE n D ATA BYTE n+1 D ATA BYTE n+2 Figure 12. Sequential Read Sequence http://onsemi.com 8 D ATA BYTE n+x CAV24C02, CAV24C04, CAV24C08, CAV24C16 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL E1 E MIN MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 9 CAV24C02, CAV24C04, CAV24C08, CAV24C16 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.20 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 10 CAV24C02, CAV24C04, CAV24C08, CAV24C16 Example of Ordering Information CAV24C02/04/08/16 (Note 11) Prefix Device # CAV Suffix 24C16 W E −G T3 Temperature Range Lead Finish E = Automotive (−40°C to +125°C) G: NiPdAu Tape & Reel (Note 13) T: Tape & Reel 3: 3000 Units / Reel Company ID Product Number 24C02 24C04 24C08 24C16 Package W: SOIC, JEDEC Y: TSSOP 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. The device used in the above example is a CAV24C16WE−GT3 (SOIC, Automotive Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 12. For availability of other package options, please contact your nearest ON Semiconductor Sales Office. 13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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