CYPRESS CY6264

1CY 626 4
PRELIMINARY
CY6264
8K x 8 Static RAM
Features
over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. Both devices have an automatic power-down feature (CE1), reducing the power consumption by
An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
SOIC
Top View
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
I/O1
A1
A2
A3
A4
A5
A6
A7
A8
I/O2
I/O3
256 x 32 x 8
ARRAY
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
CY6264-2
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
I/O7
OE
CY6264-1
Selection Guide
CY6264-55
CY6264-70
Maximum Access Time (ns)
55
70
Maximum Operating Current (mA)
100
100
20/15
20/15
Maximum Standby Current (mA)
Shaded area contains advanced information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 1994 – Revised June 1996
PRELIMINARY
Maximum Ratings
CY6264
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ............................................ –0.5V to +7.0V
DC Input Voltage[1]......................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
6264-55
Parameter
Description
Test Conditions
Min.
2.4
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
6264-70
Max.
Min.
Unit
2.4
0.4
Voltage[1]
Max.
V
0.4
V
2.2
VCC
2.2
VCC
V
–0.5
0.8
–0.5
0.8
V
VIL
Input LOW
IIX
Input Load Current
GND < VI < VCC
–5
+5
–5
+5
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5
+5
–5
+5
µA
IOS
Output Short
Circuit Current[2]
VCC = Max.,
VOUT = GND
–300
–300
mA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA
100
100
mA
ISB1
Automatic CE1
Power–Down Current
Max. VCC, CE1 > VIH,
Min. Duty Cycle=100%
20
20
mA
ISB2
Automatic CE1
Power–Down Current
Max. VCC, CE1 > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
15
15
mA
Shaded area contains advanced information.
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Notes:
1. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R1 481Ω
5V
OUTPUT
R2
255Ω
(a)
ALL INPUT PULSES
3.0V
5 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
< 5 ns
(b)
CY6264-3
THÉVENIN EQUIVALENT
OUTPUT
167Ω
GND
10%
1.73V
2
90%
90%
10%
< 5 ns
CY6264-4
PRELIMINARY
CY6264
Switching Characteristics Over the Operating Range[4]
6264-55
Parameter
Description
Min.
6264-70
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
55
70
ns
tACE2
CE2 HIGH to Data Valid
40
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low Z
55
5
70
5
3
Z[5]
ns
ns
5
ns
tHZOE
OE HIGH to High
tLZCE1
CE1 LOW to Low Z[6]
5
5
ns
tLZCE2
CE2 HIGH to Low Z
3
5
ns
Z[5, 6]
tHZCE
CE1 HIGH to High
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
tPD
WRITE
20
ns
30
20
0
CE1 HIGH to Power-Down
30
0
25
ns
ns
ns
30
ns
CYCLE[7]
tWC
Write Cycle Time
50
70
ns
tSCE1
CE1 LOW to Write End
40
60
ns
tSCE2
CE2 HIGH to Write End
30
50
ns
tAW
Address Set-Up to Write End
40
55
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
25
40
ns
tSD
Data Set-Up to Write End
25
35
ns
tHD
Data Hold from Write End
0
0
ns
Z[5]
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z
20
5
30
5
ns
ns
Shaded area contains advanced information.
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/I OH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
7. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
PRELIMINARY
CY6264
Switching Waveforms
Read Cycle No.1[8, 9]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
CY6264-5
Read Cycle No. 2 [10, 11]
tRC
CE1
CE2
tACE
OE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
CY6264-6
Write Cycle No. 1 (WE Controlled)[9, 11]
tWC
ADDRESS
tSCE1
CE1
CE2
tSCE2
OE
tAW
WE
tHA
tSA
tPWE
tSD
DATAIN VALID
DATA IN
tHZWE
DATA I/O
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
CY6264-7
Notes:
8. Device is continuously selected. OE, CE = V IL. CE 2 = VIH.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = V IH, or WE = V IL.
4
PRELIMINARY
CY6264
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled) [9, 11, 12]
tWC
ADDRESS
CE1
tSCE1
tSA
tSCE2
CE2
tAW
tHA
tPWE
WE
tSD
tHD
DATAIN VALID
DATA IN
tHZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
CY6264-8
Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.4
1.2
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.0
1.0
100
ICC
ICC
120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.8
80
0.6
60
0.8
0.6
0.4
0.4
0.0
4.0
4.5
5.0
5.5
6.0
40
VCC =5.0V
VIN =5.0V
0.2
ISB
0.2
20
ISB
0.0
−55
25
125
0
0.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.4
1.6
1.3
1.4
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
1.2
1.2
TA =25°C
60
1.0
VCC =5.0V
1.0
40
0.8
0.9
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
6.0
0.6
−55
VCC =5.0V
TA =25°C
80
1.1
0.8
4.0
VCC =5.0V
TA =25°C
20
25
125
AMBIENT TEMPERATURE (°C)
5
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
PRELIMINARY
CY6264
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
2.5
25.0
2.0
20.0
1.5
15.0
1.0
10.0
0.5
5.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0.0
VCC =5.0V
TA =25°C
VCC =0.5V
1.00
VCC =4.5V
TA =25°C
0
200
SUPPLY VOLTAGE(V)
400
600
800 1000
CAPACITANCE(pF)
Truth Table
CE1
CE2
WE
OE
Input/Output
H
X
X
X
High Z
Deselect/Power-Down
X
L
X
X
High Z
Deselect
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
High Z
Deselect
Mode
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
2
A5
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Y1
7
A10
Y4
8
A11
Y3
9
A12
Y0
10
A0
Y2
21
A1
X0
23
A2
X1
24
A3
X2
25
NORMALIZED ICC vs. CYCLE TIME
1.25
6
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
PRELIMINARY
CY6264
Ordering Information
Speed
(ns)
55
Ordering Code
CY6264-55SC
Package
Name
Package Type
Operating
Range
S23
28-Lead 330-Mil SOIC[13]
Commercial
[13]
Commercial
70
CY6264-70SC
S23
28-Lead 330-Mil SOIC
55
CY6264-55SNC
S22
28-Lead 300-Mil SOIC
Commercial
70
CY6264-70SNC
S22
28-Lead 300-Mil SOIC
Commercial
Shaded area contains advanced information.
Note:
13. Not recommended for new designs.
Document #: 38-00425-A
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
7
PRELIMINARY
CY6264
Package Diagrams (continued)
28-Lead (330-Mil) SOIC S23
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.