APW7067N Synchronous Buck PWM and Linear Controller Features General Description • Provided Two Regulated Voltages - Synchronous Buck Converter - Linear Regulator • Single 12V Power Supply Required • Excellent Both Output Voltage Regulation - 0.8V Internal Reference - ±1% Over Line Voltage and Temperature The APW7067N integrates synchronous buck PWM and linear controller, as well as monitoring and protection functions into a single package. The synchronous PWM controller drives dual N-channel MOSFETs, which provides one controlled power output with under-voltage and overcurrent protections. Linear controller drives an external N-channel MOSFET with under-voltage protection. • Integrated Soft-Start for PWM and Linear Outputs • Programmable Frequency Range from 150kHz to 1000kHz • Voltage Mode PWM Control Design and Up to 89% (Typ.) Duty Cycle • Under-Voltage Protection for PWM and Linear Output • Over-Current Protection for PWM Output - Sense Low-Side MOSFET’s RDS(ON) • SOP-14, QSOP-16 and QFN4x4-16 packages • Lead Free and Green Devices Available The APW7067N provides excellent regulation for output load variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. The switching frequency is adjustable from 150kHz to 1000kHz. The APW7067N with excellent protection functions: POR, OCP and UVP. The Power-On-Reset (POR) circuit can monitor VCC12 supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides both outputs with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the lower MOSFET’s R DS(ON), comparing with internal VOCP (0.25V), eliminating the need for a current sensing resister. When the output current reaches the trip point, the controller will shutdown the IC directly, and latch the converter’s output. The Under-Voltage Protection (UVP) monitors the voltages of FB and FBL pins for shortcircuit protection. When the VFB or VFBL is less than 50% of VREF, the controller will shutdown the IC directly. (RoHS Compliant) Typical Application Circuit 12V VIN1 Applications VIN2 Q1 Q3 L PWM Linear Controller Controller VOUT2 • VOUT1 Graphic Cards Q2 RFS_DIS ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 1 www.anpec.com.tw APW7067N Ordering and Marking Information APW7067N Package Code K : SOP - 14 M : QSOP - 16 QA : QFN4x4 - 16 Temp. Range E : -20 to 70 °C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device Assembly Material Handling Code Temp. Range Package Code APW7067N XXXXX APW7067N K : XXXXX - Date Code APW7067N APW7067N M : XXXXX - Date Code XXXXX APW7067N QA : XXXXX - Date Code APW7067N XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). BOOT 1 16 UGATE FS_DIS 2 13 PHASE FS_DIS 2 15 PHASE COMP 3 12 PGND COMP 3 14 PGND FB 4 11 LGATE FB 4 13 LGATE DRIVE 5 10 NC DRIVE 5 12 NC FBL 6 9 NC FBL 6 11 NC GND 7 8 VCC12 GND 7 10 VCC12 GND 8 9 COMP 1 FB 2 DRIVE 3 FBL 4 PHASE 14 UGATE UGATE 1 BOOT BOOT FS_DIS Pin Configuration 16 15 14 13 12 PGND Absolute Maximum Ratings (Note 1) Symbol 6 7 8 DGND VCC12 VCC12 QFN4x4-16 TOP VIEW Rating Unit VCC12 VCC12 to GND -0.3 to +16 V VBOOT BOOT to PHASE -0.3 to +16 V VUGATE VLGATE VPHASE Parameter NC 9 AGND QSOP-16 TOP VIEW 10 NC VCC12 5 SOP-14 TOP VIEW 11 LGATE Metal GND Pad (Bottom) UGATE to PHASE <400ns pulse width -5 to VBOOT +5 >400ns pulse width LGATE to PGND PHASE to GND Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 -0.3 to VBOOT +0.3 <400ns pulse width -5 to VCC12+5 >400ns pulse width -0.3 to VCC12+0.3 <200ns pulse width -10 to +30 >200ns pulse width -0.3 to 16 2 V V V www.anpec.com.tw APW7067N Absolute Maximum Ratings (Cont.) Symbol VDRIVE Parameter VFB, VFBL, VCOMP, VFS_DIS FB, FBL, COMP, FS_DIS to GND VPGND TJ Rating Unit 12 V -0.3 to 7 V DRIVE to GND PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to +150 °C -65 ~ 150 °C 260 °C TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol Parameter Rating Unit VCC12 IC Supply Voltage 10.8 to 13.2 V VIN1 Converter Input Voltage 2.9 to 13.2 V VOUT1 Converter Output Voltage 0.9 to 5 V IOUT1 Converter Output Current 0 to 30 A IOUT2 Linear Output Current 0 to 3 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APW7067N Min Typ Max Unit INPUT SUPPLY CURRENT ICC12 VCC12 Supply Current (Shutdown mode) UGATE, LGATE and DRIVE open; FS_DIS = GND 4 6 mA VCC12 Supply Current UGATE, LGATE and DRIVE open; FOSC = 600kHz 16 24 mA POWER-ON RESET Rising VCC12 Threshold 7.7 7.9 8.1 V Falling VCC12 Threshold 7.2 7.4 7.6 V OSCILLATOR +15 % FOSC Accuracy Oscillator Frequency RFS_DIS = 110k ohms 255 -15 300 345 kHz 510 600 690 kHz FOSC Oscillator Frequency RFS_DIS = 47k ohms VOSC Ramp Amplitude (nominal 1.2V to 2.7V) (Note 2) Duty Maximum Duty Cycle 1.5 V 89 % REFERENCE VREF Reference Voltage for Error Amp1 and Amp2 Reference Voltage Tolerance 0.792 -1 0.80 0.808 V +1 % PWM Load Regulation IOUT1 = 0 to 10A 1 % Linear Load Regulation IOUT2 = 0 to 3A 1 % Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 3 www.anpec.com.tw Note 4: Refer to the typical application circuits APW7067N Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APW7067N Min Typ Max Unit PWM ERROR AMPLIFIER Gain GBWP SR Open Loop Gain RL = 10k, CL = 10pF (Note 2) 93 dB Open Loop Bandwidth RL = 10k, CL = 10pF (Note 2) 20 MHz Slew Rate RL = 10k, CL = 10pF (Note 2) FB Input Current VFB = 0.8V 8 V/µs 0.1 1 µA VCOMP COMP High Voltage 5 V VCOMP COMP Low Voltage 0 V ICOMP COMP Source Current VCOMP = 2V 12 mA ICOMP COMP Sink Current VCOMP = 2V 12 mA VBOOT = 12V, VUGATE - VPHASE = 2V 2.5 A 2 A 2.5 A 3.5 A GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE Lower Gate Source Current ILGATE Lower Gate Sink Current RUGATE Upper Gate Source Impedance VBOOT = 12V, IUGATE = 0.1A 2.25 3.375 Ω RUGATE Upper Gate Sink Impedance VBOOT = 12V, IUGATE = 0.1A 0.7 1.05 Ω RLGATE Lower Gate Source Impedance VCC12 = 12V, ILGATE = 0.1A 2.25 3.375 Ω RLGATE Lower Gate Sink Impedance VCC12 = 12V, ILGATE = 0.1A 0.4 0.6 Ω TD VCC12 = 12V, VLGATE = 2V Dead Time 20 ns LINEAR REGULATOR Gain GBWP SR Open Loop Gain RL = 10k, CL = 10pF (Note 2) 70 dB Open Loop Bandwidth RL = 10k, CL = 10pF (Note 2) 19 MHz Slew Rate RL = 10k, CL = 10pF (Note 2) FBL Input Current VFBL= 0.8V 6 V/µs 0.1 1 µA VDRIVE DRIVE High Voltage 10 V VDRIVE DRIVE Low Voltage 0 V IDRIVE DRIVE Source Current VDRIVE = 5V 4 mA IDRIVE DRIVE Sink Current VDRIVE = 5V 3 mA PROTECTION VFB-UV FB Under Voltage Protection Trip Point Percent of VREF 50 % VFBL-UV FBL Under Voltage Protection Trip Point Percent of VREF 50 % VOCP OCP Voltage 230 250 270 mV SOFT START TSS Internal Soft-Start Interval (Note 3) FOSC = 600kHz 2.1 ms FOSC = 300kHz 4.2 ms Note 2: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 4 www.anpec.com.tw APW7067N Typical Operating Characteristics UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 3.5 VBOOT =12V VPHASE=0V 2.5 VBOOT =12V VPHASE=0V 3 UGATE Sink Current (A) UGATE Source Current (A) 3 2 1.5 1 0.5 2.5 2 1.5 1 0.5 0 0 0 2 4 6 8 10 0 12 0.5 1 UGATE Voltage (V) LGATE Source Current vs. LGATE Voltage 2 2.5 3 LGATE Sink Current vs. LGATE Voltage 7 3 VCC12=12V VCC12=12V 6 2.5 LGATE Sink Current (A) LGATE Source Current (A) 1.5 UGATE Voltage (V) 2 1.5 1 0.5 5 4 3 2 1 0 0 0 2 4 6 8 10 0 12 LGATE Voltage (V) 1 2 3 4 LGATE Voltage(V) VREF vs. Junction Temperature 0.804 Reference Voltage(V) 0.8035 0.803 0.8025 VREF 0.802 0.8015 0.801 0.8005 -40 -20 0 20 40 60 80 100 120 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 5 www.anpec.com.tw APW7067N Operating Waveforms Power On Power Off VCC12=12V, VIN1=12V,VIN2=3.3V VOUT 1=1.2V,VOUT 2=2.5V L=1uH VCC12=12V, VIN1=12V,VIN2=3.3V VOUT1=1.2V,VOUT2=2.5V L=1uH 1 1 2 2 3 3 CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VOUT2 (2V/div) Time: 5ms/div CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VOUT2 (2V/div) Time: 5ms/div EN Shutdown VCC12 =12V, L=1uH, VIN1 =12V, VIN2 =3.3V VOUT1 =1.2V, VOUT2=2.5V VCC12 =12V, L=1uH, VIN1 =12V, VIN2 =3.3V VOUT1 =1.2V, VOUT2=2.5V 1 1 2 2 3 3 4 4 CH1: VFS_DIS (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT1 (1V/div) CH4: VOUT2 (2V/div) CH1: VFS_DIS (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT1 (1V/div) CH4: VOUT2 (2V/div) Time: 5ms/div Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 6 www.anpec.com.tw APW7067N Operating Waveforms (Cont.) UGATE Rising UGATE Falling VCC12=12V, VIN1=12V VOUT1=1.2V VCC12=12V, VIN1=12V VOUT1=1.2V 1 1 2 2 3 3 CH1: VUGATE (20V/div) CH2: VPHASE (10V/div) CH3: VLGATE (10V/div) Time: 50ns/div CH1: VUGATE (20V/div) CH2: VPHASE (10V/div) CH3: VLGATE (10V/div) Time: 50ns/div UVP_PWM Controller (VFB< 0.4V) UVP_Linear Regulator (VFBL< 0.4V) VCC12=12V, VIN1 =12V VOUT 1=1.2V, L=1uH, I OUT1=10A VCC12=12V, VIN2 =12V VOUT 2=1.2V, I OUT 2=10A 1 1 2 2 3 4 3 CH1: VFB (1V/div) CH2: VOUT1 (1V/div) CH3: VUGATE (20V/div) CH4: VCOMP (5V/div) Time: 50µs/div Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 CH1: VFBL (1V/div) CH2: VDRIVE (5V/div) CH3: VOUT2 (2V/div) Time: 100µs/div 7 www.anpec.com.tw APW7067N Operating Waveforms (Cont.) Load Transient Response (PWM Controller) - VCC12=12V, VIN1=12V, VOUT1=2V, FOSC=300kHz - IOUT1 slew rate=±10 A/µs IOUT1=0Aà10A IOUT1=0Aà10Aà0A IOUT1=10Aà0A 1 1 1 2 2 2 3 3 3 CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1 (10A/div) Time: 20µs/div CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1(10A/div) Time: 50µs/div CH1: VOUT1 (100mV/div,AC) CH2: VUGATE (20V/div) CH3: IOUT1(10A/div) Time: 20µs/div Load Transient Response (Linear Regulator) - VCC12=12V, VIN2=3.3V, VOUT2=2.5V - IOUT2 slew rate=±3A/µs IOUT2=0Aà3A IOUT2=0Aà3Aà0A 1 1 2 2 IOUT2=3Aà0A 1 CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 1µs/div Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 2 CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 10µs/div 8 CH1: VOUT2 (100mV/div,AC) CH2: IOUT2 (2A/div) Time: 1µs/div www.anpec.com.tw APW7067N Operating Waveforms (Cont.) Over Current Protection Short Test after Power Ready 1 1 2 2 3 3 4 4 CH1: VOUT1 (1V/div) CH2: VDRIVE (5V/div) CH3: VUGATE (20V/div) CH4: IL (10A/div) Time: 50µs/div CH1: VOUT1 (1V/div) CH2: VDRIVE (5V/div) CH3: VUGATE (20V/div) CH4: IL (10A/div) Time: 50µs/div Short Test before Power On 1 2 3 4 CH1: VCC12 (10V/div) CH2: VOUT1 (1V/div) CH3: VUGATE (20V/div) CH4: IL (10A/div) Time: 2ms/div Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 9 www.anpec.com.tw APW7067N Function Pin Description VCC12 DRIVE Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. This pin drives the gate of an external N-channel MOSFET for linear regulator. It is also used to set the compensation for some specific applications, for example, with low values of output capacitance and ESR. BOOT This pin is the inverting input of the linear regulator error amplifier. It is used to set the output voltage. This pin is also monitored for under-voltage protection, when the F BL voltage is under 50% of reference voltage (0.4V), both outputs will be shutdown immediately. FBL This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal diode, and the power supply valtage VCC12, generates the bootstrap voltage for the upper gate diver (UGATE). FS_DIS PHASE This pin be allowed to adjust the switching frequency. Connect a resistor from FS_DIS pin to the ground to increase the switching frequency. This pin also provides shutdown function, use an open drain logic signal to pull this pin low to disable both outputs, leave open to enable both outputs. This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the lower MOSFET for over-current protection. GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection, when the FB voltage is under 50% of reference voltage (0.4V), both outputs will be shut - downed immediately. UGATE This pin is the gate driver for the upper MOSFET of PWM output. LGATE This pin is the gate driver for the lower MOSFET of PWM output. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 10 www.anpec.com.tw APW7067N Block Diagram VCC12 Power-OnReset Regulator BOOT GND Sense Low Side UGATE VREF (0.8V) 10V O.C.P Comparator U.V.P Comparator 50%VREF :2 PHASE Soft Start and Fault Logic VOCP 0.25V Gate Control LGATE PGND Error Amp 1 PWM Comparator U.V.P Comparator FBL 10V :2 50%VREF VREF DRIVE Oscillator VREF FS_DIS COMP FB Sawtooth wave Error Amp 2 Typical Application Circuits C1 2.2nF VIN1 Q3 ON/OFF CIN1 2N7002 R2 C2 3.9K 0.01uF VOUT1 Q1 APM2509 R1 1.5K R3 22Ω VOUT1 L C4 1uH 0.1uF 1.2V C3 22nF 1 BOOT UGATE 14 FS_DIS PHASE 13 12V 470uFx2 RFS_DIS VIN2 3.3V 2 RGND1 3K COUT1 470uFx2 PGND 12 LGATE 11 DRIVE NC 10 6 FBL NC 9 7 GND VCC12 8 3 COMP 4 FB 5 Q2 CIN2 470uF Q4 APM3055 C5 R5 C6 2.2nF APM2506 12V R6 2.2Ω R7 2.2Ω R4 VOUT2 APW7067N 2.5K 2.5V COUT2 470uF RGND2 C7 1uF 1.17K * C5, R5 for specific application Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 11 www.anpec.com.tw APW7067N Function Description Power-On-Reset (POR) Voltage(V) VFB The Power-On-Reset (POR) function of APW7067N continually monitors the input supply voltage (V CC12), ensures the supply voltage exceed its rising POR VFBL threshold voltage. The POR function initiates soft-start interval operation while VCC12 voltage exceeds its POR 20mV 32/FOSC threshold and inhibits operation under disabled status. 32/FOSC Soft-Start 20mV Figure 1. shows the soft-start interval. When VCC12 reaches the rising POR threshold voltage, the internal reference voltage is controlled to follow a voltage proportional to the t3 Time t4 Figure 2. The Controlled Stepped FB and FBL Voltage during Soft-Start soft-start voltage. The soft-start interval is variable by the oscillator frequency. The formulation is given by: 1 TSS = ∆( t 2 − t1) = × 1280 FOSC Figure 2. shows more detail of the FB and FBL voltage Over-Current Protection The over-current protection monitors the output current by using the voltage drop across the lower MOSFET’s ramps. The FB and FBL voltage soft-start ramps are formed with many small steps of voltage. The voltage of RDS(ON) and this voltage drop will be compared with the internal 0.25V reference voltage. When the voltage drop one step is about 20mV in VFB and VFBL, and the period of one step is about 32/FOSC. This method provides a across the lower MOSFET’s RDS(ON) is larger than 0.25V, an over-current condition is detected, the controller will controlled voltage rise and prevents the large peak current to charge the output capacitors. The FB voltage shutdown the IC directly, and latch the converter's output. compares the FBL voltage to shift to an earlier time the establishment as Figure2. The voltage estabilishment The threshold of the over current limit is given by: VOCP (0.25V) ILIMIT = RDS(ON) (Low _ Side ) time difference for V FB and V FBL is variable by the oscillator. The formulation is given by: 1 1 ∆( t 4 − t 3 ) = × 320 = × TSS FOSC 4 For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. Voltage (V) - The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should determine the maximum RDS(ON) in manufacture’s datasheet. - The minimum V OCP should be used in the above equation. - Note that the ILIMIT is the current flow through the lower MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. VCC12 POR Under Voltage Protection VOUT1 VOUT2 t0 t1 t2 The FB and FBL pin are monitored during converter operation by their own Under Voltage (UV) comparator. If the FB or FBL voltage drop below 50% of the reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side Time Figure 1. Soft-Start Interval Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 12 www.anpec.com.tw APW7067N Function Description (Cont.) Under Voltage Protection (Cont.) and low-side MOSFET and the converter’s output is latched to be floating. 1200 Shutdown and Enable 1000 FOSC (KHz) Pulling the FS_DIS voltage to GND by an open drain transistor, shown in typical application circuit, shutdown the APW7067N PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. 800 600 Switching Frequency The APW7067N provides the adjustable oscillator switching frequency . The switching frequency is determined 400 0 10 20 30 40 50 60 70 80 R (KΩ ) by the value of RFS_DIS (from FS_DIS pin to GND), the adjustable range from150kHz to 1000kHz . Figure 4. Oscillator Frequency vs.R FS-DIS (High Frequency) Figure 3. shows how to select the resistor for the desired frequency. If the IC is operated in higher frequencies (ex. 600 kHz or above), the slope of the 500 450 curve is steep, and a small change in resistance will have a big effect on the frequency. At lower frequencies, 400 FOSC (KHz) the slope of the curve is much less steep, even a large change in resistor value doesn’t change the frequency too much. Figure 4. shows more detail for the higher frequency and Figure5. shows the lower frequency. 300 250 200 1600 150 1400 100 1200 FOSC (KHz) 350 50 150 250 350 450 550 650 750 R (KΩ ) 1000 Figure 5. Oscillator Frequency vs.R FS-DIS (Low Frequency) 800 600 400 200 0 0 100 200 300 400 500 600 700 800 R (KΩ ) Figure 3. Oscillator Frequency vs. R FS-DIS Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 13 www.anpec.com.tw APW7067N Application Information Output Voltage Selection In some applications, heatsink might be required to help maintain the junction temperature of the MOSFET below The output voltage of PWM converter can be programmed with a resistive divider. Use 1% or better resistors for the its maximum rating. resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference Linear Regulator Compensation Selection The linear regulator is stable over all loads current. voltage is 0.8V. The output voltage is determined by: R1 VOUT1 = 0.8 × 1 + R GND1 However, the transient response can be further enhanced by connecting a RC network between the FBL and DRIVE Where R1 is the resistor connected from VOUT1 to FB and pin. Depending on the output capacitance and load current of the application, the value of this RC network is RGND1 is the resistor connected from FB to GND. then varied. The linear regulator output voltage VOUT2 is also set by means of an external resistor divider. The FBL pin is the PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: VOUT2 slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB and V OUT1 R4 = 0.8 × 1 + R GND2 should be added. The compensation network is shown in Fig. 9. The output LC filter consists of the output Where R4 is the resistor connected from VOUT2 to FBL inductor and output capacitors. The transfer function of the LC filter is given by: and RGND2 is the resistor connected from FBL to GND. Linear Regulator Input/Output Capacitor Selection GAINLC = The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor 1 + s × ESR × COUT1 s2 × L × COUT1 + s × ESR × COUT1 + 1 The poles and zero of this transfer functions are: will momentarily supply the required transient current. The output capacitor for the linear regulator is chosen to FLC = minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage 1 2 × π × L × COUT1 FESR = rating. Linear Regulator Input/Output MOSFET Selection 1 2 × π × ESR × COUT1 The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. The maximum DRIVE voltage is about 10V when VCC12 is equal 12V. Since this pin drives an external N-channel VPHASE MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the VGS. L VOUT1 COUT1 VOUT2MAX = 10 - VGS Another criterion is its efficiency of heat removal. The power dissipated by the MOSFET is given by: ESR PD = IOUT2 x (VIN2 – V OUT2) Figure 6. The Output LC Filter Where IOUT2 is the maximum load current, VOUT2 is the nominal output voltage. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 14 www.anpec.com.tw APW7067N Application Information (Cont.) The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 PWM Compensation (Cont.) FLC 1 2 × π × (R1+ R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 1 FP2 = 2 × π × R3 × C3 FZ2 = GAIN (dB) -40dB/dec FESR C1 -20dB/dec R3 C3 R2 C2 VOUT1 Frequency(Hz) R1 Figure 7. The LC Filter GAIN and Frequency Figure 9. Compensation Network the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given The closed loop gain of the converter can be written as: by: GAINLC X GAINPWM X GAINAMP VIN = ∆VOSC Figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below VIN1 Driver guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade OSC ΔVOSC VCOMP VREF The PWM modulator is shown in Figure 8. The input is GAINPWM FB PWM Comparator slope and a phase margin greater than 45 degree. PHASE Output of Error Amplifier 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Driver Use the following equation to calculate R2: ∆VOSC FO R2 = × × R1 VIN FLC Figure 8. The PWM Modulator The compensation network is shown in Figure 9. It provides a close loop transfer function with the highest 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: FZ1 = 0.75 X FLC Calculate the C2 by the equation: 1 C2 = 2 × π × R2 × FLC × 0.75 1 1 // R2 + VCOMP sC1 sC2 GAINAMP = = 1 VOUT1 R1// R3 + sC3 1 1 s + ×s + R2 × C2 ( R1 + R3) × C3 R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 C1 C2 R3 C3 × × × Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 4. Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C2 C1 = 2 × π × R2 × C2 × FESR − 1 15 www.anpec.com.tw APW7067N Application Information (Cont.) PWM Compensation (Cont.) 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the exist between the inductor’s ripple current and the regulator load transient response time. compensation gain at FP2 with the capabilities of the error amplifier. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the FP2 = 0.5 X FS FZ2 = FLC ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation Combine the two equations will get the following component calculations: R1 R3 = FS −1 2 × FLC C3 = of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value 1 π × R3 × FS FZ1 FZ2 has been chosen, select an inductor that is capable of carrying the required peak current without going into FP1 saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase FP2 GAIN (dB) abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the FLC FESR Converter Gain desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, PWM & Filter Gain and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make Frequency(Hz) Figure 10. Converter Gain and Frequency Output Inductor Selection sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum voltage can be approximated by: IRIPPLE = VIN1 − VOUT1 VOUT1 × FS × L VIN1 RMS current rating requirement is approximately IOUT1/2, where IOUT1 is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge ∆VOUT1 = IRIPPLE × ESR Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 16 www.anpec.com.tw APW7067N Application Information (Cont.) Input Capacitor Selection (Cont.) tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can be connected between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: 2 PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS 2 PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D) Where IOUT1 is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW, is a function of the reverse transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 17 www.anpec.com.tw APW7067N Layout Consideration In any high switching frequency converter, a correct - The input capacitor should be near the drain of the layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz or upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close above, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic to the output capacitor GND and the lower MOSFET GND. circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the - The drain of the MOSFETs (VIN1 and PHASE nodes) should be a large plane for heat sinking. MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling APW7067N by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike VIN1 VCC12 during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting VIN2 BOOT impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate DRIVE VOUT2 till combined using ground plane construction or single point grounding. Figure 11. illustrates the layout, with bold L O A D lines indicating high current paths; these traces must be short and wide. Components along the bold lines should FBL L O A D UGATE PHASE LGATE VOUT1 Figure 11. Layout Guidelines be placed lose together. Below is a checklist for your layout: - The metal plate of the bottom of the packages (QFN-16) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG, DRIVE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers and boot capacitors should be close their pins. ( F o r e x a m p l e , p l a c e t h e decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 18 www.anpec.com.tw APW7067N Package Information SOP – 14 D E E1 SEE VIEW A h X 45 ° e c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 b L VIEW A S Y M B O L SOP-14 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° e 0.049 1.27 BSC 0.050 BSC 8° Note: 1. Follow JEDEC MS-012 AB. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 19 www.anpec.com.tw APW7067N Package Information QSOP-16 D h X 45 E E1 SEE VIEW A c A 0.25 b A2 A1 GAUGE PLANE SEATING PLANE L 0 e VIEW A S Y M B O L QSOP-16 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.24 b 0.20 0.30 0.008 0.012 c 0.15 0.25 0.006 0.010 0.049 D 4.90 BSC 0.193 BSC E 5.99 BSC 0.236 BSC E1 3.91 BSC 0.154 BSC e 0.635 BSC 0.025 BSC L 0.40 1.27 0.016 h 0.25 0.50 0.010 0.020 0 0° 8° 0° 8° Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 20 0.050 www.anpec.com.tw APW7067N Package Information QFN4x4 - 16 D b E A D2 A1 A3 L E2 Pin 1 Corner e QFN4*4-16 S Y M B O L MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 0.00 0.05 0.000 0.002 0.35 0.010 A1 MILLIMETERS A3 b 0.20 REF 0.25 D D2 2.50 0.098 2.80 2.50 Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 0.110 0.157 BSC 2.80 0.098 0.50 0.012 0.65 BSC 0.30 0.014 0.157 BSC 4.00 BSC e L 0.008 REF 4.00 BSC E E2 INCHES 0.110 0.026 BSC 21 0.020 www.anpec.com.tw APW7067N Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-14 Application QSOP- 16 Application QFN4x4-16 330.0± 2.00 A H 50 MIN. P0 P1 T1 16.4+2.00 -0.00 P2 4.0± 0.10 8.0± 0.10 2.0± 0.05 A H T1 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 330 ± 1 62 +1.5 12.75+ 0.15 P0 P1 5.5± 1 D W E1 F 1.5 MIN. 20.2 MIN. 16.0± 0.30 1.75± 0.10 7.50± 0.05 D1 A0 B0 K0 6.40± 0.20 9.00± 0.20 2.10± 0.20 d T 0.6+0.00 -0.40 D W E1 F 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 P2 D0 D1 T A0 B0 K0 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013 T1 12.4+2.00 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 A H 330.0± 2.00 50 MIN. P0 P1 P2 4.0± 0.10 8.0± 0.10 2.0± 0.10 d 1.5 MIN. d D W E1 F 1.5 MIN. 20.2 MIN. 12.0± 0.30 1.75± 0.10 5.5± 0.10 D1 T 0.6+0.00 -0.40 A0 B0 K0 4.35± 0.20 4.35± 0.20 1.1± 0.20 1.5 MIN. (mm) Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 22 www.anpec.com.tw APW7067N Devices Per Unit Package Type SOP- 14 QSOP- 16 QFN4x4-16 Reflow Condition Unit Tape & Reel Tape & Reel Tape & Reel Quantity 2500 2500 3000 (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 23 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APW7067N Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness <2.5 mm ≥2.5 mm Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Volume mm <350 240 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Mar., 2008 24 www.anpec.com.tw