TS52001 Version 1.3 High Efficiency Li-Ion Battery Charger for Photovoltaic Sources DESCRIPTION FEATURES The TS52001 is a DC/DC synchronous switching Liion Battery Charger with fully integrated power switches, internal compensation, and full fault protection. The TS52001 utilizes a temperatureindependent photovoltaic Maximum Power Point Tracking (MPPT-Lite™) calculator to optimize power output from the source during Full Charge ConstantCurrent (CC) mode. The switching frequency of 1MHz enables the use of small filter components, resulting in smaller board space and reduced BOM costs. Utilizes a temperature-independent PV MPPT-Lite™ regulation scheme VBAT reverse current blocking Programmable temperature-compensated termination voltage with +/- 1% tolerance Up to 1.5A of continuous output current in Full Charge Constant-Current (CC) mode User programmable charging current High efficiency – up to 92% at typical load Current mode PWM control in constant voltage Supervisor for VBAT reported at the nFLT pin Input supply under-voltage lockout Full protection for VBAT over-current, over-temp, over-voltage, and charging timeout Charge status indication I2C program interface with EEPROM registers In Full Charge Constant-Current mode the duty cycle is controlled by the MPPT-Lite™ regulator. Once termination voltage is reached, the regulator operates in voltage mode. When the regulator is disabled (EN is low), the device draws 10uA quiescent current. The TS52001 includes supervisory reporting through the nFLT (Inverted Fault) open drain output to interface other components in the system. Device programming is achieved by an I²C interface through SCL and SDA pins. SUMMARY SPECIFICATIONS Wide input voltage range: 4.0V to 8.1V Packaged in a 16pin QFN (4x4) APPLICATIONS Portable solar chargers Off-grid systems Wireless sensor networks Smoke detectors HVAC controls TYPICAL APPLICATION Photovoltaic Cells VIN VTH_REF RREF CIN VTHERM GND CVdd LOUT VDD RSENSE COUT TS52001 VDD RPULLUP (optional) Battery SW SCL VSENSE SDA VBAT nFLT PG EN RTHM VDD RPULLUP (optional) PGND Specifications subject to change WWW.TRIUNESYSTEMS.COM -1- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 PINOUT SDA SW PGND PGND SW SCL VIN VIN TS52001 TS5201 QFN16 4x4 Top/Symbolization View VSENSE VTH_REF VBAT VTHERM VDD nFLT EN GND Figure 1b: Package Pinout Diagram PIN DESCRIPTION Pin Symbol SW Pin # 1 Function Switching Voltage Node Description Connected to 4.7uH (typical) inductor VIN 2 Photovoltaic Input Voltage Input voltage VSENSE 3 Current Sense Positive Input Positive input for the MPP current loop. VBAT 4 Battery Input Regulator Feedback Input GND 5 GND Primary ground for the majority of the device except the low-side power FET. EN 6 Enable Input Above 2.2V the device is enabled. GND the pin to disable the device. Includes internal pull-up. nFLT 7 Inverted Fault Open-drain output. VDD 8 Internal 3.3V Supply Output Connected to 100nF capacitor to GND VTHERM 9 Battery Temperature Sensor Minus Node Minus node for the thermistor which is located in close proximity to the battery. VTH_REF 10 Battery Temperature Sensor Positive Node Positive node for the thermistor which is located in close proximity to the battery VIN 11 Photovoltaic Input Voltage Input voltage SCL 12 Clock Input I2C clock input. SDA 13 Data Input/Output I2C data open-drain output. SW 14 Switching Voltage Node Connected to 4.7uH (typical) inductor PGND 15 Power GND GND supply for internal low-side FET/integrated diode PGND 16 Power GND GND supply for internal low-side FET/integrated diode Specifications subject to change WWW.TRIUNESYSTEMS.COM -2- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 FUNCTIONAL BLOCK DIAGRAM EN CIN nFLT Photovoltaic Cells VIN VIN VIN I²C Interface MONITOR & CONTROL SCL SDA ~5V @ 450mA Over Voltage Protection Oscillator VBAT VTH_REF Ramp Generator BATT Current Control RREF BATT Thermal Control VTHERM VBAT VIN Gate Drive Compensation Network LOUT RSENSE RTHM Comparator Error Amp SW BATT Gate Drive Control COUT Gate Drive Backgate Blocking Vref PGND VIN VDD Regulator MPP & Current Control VSENSE VBAT VDD CVDD GND Figure 2: TS52001 Block Diagram Specifications subject to change WWW.TRIUNESYSTEMS.COM -3- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 ABSOLUTE MAXIMUM RATINGS Over operating free–air temperature range unless otherwise noted(1,2,3) Parameter Range Unit -0.3 to 8.8 V SW -1 to 8.8 V VDD -0.3 to 3.6 V Operating Junction Temperature Range, TJ -40 to 125 C Storage Temperature Range, TSTG -65 to 150 C ±2k V +/-200 V 260 C VIN, EN, nFLT, SCL, SDA, VTHERM, VTH_REF, VBAT, VSENSE Electrostatic Discharge – Human Body Model Electrostatic Discharge – Machine Model Lead Temperature (soldering, 10 seconds) (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL CHARACTERISTICS Symbol Parameter Value Unit JA Thermal Resistance Junction to Air (Note 1) 50 °C/W Note 1: Assumes 4x4 QFN-16 in 1 in2 area of 2 oz copper and 25C ambient temperature. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit VIN Photovoltaic Input Operating Voltage 4 8.1 V RSENSE Sense Resistor 50 m LOUT Output Filter Inductor Typical Value (Note 1) 4.7 uH COUT Output Filter Capacitor Typical Value (Note 2) 4.7 uF COUT-ESR Output Filter Capacitor ESR CIN Input Supply Bypass Capacitor Value (Note 3) 3.3 10 CVDD VDD Supply Bypass Capacitor Value (Note 2) 70 100 TA Operating Free Air Temperature TJ Operating Junction Temperature 100 m uF 130 nF -40 85 C -40 125 C Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VBAT load requirement plus the inductor current ripple. Note 2: For best performance, a low ESR ceramic capacitor should be used. Note 3: For best performance, a low ESR ceramic capacitor should be used. If CIN is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should be added in parallel to CIN. Specifications subject to change WWW.TRIUNESYSTEMS.COM -4- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CHARACTERISTICS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Condition VIN Supply Voltage VIN Photovoltaic Voltage Input Quiescent current ICC-NORM ILOAD = 0A, no switching Normal Mode Quiescent current ICC-DISABLE EN = 0V Disable Mode VBAT Leakage IBAT-LEAK Leakage Current From Batt EN = 0V, VBAT = 4.1V IBAT-BACK Reverse Current VBAT > VIN, VBAT = 4.1V, Tj < 85C VIN Under-Voltage Lockout Input Supply Under-Voltage VIN-UV VIN Increasing Threshold Input Supply Under-Voltage VIN-UV_HYST Threshold Hysteresis OSC FOSC Oscillator Frequency nFLT Open Drain Output IOH-nFLT High-Level Output Leakage VnFLT = 5.3V VOL-nFLT Low-Level Output Voltage InFLT = -1mA EN/SCL/SDA Input Voltage Thresholds VIH High Level Input Voltage VIL Low Level Input Voltage VHYST Input Hysteresis VEN=VIN IIN-EN Input Leakage VEN=0V VSCL=VIN IIN-SCL Input Leakage VSCL=0V VSDA=VIN IIN-SDA Input Leakage VSDA=0V VOL-SDA Low-Level Output Voltage ISDA = -1mA Thermal Shutdown Thermal Shutdown Junction TSD Temperature TSDHYST TSD Hysteresis Pre-Charge End VPreChg Pre-Charge Voltage Threshold VPCHYST Pre-Charge Voltage Hysteresis Charge Restart Voltage below termination for VReStart charging restart Specifications subject to change WWW.TRIUNESYSTEMS.COM -5- Min Typ 4 Max Unit 8.1 V 3 10 mA 50 uA 10 10 uA uA V 3.15 100 200 0.9 1 mV 1.1 MHz 0.4 uA V 0.1 2.2 0.8 200 0.1 -2.0 55 -0.1 0.1 -0.1 0.4 150 2.9 V V mV uA uA uA uA uA uA V 170 °C 10 °C 3.0 70 100 3.1 V mV mV Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CHARGER CHARACTERISTICS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Condition Charging Regulator: L=4.7uH and C=4.7uF Output Current Limit in Full-Charge IBAT-FC IBAT = 1.5A Mode IBAT 10% VBAT 1% Typ IBAT IBAT + 10% VBAT + 1% Unit A Termination Voltage in Top-Off Mode tTO Top-Off Mode Time Out 0 120 min tFC Full-Charge Timer 200 1400 min tacc Timer Accuracy -10% +10% IBAT IOCD High Side Switch On Resistance Low Side Switch On Resistance Max Output Current Over-Current Detect VBAT-OV VBAT Over-Voltage Threshold DUTYMAX Max Duty Cycle ISW = -1A, TJ=25C ISW = 1A, TJ=25C HS switch current 101% VBAT VBAT Max VBAT-TO RDSON IBAT = 0.1C, 0C < Tj < 85C Min 200 250 1.5 2.5 102% VBAT 98 V mΩ mΩ A A 103% VBAT % I2C INTERFACE TIMING REQUIREMENTS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Standard Mode Symbol Parameter Min Max fscl I2C clock frequency 0 100 tsch I2C clock high time 4 tscl I2C clock low time 4.7 (2) 2 tsp I C tolerable spike time 0 50 tsds I2C serial data setup time 250 tsdh I2C serial data hold time 0 (2) ticr I2C input rise time 1000 ticf(2) I2C input fall time 300 tocf(2) I2C output fall time; 10 pF to 400 pF bus 300 tbuf I2C bus free time between Stop and Start 4.7 tsts I2C Start or repeated Start condition setup time 4.7 tsth I2C Start or repeated Start condition hold time 4 tsps(2) I2C Stop condition setup time 4 (1) The I²C interface will operate in either standard or fast mode. (2) Parameters not tested in production. Specifications subject to change WWW.TRIUNESYSTEMS.COM -6- Fast Mode(1) Min Max 0 400 0.6 1.3 0 50 250 0 300 300 300 1.3 0.6 0.6 0.6 Unit kHz µs µs ns ns µs ns ns ns µs µs µs µs Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 THERMISTOR CHARACTERISTICS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Condition VVTH_REF VTH_REF output voltage IVT_REF = 2uA-100uA 10KΩ Temperature Thresholds – β=3434K Min Typ 1.22 0°C 0°C Vtherm Threshold (0°C) Decreasing Temperature 75.6 0°CHYST 0°C Vtherm Threshold with Hysteresis (10°C) Increasing Temperature 66.5 10°C 10°C Vtherm Threshold (10°C) Decreasing Temperature 66.2 10°CHYST 10°C Vtherm Threshold with Hysteresis (11°C) Increasing Temperature 65.4 45°C 45°C Vtherm Threshold (45°C) Increasing Temperature 34.5 45°CHYST 45°C Vtherm Threshold with Hysteresis (44°C) Decreasing Temperature 35.3 50°C 50°C Vtherm Threshold (50°C) Increasing Temperature 30.8 50°CHYST 50°C Vtherm Threshold with Hysteresis (49°C) Decreasing Temperature 31.5 60°C 60°C Vtherm Threshold (60°C) Increasing Temperature 24.9 Decreasing Temperature 30.8 60°C Vtherm Threshold with Hysteresis (50°C) 100KΩ Temperature Thresholds – β=4311K 60°CHYST 0°C 0°C Vtherm Threshold (0°C) Decreasing Temperature 80.5 0°CHYST 0°C Vtherm Threshold with Hysteresis (10°C) Increasing Temperature 69.8 10°C 10°C Vtherm Threshold (10°C) Decreasing Temperature 69.8 10°CHYST 10°C Vtherm Threshold with Hysteresis (11°C) Increasing Temperature 68.6 45°C 45°C Vtherm Threshold (45°C) Increasing Temperature 31.3 45°CHYST 45°C Vtherm Threshold with Hysteresis (44°C) Decreasing Temperature 32.3 50°C 50°C Vtherm Threshold (50°C) Increasing Temperature 27.0 50°CHYST 50°C Vtherm Threshold with Hysteresis (49°C) Decreasing Temperature 27.8 60°C 60°C Vtherm Threshold (60°C) Increasing Temperature 19.4 60°CHYST 60°C Vtherm Threshold with Hysteresis (50°C) Decreasing Temperature 27.0 Specifications subject to change WWW.TRIUNESYSTEMS.COM -7- Max Unit V %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF %VTH _REF Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 FUNCTIONAL DESCRIPTION The TS52001 is a fully-integrated Li-Ion battery charger IC based on a highly-efficient switching topology. It includes a Maximum Power Point Tracking (MPPT) function to optimize its input voltage to extract the maximum possible power from a photovoltaic cell. It includes configurability for termination voltage, charge current and a host of other variables to allow optimum charging conditions for a wide range of Li-Ion batteries. A 1 MHz internal switching frequency facilitates low-cost LC filter combinations. When the battery voltage is below 3.0 volts, the device will enter a pre-charge state and apply a small, programmable charge current to safely charge the battery to a level for which full charge current can be applied. Once the full charge mode has been initiated, the device will maximize available charge current to the battery by adjusting its duty cycle to regulate its input voltage to the Maximum Power Point (MPP) voltage of the photovoltaic cell. If sufficient current is available from the PV cell to exceed the safe 1C charge rate of the battery, then the programmable 1C current limit function will take precedence over the MPP control function and the PV cell voltage will rise above the MPP value. When the battery voltage has increased enough to go into maintenance mode, the PWM control loop will force a constant voltage across the battery. Once in constant voltage mode, current is monitored to determine when the battery is fully charged. This regulation voltage as well as the 1C charging current can be set to change based on battery temperature. There are 4 temperature ranges where these can be set independently, 0-10°C, 10-45°C, 45-50°C and 50-60°C. The 0°C and 60°C thresholds will stop charging and have 10 degrees of hysteresis. The intermediate points have 1 degree of hysteresis. INTERNAL PROTECTION DETAILS Internal Current Limit The current through the inductor is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the cycle. Current limit is always active when the regulator is enabled. Thermal Shutdown If the temperature of the die exceeds 170°C (typical), the SW outputs will tri-state to protect the device from damage. The nFLT and all other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160°C (typical), the device will attempt to start up again. If the device reaches 170°C, the shutdown/restart sequence will repeat. VIN Under-Voltage Lockout The device is held in the off state until VIN reaches 3.15V. There is a 200mV hysteresis on this input, which requires the input to fall below 2.95V before the device will disable. Battery Over-Voltage Protection The TS52001 has a battery protection circuit designed to shutdown the charging profile if the battery voltage is greater than the termination voltage. The termination voltage can change based on user programming, so the protection threshold is set to 2% above the termination voltage. Shutting down the charging profile puts the TS52001 in a fault condition. FAULT HANDLING nFLT Pin Functionality In the event of a battery over-voltage, the battery temperature being outside of the safe charging range or the full charge timer expiring, charging will stop, and the nFLT pin will be pulled low. When the fault condition is no longer present, the device will enter the INITIALIZE state, but the nFLT pin will remain low until register 0 is read. When the register 0 is read, the nFLT pin will go high until a new fault is detected. Other Faults When an open thermistor, thermal shut down, VIN under-voltage, or top off time-out are detected, charging will immediately stop and the corresponding bit in register 0 will be set. The device will enter the INITIALIZE state until the fault is no longer detected. Specifications subject to change WWW.TRIUNESYSTEMS.COM -8- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 SERIAL INTERFACE The TS52001 features an I2C slave interface which offers advanced control and diagnostic features. I2C operation offers configuration control for termination voltages, charge currents, and charge timeouts. This configurability allows for optimum charging conditions in a wide range of Li-Ion batteries. I2C operation also offers fault and warning indicators. Whenever a fault is detected, the associated status bit in the STATUS register is set and the nFLT pin is pulled low. Whenever a warning is detected, the associated status bit in the STATUS register is set, but the nFLT pin is not pulled low. Reading of the STATUS register resets the fault and warning status bits, and the nFLT pin is released after all fault status bits have been reset. I2C SUBADDRESS DEFINITION Figure 3: Sub-address in I2C Transmission I2C BUS OPERATION The TS52001 has a slave I2C interface that supports standard and fast mode data rates, auto-sequencing, and is compliant to I2C standard version 3.0. I2C is a two-wire serial interface where the two lines are serial clock (SCL) and serial data (SDA). SDA must be connected to a positive supply through an external pull-up resistor. The devices communicating on this bus can drive the SDA line low or release it to high impedance. The device that initiates the I2C transaction becomes the master of the bus. Communication is initiated by the master sending a Start condition, a high-to-low transition on SDA, while the SCL line is high. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/nW). After receiving the valid address byte, the device responds with an acknowledge (ACK). An ACK is a low on SDA during the high of the ACK related clock pulse. On the I2C bus, during each clock pulse only one data bit is transferred. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as Start or Stop control commands. A low-to-high transition on SDA while the SCL input is high, indicates a Stop condition and is sent by the master (see Figure 4). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The SDA line must be released by the transmitter before the receiver can send an ACK bit. The receiver that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. To ensure proper operation, setup and hold times must be met. An end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. The transmitter must then release the data line to enable the master to generate a Stop condition. Specifications subject to change WWW.TRIUNESYSTEMS.COM -9- Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 Figure 4: I2C Start / Stop Protocol Figure 5: I2C Data Transmission Timing Specifications subject to change WWW.TRIUNESYSTEMS.COM - 10 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CHARGING STATE DIAGRAM EN INITIALIZE Waiting for Valid Charging Conditions NO No Faults & Vbat < Restart YES PRE CHARGE MPPT w/Pre Charge Current Limit NO Vbat > PreCharge Threshold YES YES 1C CHARGING MPPT w/1C Current Limit and Full Charge Timer Vbat < PreCharge Threshold NO NO NO Vbat = Vterm VBAT = Vterm & Icharge < Ieoc YES END OF CHARGE Vbat regulated to Termination Voltage with EOC Timer YES Icharge < Top Off End Current NO YES Specifications subject to change WWW.TRIUNESYSTEMS.COM - 11 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 REGISTER DESCRIPTION (Device Address = 0x48) REGISTER ADDRESS (HEX) NAME DEFAULT DESCRIPTION 0 00 STATUS 0x00 Status bit register 1 N/A N/A N/A Register not implemented 2 02 CONFIG1(1) EEPROM Configuration register 3 03 CONFIG2(1) EEPROM Configuration register 4 04 CONFIG3(1) EEPROM Configuration register 5 05 CONFIG4(1) EEPROM Configuration register 6 06 CONFIG5(1) EEPROM Configuration register 7-16 N/A N/A N/A Registers not implemented 17 11 CONFIG_ENABLE 0x00 Enable configuration register access 18 12 EEPROM_CTRL(1) 0x00 EEprom control register (1) CONFIG and EEPROM_CTRL registers are only accessible when CONFIG_ENABLE register is written. STATUS REGISTER (STATUS) Address – 0x00h DATA BIT FIELD NAME READ/WRITE D7 BATT_OV R D6 1C_TO R D5 TEMP_0C R D4 TEMP_60C R D3 TSD R D2 TOP_TO R D1 VIN_UV R D0 TH_OPEN R FIELD NAME BIT DEFINITION(2) BATT_OV Battery over-voltage 1C_TO Full charge timer has timed out TEMP_0C Thermistor indicates battery temperature < 0°C TEMP_60C Thermistor indicates battery temperature > 60°C TSD Thermal shutdown TOP_TO Top Off timer has timed out VIN_UV VIN under-voltage TH_OPEN Thermistor Open (battery not present) (1) Faults are defined as BATT_OV, 1C_TO, TEMP_0C, and TEMP_60C. Warnings are defined as TSD, TOP_TO, VIN_UV, and TH_OPEN. Faults cause the nFLT pin to be pulled low, Warnings do not cause the nFLT pin to be pulled low. All status bits are cleared after register read access. nFLT pin will go high impedance (open drain output) after the status register has been read and all status bits have been reset. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 12 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CONFIGURATION REGISTER (CONFIG1) Address – 0x02h DATA BIT FIELD NAME READ/WRITE D7 D6 PRE_CHRG[1:0] R/W R/W D5 D4 D3 V_TERM_0_10[2:0] R/W R/W R/W D2 D1 D0 V_TERM_10_45[2:0] R/W R/W R/W FIELD NAME PRE_CHRG[1:0](1) BIT DEFINITION Pre-Charging configuration 00 – 50 mA 01 – 100 mA 10 – 185 mA 11 – 370 mA (2) V_TERM_0_10[2:0] Voltage Termination 0-10°C configuration 000 – 3.94 V 001 – 4.00 V 010 – 4.05 V 011 – 4.10 V 100 – 4.12 V 101 – 4.15 V 110 – 4.18 V 111 – Invalid Setting V_TERM_10_45[2:0](2) Voltage Termination 10-45°C configuration 000 – 3.94 V 001 – 4.00 V 010 – 4.05 V 011 – 4.10 V 100 – 4.12 V 101 – 4.15 V 110 – 4.18 V 111 – Invalid Setting (1) PRE_CHRG Note: Maximum output current when VBAT < 3.0 V. (2) V_TERM Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and >60°C, charging is disabled and a fault is set. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 13 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CONFIGURATION REGISTER (CONFIG2) Address – 0x03h DATA BIT FIELD NAME READ/WRITE D7 D6 EOC[1:0] R/W R/W D5 D4 D3 V_TERM_45_50[2:0] R/W R/W R/W D2 D1 D0 V_TERM_50_60[2:0] R/W R/W R/W FIELD NAME EOC[1:0](1) BIT DEFINITION End of charge configuration 00 – 50 mA 01 – 100 mA 10 – 185 mA 11 – 370 mA (2) V_TERM_45_50[2:0] Voltage Termination 45-50°C configuration 000 – 3.94 V 001 – 4.00 V 010 – 4.05 V 011 – 4.10 V 100 – 4.12 V 101 – 4.15 V 110 – 4.18 V 111 – Invalid Setting V_TERM_50_60[2:0](2) Voltage Termination 50-60°C configuration 000 – 3.94 V 001 – 4.00 V 010 – 4.05 V 011 – 4.10 V 100 – 4.12 V 101 – 4.15 V 110 – 4.18 V 111 – Invalid Setting (1) EOC Note: Maximum output current when VBAT < 3.0 V. (2) V_TERM Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and >60°C, charging is disabled and a fault is set. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 14 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CONFIGURATION REGISTER (CONFIG3) Address – 0x04h DATA BIT FIELD NAME READ/WRITE D7 R/W D6 D5 MAX_CHRG_CURR_0_10[3:0] R/W R/W D4 D3 R/W R/W D2 D1 MAX_CHRG_CURR_10_45[3:0] R/W R/W D0 R/W FIELD NAME MAX_CHRG_CURR_0_10[3:0](1) BIT DEFINITION Maximum charge current 0-10°C configuration 0000 – 50 mA 0001 – 100 mA 0010 – 200 mA 0011 – 300 mA 0100 – 400 mA 0101 – 500 mA 0110 – 600 mA 0111 – 700 mA 1000 – 800 mA 1001 – 900 mA 1010 – 1000 mA 1011 – 1100 mA 1100 – 1200 mA 1101 – 1300 mA 1110 – 1400 mA 1111 – 1500 mA MAX_CHRG_CURR_10_45[3:0](1) Maximum charge current 10-45°C configuration 0000 – 50 mA 0001 – 100 mA 0010 – 200 mA 0011 – 300 mA 0100 – 400 mA 0101 – 500 mA 0110 – 600 mA 0111 – 700 mA 1000 – 800 mA 1001 – 900 mA 1010 – 1000 mA 1011 – 1100 mA 1100 – 1200 mA 1101 – 1300 mA 1110 – 1400 mA 1111 – 1500 mA (1) MAX_CHRG_CURR Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and >60°C, charging is disabled and a fault is set. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 15 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CONFIGURATION REGISTER (CONFIG4) Address – 0x05h DATA BIT FIELD NAME READ/WRITE D7 R/W D6 D5 MAX_CHRG_CURR_45_50[3:0] R/W R/W D4 D3 R/W R/W D2 D1 MAX_CHRG_CURR_50_60[3:0] R/W R/W D0 R/W FIELD NAME MAX_CHRG_CURR_45_50[3:0](1) BIT DEFINITION Maximum charge current 45-50°C configuration 0000 – 50 mA 0001 – 100 mA 0010 – 200 mA 0011 – 300 mA 0100 – 400 mA 0101 – 500 mA 0110 – 600 mA 0111 – 700 mA 1000 – 800 mA 1001 – 900 mA 1010 – 1000 mA 1011 – 1100 mA 1100 – 1200 mA 1101 – 1300 mA 1110 – 1400 mA 1111 – 1500 mA MAX_CHRG_CURR_50_60[3:0](1) Maximum charge current 50-60°C configuration 0000 – 50 mA 0001 – 100 mA 0010 – 200 mA 0011 – 300 mA 0100 – 400 mA 0101 – 500 mA 0110 – 600 mA 0111 – 700 mA 1000 – 800 mA 1001 – 900 mA 1010 – 1000 mA 1011 – 1100 mA 1100 – 1200 mA 1101 – 1300 mA 1110 – 1400 mA 1111 – 1500 mA (1) MAX_CHRG_CURR Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and >60°C, charging is disabled and a fault is set. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 16 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 CONFIGURATION REGISTER (CONFIG5) Address – 0x06h DATA BIT FIELD NAME READ/WRITE D7 TOP_END R/W D6 TH R/W D5 R/W D4 TOP_TO[2:0] R/W D3 D2 R/W R/W D1 1C_TO[2:0] R/W D0 R/W FIELD NAME TOP_END(1) (1) (2) (3) (4) BIT DEFINITION Top Off end configuration 0 – 25 mA 1 – 92 mA TH(2) Thermistor configuration 0 – 10k Ohms 1 – 100k Ohms TOP_TO[2:0](3) Top Off timer time out configuration 000 – 0 minutes 001 – 20 minutes 010 – 40 minutes 011 – 60 minutes 100 – 80 minutes 101 – 100 minutes 110 – 120 minutes 111 – Disable time out timer 1C_TO[2:0](4) Full charge timer time out configuration 000 – Disable full charge timer 001 – 200 minutes 010 – 400 minutes 011 – 600 minutes 100 – 800 minutes 101 – 1000 minutes 110 – 1200 minutes 111 – 1400 minutes TOP_END Note: Charging stops when VBAT = Vtermination and IBAT < Top Off end. TH Note: Setting for nominal thermistor and reference resistor value. TOP_TO Note: Timer starts when VBAT= Vtermination and IBAT < EOC. 1C_TO Note: Timer starts when VBAT > 3.0V. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 17 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 ENABLE CONFIGURATION REGISTER (CONFIG_ENABLE) Address – 0x11h DATA BIT FIELD NAME READ/WRITE RESET VALUE D7 Not used R 0 FIELD NAME EN_CFG D6 Not used R 0 D5 Not used R 0 D4 Not used R 0 D3 Not used R 0 D2 Not used R 0 D1 Not used R 0 D0 EN_CFG R/W 0 D1 Not used R 0 D0 EE_PROG R/W 0 BIT DEFINITION Enable access control bit for configuration registers 2-6 0 – Disable access 1 – Enable access EEPROM CONTROL REGISTER (EEPROM_CTRL) Address – 0x12h DATA BIT FIELD NAME READ/WRITE RESET VALUE D7 Not used R 0 D6 Not used R 0 D5 Not used R 0 D4 Not used R 0 D3 Not used R 0 D2 Not used R 0 FIELD NAME EE_PROG(1) BIT DEFINITION EEprom program control bit for configuration registers 2-6 0 – Disable EEprom programming 1 – Enable EEprom programming with data from configuration registers 2-6 (1) EE_PROG Note: Inputs VIN and EN must be present for 200 ms. EXTERNAL COMPONENT SELECTION The internal compensation is optimized for a 4.7uF output capacitor and a 4.7uH inductor. To keep the output ripple low, a low ESR (less than 35mOhm) ceramic is recommended. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 18 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 PACKAGE MECHANICAL DRAWINGS Specifications subject to change WWW.TRIUNESYSTEMS.COM - 19 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 APPLICATION USING A MULTI-LAYER PCB To maximize the efficiency of this package for application on a single layer or multi-layer PCB, certain guidelines must be followed when laying out this part on the PCB. The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane. Solder Pad (Land Pattern) Package Thermal Pad Thermal Via's Package Outline Package and PCB Land Configuration For a Multi-Layer PCB JEDEC standard FR4 PCB Cross-section: (square) Package Solder Pad Component Traces 1.5038 - 1.5748 mm Component Trace (2oz Cu) 2 Plane 4 Plane 1.5748mm Thermal Via 1.0142 - 1.0502 mm Ground Plane (1oz Cu) Thermal Isolation Power plane only 0.5246 - 0.5606 mm Power Plane (1oz Cu) 0.0 - 0.071 mm Board Base & Bottom Pad Package Solder Pad (bottom trace) Multi-Layer Board (Cross-sectional View) In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias, thickness of copper, etc. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 20 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 Mold compound Die Epoxy Die attach Exposed pad Solder 5% - 10% Cu coverage Single Layer, 2oz Cu Ground Layer, 1oz Cu Signal Layer, 1oz Cu Thermal Vias with Cu plating 90% Cu coverage 20% Cu coverage Bottom Layer, 2oz Cu Note: NOT to Scale The above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. Each application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the power in the system. The output current rating for the linear regulators may have to be de-rated for ambient temperatures above 85C. The de-rate value will depend on calculated worst case power dissipation and the thermal management implementation in the application. APPLICATION USING A SINGLE LAYER PCB Use as much Copper Area as possible for heat spread Package Thermal Pad Package Outline Layout recommendations for a Single Layer PCB: utilize as much Copper Area for Power Management. In a single layer board application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method (solder paste or thermal conductive epoxy). In both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat. IMPORTANT: If the attachment method is NOT implemented correctly, the functionality of the product is not guaranteed. Power dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 21 - Copyright © 2011, Triune Systems, LLC TS52001 Version 1.3 Legal Notices Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. “Typical” parameters which may be provided in Triune Systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for your application by your technical experts. TRIUNE SYSTEMS MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Triune Systems disclaims all liability arising from this information and its use. Triune System products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Triune Systems product could create a situation where personal injury or death may occur. Should the Buyer purchase or use Triune Systems products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Triune Systems, and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Triune Systems was negligent regarding the design or manufacture of the part. No licenses are conveyed, implicitly or otherwise, under any Triune Systems intellectual property rights. Trademarks The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A.. All other trademarks mentioned herein are property of their respective companies. © 2012 Triune Systems, LLC. All Rights Reserved. Specifications subject to change WWW.TRIUNESYSTEMS.COM - 22 - Copyright © 2011, Triune Systems, LLC