ESD8472MUT5G Ultra-Low Capacitance RF ESD Protection Micro−Packaged Diodes for ESD Protection The ESD8472MUT5G is designed to protect voltage sensitive components that require ultra-low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, high breakdown voltage, high linearity, low leakage, and fast response time make these parts ideal for ESD protection on designs where board space is at a premium. It has industry leading capacitance linearity over voltage making it ideal for RF applications. This capacitance linearity combined with the extremely small package and low insertion loss makes this part well suited for use in antenna line applications for wireless handsets and terminals. http://onsemi.com MARKING DIAGRAM Features • • • • • • • • • Industry Leading Capacitance Linearity Over Voltage Ultra−Low Capacitance: 0.2 pF Insertion Loss: 0.030 dBm 0201DNS Package: 0.60 mm x 0.30 mm Stand−off Voltage: 5.3 V Low Leakage: < 1 nA Low Dynamic Resistance: < 1 W IEC61000−4−2 Level 4 ESD Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • RF Signal ESD Protection • RF Switching, PA, and Antenna ESD Protection • Near Field Communications PIN 1 X3DFN2 CASE 152AF 4M 4 = Specific Device Code M = Date Code ORDERING INFORMATION Device Package Shipping† ESD8472MUT5G X3DFN2 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Value Unit IEC 61000−4−2 (ESD) (Note 1) Rating 20 kV IEC 61000−4−5 (ESD) (Note 2) 3.0 A °PD° RqJA 300 400 mW °C/W TJ, Tstg −55 to +150 °C TL 260 °C Total Power Dissipation (Note 3) @ TA = 25°C Thermal Resistance, Junction−to−Ambient Junction and Storage Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) Symbol Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform. 2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. 3. Mounted with recommended minimum pad size, DC board FR−4 © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 1 1 Publication Order Number: ESD8472/D ESD8472MUT5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT I IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Parameter Reverse Working Voltage Breakdown Voltage Symbol Condition Min Typ VRWM VBR IT = 1 mA (Note 4) Max Unit 5.3 V 7.0 V Reverse Leakage Current IR VRWM = 5.3 V <1 50 nA Clamping Voltage VC IPP = 1 A (Note 5) 11 15 V Clamping Voltage VC IPP = 3 A (Note 5) 14 20 V ESD Clamping Voltage VC Per IEC61000−4−2 See Figures 1 and 2 Junction Capacitance CJ VR = 0 V, f = 1 MHz VR = 0 V, f = 1 GHz 0.20 0.15 Dynamic Resistance RDYN Insertion Loss 0.30 0.30 pF TLP Pulse 1 W f = 1 MHz f = 8.5 GHz 0.050 0.250 dB 4. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 5. Non−repetitive current pulse at 25°C, per IEC61000−4−5 waveform. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESD8472MUT5G Figure 3. IV Characteristics Figure 4. CV Characteristics Figure 5. RF Insertion Loss Figure 6. Capacitance over Frequency 20 0 18 −2 16 −4 14 −6 CURRENT (A) CURRENT (A) TYPICAL CHARACTERISTICS 12 10 8 6 −8 −10 −12 −14 4 −16 2 −18 0 0 5 10 15 20 VOLTAGE (V) 25 −20 −30 30 Figure 7. Positive TLP I−V Curve −25 −20 −15 −10 VOLTAGE (V) −5 Figure 8. Negative TLP I−V Curve http://onsemi.com 3 0 ESD8472MUT5G PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE O PIN 1 INDICATOR (OPTIONAL) 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D 0.035 C 2X DIM A A1 b D E e L E 0.035 C TOP VIEW 0.05 C A 2X 0.05 C A1 SIDE VIEW 1 0.05 M RECOMMENDED MOUNTING FOOTPRINT* SEATING PLANE 0.74 2X 0.30 1 e 2X C MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.62 BSC 0.32 BSC 0.355 BSC 0.17 0.23 2 2X b 2X 0.05 L M C A B BOTTOM VIEW 0.31 DIMENSIONS: MILLIMETERS C A B See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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