W40S11-23 Clock Buffer/Driver Features Key Specifications • Thirteen skew-controlled CMOS clock outputs (SDRAM0:12) • Supports three SDRAM DIMMs • Ideal for high-performance systems designed around Intel’s latest chip set • I2C serial configuration interface • Clock Skew between any two outputs is less than 250 ps • 1- to 5-ns propagation delay • DC to 133-MHz operation • Single 3.3V supply voltage • Low power CMOS design packaged in a 28-pin, 300-mil SOIC (Small Outline Integrated Circuit) Overview Supply Voltages:........................................... VDD = 3.3V±5% Operating Temperature:.................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: .......................................VDD + 0.5V Input Frequency:............................................... 0 to 133 MHz BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns Output Edge Rate:.............................................. >1.5 V/ns Output Clock Skew: .................................................. ±250 ps Output Duty Cycle: .................................. 45/55% worst case Output Impedance: ...............................................15Ω typical Output Type: ................................................ CMOS rail-to-rail The Cypress W40S11-23 is a low-voltage, thirteen-output clock buffer. Output buffer impedance is approximately 15Ω, which is ideal for driving SDRAM DIMMs. Pin Configuration Block Diagram SDATA SCLOCK Serial Port SOIC Device Control SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN SDRAM4 SDRAM5 SDRAM12 VDD SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD SDRAM11 SDRAM10 GND VDD SDRAM9 SDRAM8 GND VDD SDRAM7 SDRAM6 GND GND  SCLOCK SDRAM9 SDRAM10 SDRAM11 Note: 1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs (not CMOS level). SDRAM12 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 28, 1999 rev. ** W40S11-23 Pin Definitions Pin No. Pin Type 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12 O SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. BUF_IN 9 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SDATA 14 I/O I2C Data input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. SCLOCK 15 I I2C clock input: The I2C data clock should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. VDD 1, 5, 13, 20, 24, 28 P Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. GND 4, 8, 16, 17, 21, 25 G Ground Connection: Connect all ground pins to the common system ground plane. Pin Name SDRAM0:12 Pin Description Functional Description capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15Ω. Output Drivers Operation The W40S11-23 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal Data is written to the W40S11-23 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1. Table 1. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Commands the W40S11-23 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S11-23 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W40S11-23, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W40S11-23, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 2 5 Data Byte 1 6 Data Byte 2 The data bits in these bytes set internal W40S11-23 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. 7 Data Byte 3 Don’t Care Refer to Cypress Frequency Timing Generators. 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 Bit Sequence Byte Description 2 W40S11-23 Writing Data Bytes Table 2 gives the bit formats for registers located in Data Bytes 0–6. Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 2. Data Bytes 0–2 Serial Configuration Map Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable) 7 11 SDRAM5 Clock Output Disable Low Active 6 10 SDRAM4 Clock Output Disable Low Active 5 N/A Reserved (Reserved) - - 4 N/A Reserved (Reserved) - - 3 7 SDRAM3 Clock Output Disable Low Active 2 6 SDRAM2 Clock Output Disable Low Active 1 3 SDRAM1 Clock Output Disable Low Active 0 2 SDRAM0 Clock Output Disable Low Active Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable) 7 27 SDRAM11 Clock Output Disable Low Active 6 26 SDRAM10 Clock Output Disable Low Active 5 23 SDRAM9 Clock Output Disable Low Active 4 22 SDRAM8 Clock Output Disable Low Active 3 N/A Reserved (Reserved) - - 2 N/A Reserved (Reserved) - - 1 19 SDRAM7 Clock Output Disable Low Active 0 18 SDRAM6 Clock Output Disable Low Active - - Low Active Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable) 7 N/A Reserved (Reserved) 6 12 SDRAM12 Clock Output Disable 5 N/A Reserved (Reserved) -- -- 4 N/A Reserved (Reserved) -- -- 3 N/A Reserved (Reserved) -- -- 2 N/A Reserved (Reserved) -- -- 1 N/A Reserved (Reserved) -- -- 0 N/A Reserved (Reserved) -- -- Note: 2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to a “0.” 3 W40S11-23 How To Use the Serial Data Interface logic 1. All bus devices generally have logic inputs to receive data. Electrical Requirements Although the W40S11-23 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. Figure 1 illustrates electrical characteristics for the serial interface bus used with the W40S11-23. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2kΩ ~ 2kΩ SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT SDATA SCLOCK DATA IN N DATA OUT CLOCK IN N DATA IN DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 1. Serial Interface Bus Electrical Characteristics 4 SDATA N W40S11-23 Signaling Requirements A write sequence is initiated by a “start bit” as shown in Figure 3. A “stop bit” signifies that a transmission has ended. As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). As stated previously, the W40S11-23 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 4. SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 2. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 3. Serial Data Bus Start and Stop Bit 5 Figure 4. Serial Data Bus Write Sequence Signaling from System Core Logic Start Condition Stop Condition Slave Address (First Byte) Command Code (Second Byte) SDATA MSB 1 1 0 1 0 0 1 LSB 0 SCLOCK 1 2 3 4 5 6 7 8 Byte Count (Third Byte) MSB A 1 LSB 2 3 4 5 6 7 8 Last Data Byte (Last Byte) MSB A 1 MSB 2 3 4 1 LSB 2 3 4 5 6 7 8 A SDATA Acknowledgment Bit from Clock Device Signaling by Clock Device 6 tSPF tLOW SCLOCK tSTHD tDSU tHIGH tR tF tDHD tSP tSPSU tSTHD t SPSU W40S11-23 Figure 5. Serial Data Bus Timing Diagram SDATA W40S11-23 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% Parameter IDD Description 3.3V Supply Current Test Condition/Comments Min Typ BUF_IN = 100 MHz Max Unit 250 mA V Logic Inputs VIL Input Low Voltage GND–0.3 0.8 VIH Input High Voltage 2.0 VDD+0.5 V IILEAK Input Leakage Current, BUF_IN –5 +5 µA IILEAK Input Leakage Current –20 +5 µA 50 mV Logic Outputs (SDRAM0:12) VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 65 100 160 mA IOH Output High Current VOH = 1.5V 70 110 185 mA V Pin Capacitance/Inductance CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Note: 3. SDATA and SCLOCK logic pins have 250-kΩ internal pull-up resistors. 7 W40S11-23 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency 0 133 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 4.0 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4.0 V/ns tSR Output Skew, Rising Edges 250 ps tSF Output Skew, Falling Edges 250 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 1.0 5.0 ns tPF Falling Edge Propagation Delay 1.0 5.0 ns tD Duty Cycle 45 55 % Zo AC Output Impedance tPR Rising Edge Propagation Delay Measured at 1.5V 1.0 Ordering Information Ordering Code W40S11 Ω 15 Freq. Mask Code Package Name -23 G Package Type 28-pin SOIC (300 mils) Document #: 38-00793 8 5.0 ns W40S11-23 Package Diagram 28-Pin Small Outline Integrated Circuit (SOIC, 0.300 inch) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.