ONSEMI 74HCT04

74HCT04
Hex Inverter
With LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The 74HCT04 may be used as a level converter for interfacing TTL
or NMOS outputs to High−Speed CMOS inputs. The HCT04A is
identical in pinout to the LS04.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 48 FETs or 12 Equivalent Gates
These are Pb−Free Devices
14
SOIC−14
D SUFFIX
CASE 751A
14
1
HCT04G
AWLYWW
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT04
A
L, WL
Y
W, WW
G or G
HCT
04
ALYWG
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HCT04/D
74HCT04
Pinout: 14−Lead Packages (Top View)
VCC
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
LOGIC DIAGRAM
A1
A2
A3
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
A4
A5
1
2
3
4
5
6
9
8
11
10
13
12
Y1
Y2
Y3
Y4
Y5
FUNCTION TABLE
Inputs
Outputs
A
Y
L
H
H
L
A6
Y=A
Y6
Pin 14 = VCC
Pin 7 = GND
ORDERING INFORMATION
Package
Shipping †
SOIC−14
(Pb−Free)
2500 / Tape & Reel
Device
74HCT04DR2G
74HCT04DTR2G
TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HCT04
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air
500
450
mW
Tstg
Storage Temperature Range
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
4.5
5.5
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature Range, All Package Types
– 55
+ 125
_C
tr, tf
Input Rise/Fall Time (Figure 1)
0
500
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
−55 to 25°C
≤85°C
≤125°C
Unit
Vout = 0.1V
|Iout| ≤ 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
Maximum Low−Level Input Voltage
Vout = VCC − 0.1V
|Iout| ≤ 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High−Level Output
Voltage
Vin = VIL
|Iout| ≤ 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
3.98
3.84
3.70
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
Parameter
VIH
Minimum High−Level Input Voltage
VIL
VOH
Condition
Vin = VIL
VOL
Guaranteed Limit
VCC
(V)
Symbol
Maximum Low−Level Output
Voltage
|Iout| ≤ 4.0mA
Vin = VIH
|Iout| ≤ 20mA
Vin = VIH
|Iout| ≤ 4.0mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
5.5
2.0
20
40
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
Iout = 0mA
5.5
≥ −55°C
25 to 125°C
2.9
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + ΣDICC.
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3
74HCT04
AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns)
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
15
17
19
21
22
26
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Cin
3. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
22
Power Dissipation Capacitance (Per Inverter)*
* Used to determine the no−load dynamic power consumption: PD = CPD VCC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
tf
INPUT A
2f + I
CC
pF
VCC . For load considerations, see Chapter 2 of the
tr
3.0V
2.7V
1.3V
0.3V
TEST
POINT
GND
tPLH
OUTPUT
DEVICE
UNDER
TEST
tPHL
90%
OUTPUT Y
C L*
1.3V
10%
tTLH
tTHL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)
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4
74HCT04
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
74HCT04
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
0.25 (0.010)
8
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
74HCT04
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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7
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For additional information, please contact your local
Sales Representative
74HCT04/D