SCBS094B − DECEMBER 1991 − JULY 1994
•
•
•
•
•
•
SN54ABT5400 . . . JT PACKAGE
SN74ABT5400 . . . DW PACKAGE
(TOP VIEW)
Output Ports Have 25-Ω Series Resistors,
So No External Resistors Are Required
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
Typical VOLV (Output Undershoot)
< 0.5 V at VCC = 5 V, TA = 25°C
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and DIPs (JT)
Y1
Y2
Y3
Y4
Y5
Y6
GND
GND
Y7
Y8
Y9
Y10
Y11
OE1
description
These 11-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
D1
D2
D3
D4
D5
D6
VCC
VCC
D7
D8
D9
D10
D11
OE2
D4
D5
D6
VCC
VCC
D7
D8
SN54ABT5400 . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all 11 outputs are in the
high-impedance state.
D3
D2
D1
Y1
Y2
Y3
Y4
The outputs, which are designed to source or sink
up to 12 mA, include 25-Ω series resistors to
reduce overshoot and undershoot.
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
D9
D10
D11
OE2
OE1
Y11
Y10
Y5
Y6
GND
GND
Y7
Y8
Y9
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking
capability of the driver.
4
5
The SN54ABT5400 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The SN74ABT5400 is characterized for
operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
D
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
!" #$%&'() %$)*!)" +
!),$-'*!$) %&--() *" $, .&/0!%*!$) #*(1 -$#&%" %$),$-' $
".(%!,!%*!$)" .(- ( (-'" $, (2*" )"-&'()" "*)#*-# 3*--*)41
-$#&%!$) .-$%(""!)5 #$(" )$ )(%(""*-!04 !)%0&#( ("!)5 $, *00
.*-*'((-"1
• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
POST OFFICE BOX 1443
6−1
SCBS094B − DECEMBER 1991 − JULY 1994
logic symbol†
14
OE1
OE2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
logic diagram (positive logic)
OE1
&
28
27
OE2
EN
15
1
1
2
26
3
25
4
24
5
23
6
20
9
19
10
18
11
17
12
16
13
D1
14
15
28
1
Y1
Y1
Y2
To 10 Other Channels
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
6−2
•
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•
SCBS094B − DECEMBER 1991 − JULY 1994
recommended operating conditions (see Note 2)
SN54ABT5400
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t /∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT5400
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused or floating inputs must be held high or low.
−55
0
V
V
0.8
VCC
−12
UNIT
VCC
−12
V
V
mA
12
12
mA
10
10
ns / V
85
°C
125
−40
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
−1.2
−1.2
MIN
MAX
SN74ABT5400
MIN
3.35
3.7
3.3
3.35
VCC = 5 V,
IOH = −1 mA
IOH = − 3 mA
3.85
4.2
3.8
3.85
3
3.1
IOH = −12 mA
IOL = 8 mA
2.6
VCC = 4.5 V
II
IOZH
VCC = 5.5 V,
VCC = 5.5 V,
IOZL
Ioff
VCC = 5.5 V,
VCC = 0,
ICEX
IO
IOS‡
VCC = 5.5 V,
VCC = 5.5 V,
Ci
SN54ABT5400
II = −18 mA
IOH = −1 mA
VOL
∆ICC§
TA = 25°C
TYP†
MAX
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V
ICC
MIN
VCC = 5.5 V,
VCC = 5.5 V,
One input at
3.4 V, Other
inputs at
VCC or GND
−1.2
VO = 2.7 V
VO = 0.5 V
VI or VO ≤ 4.5 V
VO = 5.5 V
Outputs high
0.65
±ā 1
±1
µA
50
50
50
µA
−50
−50
−50
µA
±100
µA
50
µA
−100
−25
−100
−25
−100
mA
−200
−50
−ā 200
−50
−200
mA
50
−45
−50
V
±1
±100
−25
V
V
0.8
VO = 2.5 V
VO = 0
UNIT
2.6
0.8
IOL = 12 mA
VI = VCC or GND
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
MAX
50
Outputs high
5
50
50
50
µA
Outputs low
36
45
45
45
mA
1
50
50
50
µA
Outputs enabled
1.5
1.5
1.5
Outputs disabled
0.05
0.05
0.05
1.5
1.5
1.5
Outputs disabled
Data inputs
Control inputs
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
3
Co
8
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
mA
pF
pF
+ !),$-'*!$) %$)%(-)" .-$#&%" !) ( ,$-'*!6( $#("!5) .*"( $, #(6(0$.'()1 +*-*%(-!"!% #** *)# $(".(%!,!%*!$)" *-( #("!5) 5$*0"1 (2*" )"-&'()" -("(-6(" ( -!5 $
%*)5( $- #!"%$)!)&( ("( .-$#&%" 3!$& )$!%(1
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
6−3
SCBS094B − DECEMBER 1991 − JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT5400
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2
4.5
5.7
2
6.7
2
6.5
1.5
3.7
4.5
1.5
5.5
1.5
5.2
2.5
5.7
6.6
2.5
8.6
2.5
8.5
2
4.4
5.5
2
6.9
2
6.8
1.5
3.6
4.4
1.5
5.5
1.5
5.2
1.5
4.2
5.4
1.5
7.4
1.5
6.9
+ !),$-'*!$) %$)%(-)" .-$#&%" !) ( ,$-'*!6( $#("!5) .*"( $, #(6(0$.'()1 +*-*%(-!"!% #** *)# $(".(%!,!%*!$)" *-( #("!5) 5$*0"1 (2*" )"-&'()" -("(-6(" ( -!5 $
%*)5( $- #!"%$)!)&( ("( .-$#&%" 3!$& )$!%(1
6−4
•
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•
SN74ABT5400
UNIT
ns
ns
ns
SCBS094B − DECEMBER 1991 − JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
(see Note B)
1.5 V
0V
Output
1.5 V
VOL
tPLH
tPHL
Output
Waveform 2
S1 at Open
(see Note C)
VOH
Output
1.5 V
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note C)
VOH
1.5 V
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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•
6−5
SCBS094B − DECEMBER 1991 − JULY 1994
6−6
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•
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ABT5400DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
SN74ABT5400DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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