UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 RAD-TOLERANT CLASS-V REGULATING PULSE WIDTH MODULATOR FEATURES 1 • • • • • • • • • • • • • • (1) QML-V Qualified, SMD 5962-89511 Rad-Tolerant: 30 kRad (Si) TID (1) 8-V to 35-V Operation 5.1-V Buried Zener Reference Trimmed to ±0.75% 100-Hz to 400-kHz Oscillator Range Separate Oscillator Sync Terminal Adjustable Deadtime Control Internal Soft Start Pulse-by-Pulse Shutdown Input Undervoltage Lockout With Hysteresis Latching PWM to Prevent Multiple Pulses Dual Source/Sink Output Drivers Low Cross Conduction Output Stage Tighter Reference Specifications Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. DESCRIPTION The UC1525B pulse width modulator integrated circuit is designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip 5.1-V buried zener reference is trimmed to ±0.75%, and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The UC1525B output stage features NOR logic, giving a LOW output for an OFF state. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated UC1525B-SP SLUS874 – JANUARY 2009............................................................................................................................................................................................... www.ti.com BLOCK DIAGRAM This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) 2 TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C FK 5962-8951106V2A UC1525BFK-SP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) +VIN Supply voltage VC Collector supply voltage 40 V 40 V Logic inputs –0.3 V to 5.5 V VI Analog inputs IO Output current, source or sink –0.3 V to VIN 500 mA Reference output current 50 mA Oscillator charging current 5 mA TA = 25°C 1000 mW TC = 25°C 2000 mW PD Power dissipation TJ Operating junction temperature –55°C to 150°C Tstg Storage temperature range –65°C to 150°C Tlead Lead temperature (soldering, 10 seconds) (1) (2) 300°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) +VIN Input voltage VC Collector supply voltage MAX 8 35 UNIT V 4.5 35 V Sink/source load current (steady state) 0 100 mA Sink/source load current (peak) 0 400 mA Reference load current Oscillator frequency range Oscillator timing resistor Oscillator timing capacitor Dead time resistor range (1) MIN 0 20 mA 0.1 400 kHz 2 150 kΩ 0.001 0.1 µF 0 500 Ω Range over which the device is functional and parameter limits are specified. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP 3 UC1525B-SP SLUS874 – JANUARY 2009............................................................................................................................................................................................... www.ti.com CONNECTION DIAGRAM LCC-20, PLCC-20 (Top View) FK Package ELECTRICAL CHARACTERISTICS VIN = 20 V, TA = TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.062 5.10 5.138 V Reference Section Output voltage TJ = 25°C Line regulation VIN = 8 V to 35 V 5 10 mV Load regulation IL = 0 mA to 20 mA 7 15 mV Temperature stability (1) Over operating range 10 50 mV Total output variation Over line, load, and temperature Short-circuit current VREF = 0 V, TJ = 25°C 80 100 Output noise voltage (1) 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C 40 200 µVrms 5.036 5.164 V mA Oscillator Section Initial accuracy (2) TJ = 25°C Voltage stability (2) VIN = 8 V to 35 V Temperature stability (1) (2) Over operating range Minimum frequency RT = 200 kΩ, CT = 0.1 µF Maximum frequency RT = 2 kΩ, CT = 470 pF 400 Current mirror IRT = 2 mA 1.7 2. 3 3.5 TJ = 25°C 0.3 1.2 Clock amplitude (2) Clock width (2) Sync threshold Sync input current (1) (2) 4 Sync = 3.5 V ±2 ±6 % ±0.3 ±1 % ±3 ±6 % 120 Hz kHz 2.2 mA 0.5 1 µs 2 2.8 V 1 2.5 mA V Parameters ensured by design and/or characterization, if not production tested. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0 Ω). Approximate oscillator frequency is defined by: f = 1/(CT (0.7 x RT + 3RD)). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 ELECTRICAL CHARACTERISTICS (continued) VIN = 20 V, TA = TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 5 mV 1 10 µA 1 µA Error Amplifier Section (VCM = 5.1 V) Input offset voltage Input bias current Input offset current RL ≥ 10 MΩ DC open loop gain Gain-bandwidth product (3) AV = 0 dB, TJ = 25°C 60 1 Ouput low level 75 2 0.2 Output high level dB MHz 0.5 V 3.8 5.6 V Common mode rejection VCM = 1.5 V to 5.2 V 60 75 dB Supply voltage rejection VIN = 8 V to 35 V 50 60 dB PWM Comparator Minimum duty cycle Maximum duty cycle 0 (4) Input threshold (4) Zero duty cycle Input threshold (4) Maximum duty cycle 45 49 0.7 0.9 3.3 Input bias current % % V 3.6 V µA 0.05 Shutdown Section 50 80 µA 0.4 0.7 V 0.8 1 V VSHUTDOWN = 2.5 V 0.4 1 mA VSHUTDOWN = 2.5 V, TJ = 25°C 0.2 0.5 µs ISINK = 20 mA 0.2 0.4 1 2 Soft start current VSHUTDOWN = 0 V, VSOFTSTART = 0 V Soft start low level VSHUTDOWN = 2.5 V Shutdown threshold To outputs, VSOFTSTART = 5.1 V, TJ = 25°C Shutdown input current Shutdown delay (3) 25 0.6 Output Drivers (Each OUtput) (VC = 20 V) Output low level Output high level ISINK = 100 mA ISOURCE = 20 mA 18 19 ISOURCE = 100 mA 17 18 6 7 Undervoltage lockout VCOMP and VSOFTSTART = High Collector leakage VC = 35 V Rise time (3) CL = 1 nF, TJ = 25°C 100 Fall time (3) CL = 1 nF, TJ = 25°C 50 Cross conduction charge Per cycle, TJ = 25°C 30 VIN = 35 V 14 V V 8 V 200 µA 600 ns 300 ns nc Total Standby Current Supply current (3) (4) 20 mA Parameters ensured by design and/or characterization, if not production tested. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0 Ω). Approximate oscillator frequency is defined by: f = 1/(CT (0.7 x RT + 3RD)). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP 5 UC1525B-SP SLUS874 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS Output Circuit (½ Circuit Shown) 6 Output Saturation Characteristics For single ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are acheived with speed-up capacitors C, and C2. The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. Low power transformers can be driven directly by the UC1525B. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pullups, either can readily accept a pulldown signal, which only has to sink a maximum of 100 µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10, which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM latch is immediately set providing the fastest turn-off signal to the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, ultimately discharges this external capacitor, recycling slow turn-on upon release. Oscillator Schematic Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP 7 UC1525B-SP SLUS874 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) Oscillator Charge Time vs. RT and CT Oscillator Discharge Time vs. RD and CT UDG-95064 UDG-95063 Error Amplifier Error Amplifier Open-Loop Frequency Response UDG-95065 8 Submit Documentation Feedback UDG-95066 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) LAB TEST FIXTURE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1525B-SP 9 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8951105V2A ACTIVE LCCC FK 20 1 TBD 5962-8951105VEA ACTIVE CDIP J 16 1 TBD 5962-8951106V2A ACTIVE LCCC FK 20 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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