TPS386000-Q1
www.ti.com
SBVS149 – SEPTEMBER 2010
Quad Supply Voltage Supervisors
with Programmable Delay and Watchdog Timer
Check for Samples: TPS386000-Q1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The TPS386000-Q1 family of voltage supervisors can
monitor four power rails that are greater than 0.4V
and one power rail less than 0.4V (including negative
voltage) with a 0.25% (typical) threshold accuracy.
Each of the four supervisory circuits (SVS-n) assert a
RESETn or RESETn output signal when the
SENSEm input voltage drops below the programmed
threshold. With external resistors, the threshold of
each SVS-n can be programmed (where n = 1, 2, 3,
4 and m = 1, 2, 3, 4L, 4H).
1
2
•
•
•
•
•
Qualified for Automotive Applications
4 Complete SVS Modules on 1 Silicon Platform
Programmable Delay Time: 1.4ms to 10s
Very Low Quiescent Current: 12mA typ
Threshold Accuracy: 0.25% typ
SVS-1: Manual Reset (MR) Input
SVS-1,2,3: Adjustable Threshold Down to 0.4V
SVS-4: Adjustable Threshold at Any
Positive/Negative Voltage with VREF (1.2V)
SVS-4: Window Comparator
Watchdog Timer with Dedicated Output
Well-Controlled RESETn Output During
Power-Up
Open-Drain RESETn and WDO
Package: 4mm x 4mm, 20-pin QFN
Each SVS-n has a programmable delay before
releasing RESETn or RESETn, and the delay time
can be set from 1.4ms to 10s through the CTn pin
connection. Only SVS-1 has an active-low manual
reset (MR) input; a logic-low input to MR asserts
RESET1 or RESET1.
SVS-4 monitors the threshold window using two
comparators. The extra comparator can be
configured as a fifth SVS to monitor negative voltage
with voltage reference output VREF.
The TPS386000-Q1 has a very low quiescent current
of 12mA (typical) and is available in a small, 4mm x
4mm, QFN-20 package.
Sequence: VIN
VCC41(positive)and VCC42(negative)
VCC3
VCC2
VCC1
VCC42
VCC-
VCC41
EN4
DC-DC
LDO
VCC+
AMP
VCC3
VCC2
VCC1
EN3
EN2
DC-DC
LDO
Sub CPU
MSP430
DC-DC
LDO
RS3H
RS2H
RS1H
VREF
WDI
WDO
VCC1
SENSE1
RESET1
SENSE2
VIN
Pos
and
Neg
DC-DC
RP5 RP4 RP3 RP2 RP1
VCC
MR
TPS386000
SENSE3
RS41H
RESET
RESET2
VCC2
DSP
CPU
FPGA
VCC3
CLK
RESET3
SENSE4L
RESET4
SENSE4H
CT1
CT2
CT3
CT4
GND
RS42L
CT1
RS42H
RS41L
RS3L
RS2L
CT2
CT3
CT4
RS1L
Figure 1. TPS386000-Q1 Typical Application Circuit
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS386000-Q1
SBVS149 – SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
DESCRIPTION
TPS386000QRGPRQ1
Open-drain,
active low
PACKAGELEAD
PACKAGE
DESIGNATOR (2)
TEMPERATURE
RANGE
PACKAGE
MARKING
TRANSPORT
MEDIA,
QUANTITY
VQFN-20
RGP
–40°C to +125°C
TPS386000Q
Reel, 3000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating junction temperature range, unless otherwise noted.
Input voltage range, VVCC
CT pin voltage range, VCT1, VCT2, VCT3, VCT4
Other voltage ranges: VRESET1, VRESET2, VRESET3, VRESET4, VMR, VSENSE1,
VSENSE2, VSENSE3, VSENSE4L, VSENSE4H, VWDI, VWDO
RESETn , RESETn, WDO, WDO, VREF pin current
Continuous total power dissipation
TPS386000-Q1
UNIT
–0.3 to 7.0
V
–0.3 to VVCC + 0.3
V
–0.3 to 7.0
V
5
mA
See Thermal Information Table
Operating virtual junction temperature range, TJ
(2)
–40 to +150
°C
Operating ambient temperature range
–40 to +125
°C
Storage temperature range, TSTG
–65 to +150
°C
Latch-up performance meets 100mA per AEC-Q100
(1)
(2)
Class I
Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended
operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
THERMAL INFORMATION
TPS386000-Q1
THERMAL METRIC (1)
RGP PACKAGE
UNITS
20 PINS
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
1.5
qJB
Junction-to-board thermal resistance
21.0
yJT
Junction-to-top characterization parameter
42.8
yJB
Junction-to-board characterization parameter
8.8
qJCbot
Junction-to-case (bottom) thermal resistance
21.2
(1)
2
50.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, 1.8V < VVCC < 6.5V, RRESETn (n = 1, 2, 3, 4) = 100kΩ to VVCC,
CRESETn (n = 1, 2, 3, 4L, 4H) = 50pF to GND, RWDO = 100kΩ to VVCC, CWDO = 50pF to GND, VMR = 100kΩ to VVCC, WDI =
GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
VVCC
IVCC
TEST CONDITIONS
Input supply range
MIN
TYP
1.8
Supply current (current into VCC pin)
Power-up reset voltage (2) (3)
VVCC = 3.3V, RESETn or RESETn not
asserted, WDI toggling (1), no output load,
and VREF open
VVCC = 6.5V, RESETn or RESETn not
asserted, WDI toggling (1), no output load,
and VREF open
MAX
UNIT
6.5
V
11
19
mA
13
22
mA
0.9
V
VITN
Negative-going input threshold voltage SENSE1, SENSE2, SENSE3, SENSE4L
396
400
404
mV
VITP
Positive-going input threshold voltage
SENSE4H
396
400
404
mV
VHYSN
Hysteresis (positive-going) on VITN
SENSE1, SENSE2, SENSE3, SENSE4L
3.5
10
mV
VHYSP
Hysteresis (negative-going) on VITP
SENSE4H
3.5
10
mV
ISENSE
Input current at SENSEm pin
VSENSEm = 0.42V
–25
±1
+25
nA
CCT1 > 220pF, VCT1 = 0.5V (4)
245
300
355
nA
CT1
ICT
CTn pin charging
current
VTH(CTn)
CTn pin threshold
VIL
MR and WDI logic low input
VIH
MR and WDI logic high input
CT2, CT3, CT4
VOL (max) = 0.2V, IRESETn = 15mA
CCTn > 220pF, VCTn = 0.5V
(4)
CCTn > 220pF
235
300
365
nA
1.180
1.238
1.299
V
0.3VVCC
V
0
0.7VVCC
V
IOL = 1mA
0.4
V
SENSEn = 0V, 1.3V < VVCC < 1.8V,
IOL = 0.4mA (2)
0.3
V
Low-level WDO output voltage
IOL = 1mA
0.4
V
ILKG
RESETn, RESETn, WDO, and WDO
leakage current
VRESETn = 6.5V, RESETn, RESETn, WDO,
and WDO are logic high
–300
300
nA
VREF
Reference voltage output
1mA < IVREF < 0.2mA (source only, no sink)
1.18
CIN
Input pin capacitance
CTn: 0V to VVCC, other pins: 0V to 6.5V
tW
SENSEm: 1.05VITN → 0.95VITN or
Input pulse width to SENSEm and MR 0.95V → 1.05V
ITP
ITP
pins
MR: 0.7VCC → 0.3VVCC
Low-level RESETn or RESETn output
voltage
VOL
tD
RESETn or RESETn delay time
tWDT
Watchdog timer timeout period
(1)
(2)
(3)
(4)
1.20
1.22
V
5
pF
4
ms
1
ns
CTn = open
14
20
24
ms
CTn = VVCC
225
300
375
ms
Start from RESET1 or RESET1 release or
last WDI transition
450
600
750
ms
Toggling WDI for a period less than tWDT negatively affects IVCC.
These specifications are beyond the recommended VVCC range, and only define RESETn or RESETn output performance during VCC
ramp up.
The lowest supply voltage (VVCC) at which RESETn or RESETn becomes active; tRISE(VCC) ≥ 15ms/V.
CTn (where n = 1, 2, 3, or 4) are constant current charging sources working from a range of 0V to VTH(CTn), and the device is tested at
VCTn = 0.5V. For ICT performance between 0V and VTH(CTn), see Figure 23.
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FUNCTIONAL BLOCK DIAGRAM
VCC
WDO
WDI
WDT
VREF
VREF
RESET1
SENSE1
Delay
0.4V
MR
CT1
RESET2
SENSE2
Delay
0.4V
CT2
RESET3
SENSE3
Delay
0.4V
CT3
RESET4
SENSE4L
Delay
0.4V
SENSE4H
CT4
GND
Figure 2. TPS386000
4
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PIN CONFIGURATIONS
WDI
WDO
RESET4
RESET3
RESET2
20
19
18
17
16
RGP PACKAGE
QFN-20
(TOP VIEW)
MR
1
15
RESET1
CT4
2
14
VCC
CT3
3
13
VREF
CT2
4
12
GND
11
NC
6
7
8
9
10
SENSE4L
SENSE3
SENSE2
SENSE1
5
SENSE4H
CT1
(Thermal Pad)
PIN ASSIGNMENTS
PIN
NAME
NO.
DESCRIPTION
VCC
14
Supply voltage. Connecting a 0.1mF ceramic capacitor close to this pin is recommended.
GND
12
Ground
SENSE1
10
Monitor voltage input to SVS-1
When the voltage at this terminal drops below the
threshold voltage (VITN), RESET1 is asserted.
SENSE2
9
Monitor voltage input to SVS-2
When the voltage at this terminal drops below the
threshold voltage (VITN), RESET2 is asserted.
SENSE3
8
Monitor voltage input to SVS-3
When the voltage at this terminal drops below the
threshold voltage (VITN), RESET3 is asserted.
SENSE4L
7
Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold
voltage (VITN), RESET4 or RESET4 is asserted.
SENSE4H
6
Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage
(VITP), RESET4 or RESET4 is asserted. This pin can also be used to monitor the negative voltage rail
in combination with VREF pin.
CT1
5
Reset delay programming pin for SVS-1
CT2
4
Reset delay programming pin for SVS-2
CT3
3
Reset delay programming pin for SVS-3
CT4
2
Reset delay programming pin for SVS-4
VREF
13
Reference voltage output. By connecting a resistor network between this pin and the negative power
rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into
resistor(s). Do not connect only capacitors and do not connect resistor(s) to a higher voltage than this
pin.
MR
1
Manual reset input for SVS-1. Logic low level of this pin asserts RESET1 or RESET1.
WDI
20
Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every 610ms (typ)
prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1 or
RESET1.
NC
11
Not connected. It is recommended to connect this pin to the GND pin (pin 12), which is next to this pin.
(Thermal Pad)
(PAD)
This is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on
the printed circuit board (PCB).
Connecting this pin to VCC through a 40kΩ to
200kΩ resistor, or leaving it open, selects a fixed
delay time (see the Electrical Characteristics).
Connecting a capacitor > 220pF between this pin
and GND selects the programmable delay time
(see the Reset Delay Time section).
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PIN ASSIGNMENTS (continued)
PIN
6
NAME
NO.
DESCRIPTION
RESET1
15
Active low reset output of SVS-1
RESET2
16
Active low reset output of SVS-2
RESET3
17
Active low reset output of SVS-3
RESET4
18
Active low reset output of SVS-4
WDO
19
Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a
low-impedance state to GND. If there is no WDT timeout, this pin stays in a high-impedance state.
RESETn is an open-drain output pin. When
RESETn is asserted, this pin remains in a
low-impedance state. When RESETn is released,
this pin goes to a high-impedance state after the
delay time programmed by CTn.
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TYPICAL CHARACTERISTICS
At TA = +25°C, and VCC = 3.3V, unless otherwise noted.
TPS386000-Q1
SUPPLY CURRENT vs SUPPLY VOLTAGE
TPS386000-Q1
RESETn TIMEOUT Period vs CTn
10000
20
+125°C
+85°C
16
+105°C
RESETn Delay (ms)
18
ICC (mA)
14
12
10
0°C
8
+25°C
-40°C
6
1000
+85°C
100
+25°C
0°C
+125°C
10
4
2
-40°C
NOTE: UVLO released at approximately 1.5V.
0
0
1
2
3
4
VCC (V)
5
6
1
0.0001
7
0.01
CT (mF)
0.1
1
Figure 3.
Figure 4.
TPS386000-Q1
RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn =
Open)
TPS386000-Q1
RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn =
VCC)
25
360
CT1
CT3
340
CT2
15
RESETn Delay (ms)
20
RESETn Delay (ms)
0.001
CT4
10
5
320
CT1
CT3
300
CT2
280
CT4
260
0
240
-50
-30
-10
10
30
50
70
90
110
130
-50
-30
-10
10
Temperature (°C)
30
50
70
90
110
130
Temperature (°C)
Figure 5.
Figure 6.
TPS386000-Q1
RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn =
0.1µF)
TPS386000-Q1
WDO TIMEOUT PERIOD vs TEMPERATURE
550
700
680
660
450
CT3
WDO Delay (ms)
RESETn Delay (ms)
500
CT4
400
CT1
CT2
350
640
VCC = 1.8V
VCC = 3.3V
620
600
580
VCC = 6.5V
560
540
300
NOTE: These curves contain variance of capacitor values.
520
500
250
-50
-30
-10
10
30
50
70
90
110
130
-50
-30
Temperature (°C)
-10
10
30
50
70
90
110
130
Temperature (°C)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, and VCC = 3.3V, unless otherwise noted.
TPS386000-Q1
SENSEn MINIMUM PULSE WIDTH
vs SENSEn THRESHOLD OVERDRIVE VOLTAGE
TPS386000-Q1
SENSE1 THRESHOLD VOLTAGE vs TEMPERATURE
100
408
SENSE4H
10
SENSE4L
SENSE2
SENSE1
SENSE3
1
VITN, (VITN + VHYSN) (mV)
SENSEn Pulse Width (ms)
2mV » 0.5%
406
VITN + VHYSN, VCC = 6.5V
404
VITN + VHYSN, VCC = 1.8V
402
VITN + VHYSN, VCC = 3.3V
VITN, VCC = 6.5V
400
VITN, VCC = 1.8V
VITN, VCC = 3.3V
398
NOTE: See Figure 27 for the measurement technique.
0.1
396
0.1
1
10
100
-50
-30
-10
10
Overdrive (%)
70
90
110
130
Figure 10.
TPS386000-Q1
SENSE2 THRESHOLD VOLTAGE vs TEMPERATURE
TPS386000-Q1
SENSE3 THRESHOLD VOLTAGE vs TEMPERATURE
408
2mV » 0.5%
2mV » 0.5%
406
VITN, (VITN + VHYSN) (mV)
VITN, (VITN + VHYSN) (mV)
50
Figure 9.
408
VITN + VHYSN, VCC = 6.5V
404
VITN + VHYSN, VCC = 1.8V
402
VITN + VHYSN, VCC = 3.3V
400
VITN, VCC = 1.8V
VITN, VCC = 3.3V
398
406
VITN + VHYSN, VCC = 3.3V
VITN + VHYSN, VCC = 6.5V
404
VITN + VHYSN, VCC = 1.8V
402
VITN, VCC = 3.3V
400
VITN, VCC = 6.5V
398
VITN, VCC = 1.8V
VITN, VCC = 6.5V
396
396
-50
-30
-10
10
30
50
70
90
110
130
-50
-30
-10
10
Temperature (°C)
30
50
70
90
110
130
Temperature (°C)
Figure 11.
Figure 12.
TPS386000-Q1
SENSE4L THRESHOLD VOLTAGE vs TEMPERATURE
TPS386000-Q1
SENSE4H THRESHOLD VOLTAGE vs TEMPERATURE
408
404
2mV » 0.5%
2mV » 0.5%
406
VITN + VHYSN, VCC = 3.3V
VITP, (VITP + VHYSP) (mV)
VITN, (VITN + VHYSN) (mV)
30
Temperature (°C)
VITN + VHYSN, VCC = 6.5V
404
VITN + VHYSN, VCC = 1.8V
402
VITN, VCC = 1.8V
400
VITN, VCC = 6.5V
VITN, VCC = 3.3V
398
402
VITP + VHYSP, VCC = 3.3V
VITP + VHYSP, VCC = 6.5V
400
VITP, VCC = 1.8V
398
VITP + VHYSP, VCC = 1.8V
396
VITP, VCC = 6.5V
394
VITP, VCC = 6.5V
396
392
-50
-30
-10
10
30
50
70
90
110
130
-50
-30
Temperature (°C)
10
30
50
70
90
110
130
Temperature (°C)
Figure 13.
8
-10
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, and VCC = 3.3V, unless otherwise noted.
OUTPUT VOLTAGE LOW vs OUTPUT CURRENT
OUTPUT VOLTAGE LOW AT 1mA vs TEMPERATURE
0.200
0.200
All RESETn, RESETn, WDO, and WDO
0.180
0.160
0.160
0.140
0.120
0.100
VCC = 3.3V, +25°C
0.080
0.100
0.080
0.060
0.040
0.040
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VCC = 6.5V
0.020
VCC = 6.5V, +25°C
0
VCC = 3.3V
0.120
0.060
0.020
VCC = 1.8V
0.140
VCC = 1.8V, +25°C
VOL (V)
VOL (V)
All RESETn, RESETn, WDO, and WDO
0.180
0
0.9
1.0
-50
-30
-10
10
Output Sink Current (mA)
30
50
70
90
110
130
Temperature (°C)
Figure 15.
Figure 16.
OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT
OUTPUT VOLTAGE HIGH AT 1mA vs TEMPERATURE
0
0
All RESETn, RESETn, WDO, and WDO
VCC = 6.5V, +25°C
VCC = 6.5V
-0.050
VCC = 1.8V, +25°C
VCC - VOH (V)
VCC - VOH (V)
-0.050
-0.100
VCC = 3.3V, +25°C
-0.150
-0.100
VCC = 3.3V
-0.150
VCC = 1.8V
-0.200
-0.200
All RESETn, RESETn, WDO, and WDO
-0.250
-0.250
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50
-30
-10
10
Output Source Current (mA)
30
50
70
90
110
130
Temperature (°C)
Figure 17.
Figure 18.
TPS386000-Q1
VREF OUTPUT LOAD REGULATION (VCC = 1.8V)
TPS386000-Q1
VREF OUTPUT LOAD REGULATION (VCC = 3.3V)
1.200
1.200
0°C
1.198
1.198
1.196
1.196
+25°C
-40°C
+85°C
1.194
VREF (V)
VREF (V)
0°C
+105°C
+125°C
1.192
+25°C
+85°C
-40°C
+105°C
1.194
+125°C
1.192
1.190
1.190
NOTE: Y-Axis (1.188V to 1.2V) is 1% of 1.2V.
NOTE: Y-Axis (1.188V to 1.2V) is 1% of 1.2V.
1.188
1.188
0
50
100
150
200
250
300
350
400
0
50
100
150
200
Load (mA)
Load (mA)
Figure 19.
Figure 20.
250
300
350
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, and VCC = 3.3V, unless otherwise noted.
TPS386000-Q1
VREF OUTPUT LOAD REGULATION (VCC = 6.5V)
TPS386000-Q1
VREF AT 0µA vs TEMPERATURE
1.207
1.207
NOTE: Y-Axis (1.195V to 1.207V) is 1% of 1.2V.
NOTE: Y-Axis (1.195V to 1.207V) is 1% of 1.2V.
1.205
1.205
0°C
VCC = 6.5V
1.203
VREF (V)
VREF (V)
1.203
1.201
1.199
1.201
VCC = 3.3V
1.199
-40°C
+25°C
+85°C
VCC = 1.8V
+105°C
1.197
1.197
+125°C
1.195
1.195
0
50
100
150
200
250
300
350
400
-50
-30
10
-10
Load (mA)
30
50
70
90
110
130
Temperature (°C)
Figure 21.
Figure 22.
TPS386000-Q1
CT1 TO CT4 PIN CHARGING CURRENT vs TEMPERATURE OVER CT PIN VOLTAGE
0.33
0.32
Current (mA)
0.1V
0.31
0V
0.3V
0.5V
0.30
1.1V
0.29
0.9V
0.7V
0.28
NOTE: Min and max values of Y-axis are ±10% of 0.3mA.
0.27
-50
-30
-10
10
30
50
70
Temperature (°C)
90
110
130
Figure 23.
10
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PARAMETRIC MEASUREMENT INFORMATION
TEST CIRCUIT
SENSEn Voltage (V)
VITN = 0.42V
VITN = 0.4V
Y1
Z1
Y2
X1 =
Z1
´ 100 (%)
0.4
X2 =
Z2
´ 100 (%)
0.4
X1 and X2 are overdrive (%) values calculated
from actual SENSEn voltage amplitudes
measured as Z1 and Z2.
YN is the minimum pulse width that gives
RESETn or RESETn transition.
Greater ZN produces shorter YN.
Z2
For SENSE4H, this graph should be inverted
180° on the voltage axis.
Time
Figure 24.
GENERAL DESCRIPTION
The TPS386000-Q1 multi-channel supervisory device
family combines four complete SVS function sets into
one IC. The design of each SVS channel is based on
the single-channel supervisory device series,
TPS3808. The TPS386000-Q1 is designed to assert
RESETn or RESETn signals, as shown in Table 1,
Table 2, Table 3, and Table 4. The RESETn or
RESETn outputs remain asserted during a
voltage threshold above 0.4V using an external
resistor divider. The SENSE4H pin can be used for
any overvoltage detection greater than 0.4V, or for
negative voltage detection using an external resistor
divider (see the Sensing Voltage Less Than 0.4V
section). A broad range of voltage threshold and
reset delay time adjustments can be supported,
allowing these devices to be used in a wide array of
applications.
user-configurable delay time after the event of reset
release (see the Reset Delay Time section). Each
SENSEm (m = 1, 2, 3, 4L) pin can be set to any
Table 1. SVS-1 Truth Table
OUTPUT
CONDITION
TPS386000-Q1
STATUS
MR = Low
SENSE1 < VITN
RESET1 = Low
Reset asserted
Reset asserted
MR = Low
SENSE1 > VITN
RESET1 = Low
MR = High
SENSE1 < VITN
RESET1 = Low
Reset asserted
MR = High
SENSE1 > VITN
RESET1 = High
Reset released after delay
Table 2. SVS-2 Truth Table
OUTPUT
CONDITION
TPS386000-Q1
STATUS
SENSE2 < VITN
RESET2 = Low
Reset asserted
SENSE2 > VITN
RESET2 = High
Reset released after delay
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Table 3. SVS-3 Truth Table
OUTPUT
CONDITION
TPS386000-Q1
STATUS
SENSE3 < VITN
RESET3 = Low
Reset asserted
SENSE3 > VITN
RESET3 = High
Reset released after delay
Table 4. SVS-4 Truth Table
OUTPUT
CONDITION
TPS386000-Q1
STATUS
SENSE4L < VITN
SENSE4H > VITP
RESET4 = Low
Reset asserted
SENSE4L < VITN
SENSE4H < VITP
RESET4 = Low
Reset asserted
SENSE4L > VITN
SENSE4H > VITP
RESET4 = Low
Reset asserted
SENSE4L > VITN
SENSE4H < VITP
RESET4 = High
Reset released after delay
Table 5. Watchdog Timer (WDT) Truth Table
CONDITION
12
OUTPUT
WDO
WDO
RESET1 OR
RESET1
Low
High
Asserted
Toggling
WDO = low
Remains in WDT
timeout
Low
High
Asserted
610ms after last WDI↑ or WDI↓
WDO = low
Remains in WDT
timeout
Low
High
Released
Toggling
WDO = low
Remains in WDT
timeout
Low
High
Released
610ms after last WDI↑ or WDI↓
WDO = low
Remains in WDT
timeout
High
Low
Asserted
Toggling
WDO = high
Normal operation
High
Low
Asserted
610ms after last WDI↑ or WDI↓
WDO = high
Normal operation
High
Low
Released
Toggling
WDO = high
Normal operation
High
Low
Released
610ms after last WDI↑ or WDI↓
WDO = low
Enters WDT
timeout
WDI PULSE INPUT
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RESET OUTPUT
In a typical TPS386000-Q1 application, RESETn or
RESETn outputs are connected to the reset input of a
processor (DSP, CPU, FPGA, ASIC, etc.), or
connected to the enable input of a voltage regulator
(DC-DC, LDO, etc.)
The TPS386000-Q1 provides open-drain reset
outputs. Pull-up resistors must be used to hold these
lines high when RESETn is not asserted, or when
RESETn is asserted. By connecting pull-up resistors
to the proper voltage rails (up to 6.5V), RESETn or
RESETn output nodes can be connected to the other
devices at the correct interface voltage levels. The
pull-up resistor should be no smaller than 10kΩ
because of the safe operation of the output
transistors. By using wired-OR logic, any combination
of RESETn can be merged into one logic signal.
The TPS386000-Q1 provides push-pull reset outputs.
The logic high level of the outputs is determined by
the VCC voltage. With this configuration, pull-up
resistors are not required and some board area can
be saved. However, all the interface logic levels
should be examined. All RESETn or RESETn
connections must be compatible with the VCC logic
level.
The RESETn or RESETn outputs are defined for
VCC voltage higher than 0.9V. To ensure that the
target processor(s) are properly reset, the VCC
supply input should be fed by the available power rail
as early as possible in application circuits. Table 1,
Table 2, Table 3, and Table 4 are truth tables that
describe how the outputs are asserted or released.
Figure 25, Figure 26, Figure 27, and Figure 28 show
the SVS-n timing diagrams. When the condition(s)
are met, the device changes the state of SVS-n from
asserted to released after a user-configurable delay
time. However, the transitions from released-state to
asserted-state are performed almost immediately with
minimal propagation
relationship between
VHYSN) and SENSEm
SVS-3, and SVS-4
Figure 27.
delay. Figure 27 describes
threshold voltages (VITN and
voltage; and all SVS-1, SVS-2,
have the same behavior of
VCC
0.9V
t
SENSE1
VHYSN
VITN
t
MR
t
RESET1
tD
tD
t
NOTE: The TPS386000-Q1 is shown here using RESETn.
Figure 25. SVS-1 Timing Diagram
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VCC
VCC
0.9V
0.9V
t
SENSE2
t
SENSE3
VHYSN
VITN
VHYSN
VITN
t
RESET2
t
RESET3
tD
tD
tD
t
NOTE: The TPS386000-Q1 is shown here using RESETn.
Figure 26. SVS-2 Timing Diagram
14
t
NOTE: The TPS386000-Q1 is shown here using RESETn.
Figure 27. SVS-3 Timing Diagram
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VCC
MR
0.9V
t
RESET1
t
SENSE4L
t
WDI
VHYSN
VITN
t
t
SENSE4H
(Internal timer)
tWDT
VITP
Timeout
VHYSP
Zero
t
WDO
t
RESET4
t
NOTE: The TPS386000-Q1 is shown here using RESETn and
WDO.
tD
Figure 29. WDT Timing Diagram
t
NOTE: The TPS386000-Q1 is shown here using RESETn.
Figure 28. SVS-4 Timing Diagram
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SENSE INPUT
WINDOW COMPARATOR
The SENSEm inputs are pins that allow any system
voltages to be monitored. If the voltage at the
SENSE1, SENSE2, SENSE3, or SENSE4L pins
drops below VITN, then the corresponding reset
outputs are asserted. If the voltage at the SENSE4H
pin exceeds VITP, then RESET4 or RESET4 is
asserted. The comparators have a built-in hysteresis
to ensure smooth reset output assertions and
deassertions. Although not required in most cases,
for extremely noise applications, it is good analog
design practice to place a 1nF to 10nF bypass
capacitor at the SENSEm input in order to reduce
sensitivity to transients, layout parasitics, and
interference between power rails monitored by this
device. A typical connection of resistor dividers are
shown in Figure 30. All the SENSEm pins can be
used to monitor voltage rails down to 0.4V. Threshold
voltages can be calculated by following equations:
The comparator at the SENSE4H pin has the
opposite comparison polarity to the other SENSEm
pins. In the configuration shown in Figure 30, this
comparator monitors overvoltage of the VCC4 node;
combined with the comparator at SENSE4L, SVS-4
forms a window comparator.
VCC1_target = (1 + RS1H/RS1L) × 0.4 (V)
VCC2_target = (1 + RS2H/RS2L) × 0.4 (V)
VCC3_target = (1 + RS3H/RS3L) × 0.4 (V)
VCC4_target1 = {1+ RS4H/®S4M + RS4L)} × 0.4 (V)
VCC4_target2 = {1+ ®S4H + RS4M)/RS4L} × 0.4 (V)
SENSING VOLTAGE LESS THAN 0.4V
By using voltage reference output VREF, the SVS-4
comparator can monitor negative voltage or positive
voltage lower than 0.4V. Figure 1 shows this usage in
an application circuit. SVS-4 monitors the positive
and negative voltage power rail (for example, +15V
and –15V supply to an op amp) and the RESET4 or
RESET4 output status continues to be as described
in Table 4. Note that RS42H is located at higher
voltage position than RS42L. The threshold voltage
calculations are shown in the following equations:
(1)
(2)
(3)
(4)
(5)
VCC41_target = (1 + RS41H/RS41L) × 0.4 (V)
VCC42_target = (1 + RS42L/RS42H) × 0.4 – RS42L/RS42H ×
VREF
= 0.4 – RS42L/RS42H × 0.8 (V)
(6)
(7)
(8)
Where VCC4_target1 is the undervoltage threshold,
and VCC4_target2 is the overvoltage threshold.
Sequence: VIN
VCC4
VCC3
VCC2
DC-DC
LDO
VIN
VCC1
VCC4
VCC3
VCC2
EN4
DC-DC
LDO
EN3
DC-DC
LDO
VCC1
RS4H
EN2
RP5 RP4 RP3 RP2 RP1
VCC
RS3H
RS2H
DC-DC
LDO
RS1H
MR
VREF
WDI
WDO
SENSE1
VCC1 VCC2 VCC3 VCC4
RESET1
SENSE2
TPS386000
RESET
RESET2
SENSE3
RESET3
SENSE4L
RESET4
DSP
CPU
FPGA
CLK
SENSE4H
CT1
RS4M
CT1
RS4L
RS3L
RS2L
CT2
CT2
CT3
CT3
CT4
GND
CT4
RS1L
Figure 30. Typical Application Circuit (SVS-4: Window Comparator)
16
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RESET DELAY TIME
Each of the SVS-n channels can be configured
independently in one of three modes. Table 6
describes the delay time settings.
Table 6. Delay Timing Selection
CTn CONNECTION
DELAY TIME
Pull-up to VCC
300ms (typ)
Open
20 ms (typ)
Capacitor to GND
Programmable
To control the MR function from more than one logic
signal, the logic signals can be combined by
wired-OR into the MR pin using multiple NMOS
transistors and one pull-up resistor.
WATCHDOG TIMER
To select the 300ms fixed delay time, the CTn pin
should be pulled up to VCC using a resistor from
40kΩ to 200kΩ. Note that there is a pulldown
transistor from CTn to GND that turns on every time
the device powers on to determine and confirm CTn
pin status; therefore, a direct connection of CTn to
VCC causes a large current flow. To select the 20ms
fixed delay time, the CTn pin should be left open. To
program a user-defined adjustable delay time, an
external capacitor must be connected between CTn
and GND. The adjustable delay time can be
calculated by the following equation:
CCT (nF) = [tDELAY (ms) – 0.5(ms)] × 0.242
RESET1 or RESET1 is released after the
user-configured reset delay time. Note that unlike the
TPS3808 series, the TPS386000-Q1 does not
integrate an internal pull-up resistor between MR and
VCC.
(9)
Using this equation, a delay time can be set to
between 1.4ms to 10s. The external capacitor should
be greater than 220pF (nominal) so that the
TPS386000-Q1 can distinguish it from an open CT
pin. The reset delay time is determined by the time it
takes an on-chip, precision 300nA current source to
charge the external capacitor to 1.24V. When the
RESETn or RESETn outputs are asserted, the
corresponding capacitors are discharged. When the
condition to release RESETn or RESETn occurs, the
internal current sources are enabled and begin to
charge the external capacitors. When the CTn
voltage on a capacitor reaches 1.24V, the
corresponding RESETn or RESETn pins are
released. Note that a low leakage type capacitor
(such as ceramic) should be used, and that stray
capacitance around this pin may cause errors in the
reset delay time.
MANUAL RESET
The manual reset (MR) input allows external logic
signal from other processors, logic circuits, and/or
discrete sensors to initiate a device reset. Because
MR is connected to SVS-1, the RESET1 or RESET1
pin is intended to be connected to processor(s) as a
primary reset source. A logic low at MR causes
RESET1 or RESET1 to assert. After MR returns to a
logic high and SENSE1 is above its reset threshold,
The TPS386000-Q1 provides a watchdog timer with a
dedicated watchdog error output, WDO or WDO. The
WDO or WDO output enables application board
designers to easily detect and resolve the hang-up
status of a processor. As with MR, the watchdog
timer function of the device is also tied to SVS-1.
Figure 29 shows the timing diagram of the WDT
function. Once RESET1 or RESET1 is released, the
internal watchdog timer starts its countdown. Inputting
a logic level transition at WDI resets the internal timer
count and the timer restarts the countdown. If the
TPS386000-Q1 fails to receive any WDI rising or
falling edge within the WDT period, the WDT times
out and asserts WDO or WDO. After WDO or WDO is
asserted, the device holds the status with the internal
latch circuit. To clear this timeout status, a reset
assertion of RESET1 or RESET is required. That is, a
negative pulse to MR, a SENSE1 voltage less than
VITN, or a VCC power-down is required.
To reset the processor by WDT timeout, WDO can be
combined with RESET1 by using the wired-OR with
the TPS386000-Q1 option.
For legacy applications where the watchdog timer
timeout causes RESET1 to assert, connect WDO to
MR; see Figure 30 for the connections and see
Figure 31 and Figure 32 for the timing diagram. This
legacy support configuration is available with the
TPS386000-Q1.
IMMUNITY TO SENSEn VOLTAGE
TRANSIENTS
The TPS386000-Q1 is relatively immune to short
negative transients on the SENSEn pin. Sensitivity to
transients depends on threshold overdrive, as shown
in the typical performance graph TPS386000-Q1
SENSEn Minimum Pulse Width vs SENSEn
Threshold Overdrive Voltage (Figure 9).
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WDI
Event 1
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Event 2
WDI
Event 3
Event 1
t
RESET1
RESET1
t
MR = WDO
MR = WDO
tD
tWDT
t
(Internal timer)
(Internal timer)
t
Figure 31. Legacy WDT Configuration Timing
Diagram
18
Figure 32. Enlarged View of Event 1 from
Figure 31
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2010
PACKAGING INFORMATION
Orderable Device
TPS386000QRGPRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
QFN
RGP
Pins
Package Qty
20
3000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS386000-Q1 :
• Catalog: TPS386000
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS386000QRGPRQ1
Package Package Pins
Type Drawing
QFN
RGP
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS386000QRGPRQ1
QFN
RGP
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
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