IN74HC10 TRIPLE 3-INPUT NAND GATE High-Performance Silicon-Gate CMOS • • • • The IN74HC10 is identical in pinout to the LS/ALS10. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC10N Plastic IN74HC10D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Output A B C Y L X X H X L X H X X L H H H H L X = don’t care PIN 14 =VCC PIN 7 = GND 1 IN74HC10 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±25 ICC DC Supply Current, VCC and GND Pins mA ±50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure VCC =4.5 V 1) VCC =2.0 V VCC =6.0 V Min 2.0 0 Max 6.0 VCC Unit V V -55 0 0 0 +125 1000 500 400 °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HC10 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V ≤85 ≤125 25 °C to °C °C -55°C 1.5 1.5 1.5 VIH Minimum High- VOUT=0.1 V or VCC-0.1 V 2.0 3.15 3.15 3.15 Level Input IOUT≤ 20 µA 4.5 4.2 4.2 4.2 Voltage 6.0 0.3 0.3 0.3 VIL Maximum Low - VOUT=0.1 V or VCC-0.1 V 2.0 0.9 0.9 0.9 Level Input IOUT ≤ 20 µA 4.5 1.2 1.2 1.2 Voltage 6.0 1.9 1.9 1.9 VOH Minimum High- VIN=VIH or VIL 2.0 4.4 4.4 4.4 Level Output IOUT ≤ 20 µA 4.5 5.9 5.9 5.9 Voltage 6.0 VIN=VIH or VIL 3.7 3.84 3.98 IOUT ≤ 4.0 mA 4.5 5.2 5.34 5.48 6.0 IOUT ≤ 5.2 mA 0.1 0.1 0.1 VOL Maximum Low- VIN=VIH 2.0 0.1 0.1 0.1 Level Output IOUT ≤ 20 µA 4.5 0.1 0.1 0.1 Voltage 6.0 VIN=VIH 0.4 0.33 0.26 IOUT ≤ 4.0 mA 4.5 0.4 0.33 0.26 6.0 IOUT ≤ 5.2 mA IIN Maximum Input VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 Leakage Current VIN=VCC ICC Maximum or GND 6.0 2.0 20 40 Quiescent Supply IOUT=0µA Current (per Package) 3 Unit V V V V µA µA IN74HC10 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C ≤85°C ≤125° C to -55°C 145 120 95 tPLH, Maximum Propagation Delay, Input A,B 2.0 29 24 19 tPHL or C to Output Y (Figures 1 and 2) 4.5 25 20 16 6.0 110 95 75 tTLH, tTHL Maximum Output Transition Time, Any 2.0 22 19 15 4.5 Output 19 16 13 6.0 (Figures 1 and 2) CIN Maximum Input Capacitance 10 10 10 CPD Power Dissipation Capacitance (Per Gate) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Unit ns ns pF Typical @25°C,VCC=5.0 V 25 pF Figure 2. Test Circuit EXPANDED LOGIC DIAGRAM (1/3 of the Device) 4