CY7B995 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer Features Description • 2.5V or 3.3V operation The CY7B995 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems. • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 100 ps • Cycle-cycle jitter <100 ps • ± 2% max output duty cycle • Selectable output drive strength • Selectable positive or negative edge synchronization • Eight LVTTL outputs driving 50Ω terminated lines • LVCMOS/LVTTL over-voltage tolerant reference input • Selectable phase-locked loop (PLL) frequency range and lock indicator • Phase adjustments in 625/1250 ps steps up to ± 7.5 ns • (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios • Spread-Spectrum-compatible • Power-down mode The user can program both the frequency and the phase of the output banks through nF[0:1] and DS[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA (3.3V). • Selectable reference divider • Industrial temperature range: -40°C to +85°C • 44-pin TQFP package Block Diagram Pin Configuration LOCK 3 DS1:0 1F1:0 3 3 1Q0 Phase Select 1Q1 2Q0 3 2F1:0 3F1:0 3 3 3 Phase Select 2Q1 3Q0 Phase Select and /K 4F1 1 sOE# 2 PD#/DIV 3 PE/HD 4 VDDQ4 5 VDDQ4 6 4Q1 7 4Q0 8 VSS 9 VSS 10 VSS 11 3 4Q0 Phase Select and /M 1F1 VSS TES T 2F1 2F0 30 LOCK 29 VDDQ1 CY7B995 28 VDDQ1 27 1Q0 26 1Q1 VSS 3 4Q1 33 1F0 32 DS1 31 DS0 12 13 14 15 16 17 18 19 20 21 22 3Q1 VDDQ3 4F1:0 44 43 42 41 40 39 38 37 36 35 34 25 VSS 24 VSS 23 VSS 2Q1 2Q0 VSS 3 VDD VDDQ1 FB /N FS VDD REF 3 3F1 3F0 3 PLL 3Q0 VDDQ3 3 /R REF 4F0 3 3Q1 PD#/DIV FS VDDQ1 VDDQ3 FB TEST PE/HD VDDQ4 sOE# Cypress Semiconductor Corporation Document #: 38-07337 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 24, 2004 CY7B995 Pin Description Pin Name I/O[1] Type Description 39 REF I LVTTL/LVCMOS Reference Clock Input. 17 FB I LVTTL Feedback Input. 37 TEST I 3-Level When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. 2 4 sOE# PE/HD I, PD LVTTL Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. I, PU 3-Level Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative / positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock. Please see Table 9. 34, 33, 36, 35, nF[1:0] 43, 42, 1, 44 I 3-Level Select frequency and phase of the outputs. Please see Tables 3, 4, 5, 7, and 8. 41 FS I 3-Level Selects VCO operating frequency range. Please see Table 6. 26,27,20,21, 13,14,7,8 nQ[1:0] O LVTTL Four banks of two outputs. Please see Table 5 for frequency settings. 32, 31 DS[1:0] I 3-Level 3 PD#/DIV 30 LOCK LVTTL PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the input. 5,6 VDDQ4[2] PWR Power Power supply for Bank 4 output buffers. Please see Table 10 for supply level constraints 15,16 VDDQ3 [2] PWR Power Power supply for Bank 3 output buffers. Please see Table 10 for supply level constraints 19,28,29 VDDQ1[2] PWR Power Power supply for Bank 1 and Bank 2 output buffers. Please see Table 10 for supply level constraints 18,40 VDD[2] PWR Power Power supply for the internal circuitry. Please see Table 10 for supply level constraints PWR Power Ground. 9-12, 22-25, 38 VSS I, PU 3-Level Select feedback divider. Please see Table 2. Power down and reference divider control. When LOW, shuts off entire chip. When at MID level, enables the reference divider. Please see Table 1 for settings. O Device Configuration The outputs of the CY7B995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 2 and the reference input divider is controlled by the 3-level PD#/DIV pin as indicated in Table 1. Table 1. Reference Divider Settings PD#/DIV R–Reference Divider H 1 M 2 L[4] N/A Notes: 1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. Document #: 38-07337 Rev. *A Page 2 of 11 CY7B995 Table 2. Feedback Divider Settings The divider settings and the FB input to ANY output connection needed to produce various output frequencies are summarized in Table 5. DS[1:0] N-Feedback Input Divider Permitted Output Divider Connected to FB LL 2 1 or 2 LM 3 1 Configuration FB Input Connected to LH 4 1,2 or 4 ML 5 1 or 2 MM 1 1,2 or 4 MH 6 1 or 2 HL 8 1 or 2 HM 10 1 HH 12 1 In addition to the reference and feedback dividers, the CY7B995 includes output dividers on Bank3 and Bank4, which are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively. Table 3. Output Divider Settings – Bank 3 3F[1:0] K - Bank3 Output Divider LL 2 HH 4 Other[5] 1 Table 4. Output Divider Settings – Bank 4 Table 5. Output Frequency Settings Output Frequency 1Q[0:1] and 2Q[0:1][6] 3Q[0:1] 4Q[0:1] (N / R) x (1 / (N / R) x (1 / K) x FREF M) x FREF (N / R) x (K / (N / R) x K x (N / R) x FREF M) x FREF FREF 1Qn or 2Qn (N / R) x FREF 3Qn (N / R) x M x (N / R) x (M / (N / R) x FREF K) x FREF FREF 4Qn The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY7B995 PLL operating frequency range that corresponds to each FS level is given in Table 6. Table 6. Frequency Range Select FS PLL Frequency Range L 24 to 50MHz M 48 to 100MHz H 96 to 200MHz Selectable output skew is in discrete increments of time unit (tU).The value of tU is determined by the FS setting and the maximum nominal frequency. The equation to be used to determine the tU value is as follows: 4F[1:0] M- Bank4 Output Divider LL 2 tU = 1 / (fNOM x MF) Other[5] 1 where MF is a multiplication factor, which is determined by the FS setting as indicated in Table 7.I Table 7. MF Calculation FS MF fNOM at which tU is 1.0ns(MHz) L 32 31.25 M 16 62.5 H 8 125 Notes: 4. When PD#/DIV = LOW, the device enters power-down mode 5. These states are used to program the phase of the respective banks. Please see Table 7 and Table 8. 6. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference frequency (FREF) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Please see Table 6. Document #: 38-07337 Rev. *A Page 3 of 11 CY7B995 Table 8. Output Skew Settings The CY7B995 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. Skew (1Q[0:1],2Q[0:1]) Skew (3Q[0:1]) Skew (4Q[0:1]) LL[7] –4tU Divide By 2 Divide By 2 LM –3tU –6tU –6tU LH –2tU –4tU –4tU ML –1tU –2tU –2tU MM Zero Skew Zero Skew Zero Skew MH +1tU +2tU +2tU HL +2tU +4tU +4tU Governing Agencies HM +3tU +6tU +6tU HH +4tU Divide By 4 Inverted[8] The following agencies provide specifications that apply to the CY7B995. The agency name and relevant specification is listed below. nF[1:0] In addition to determining whether the outputs synchronize to the rising or the falling edge of the reference signal, the 3-level PE/HD pin controls the output buffer drive strength as indicated in Table 9. Table 9. PE/HD Settings PE/HD Synchronization Output Drive Strength[9] L Negative Low Drive M Positive High Drive H Positive Low Drive Table 10.Power Supply Constraints VDD VDDQ1[10] VDDQ3[10] VDDQ4[10] 3.3V 3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V 2.5V 2.5V 2.5V 2.5V Table 11. Agency Name Specification JEDEC JESD 51 (Theta JA) JESD 65 (Skew, Jitter) IEEE 1596.3 (Jiter Specs) UL-194_V0 94 (Moisture Grading) MIL 883E Method 1012.1 (Therma Theta JC) Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Operating Voltage Functional @ 2.5V ± 5% 2.25 2.75 V VDD Operating Voltage Functional @ 3.3V ± 10% 2.97 3.63 V VIN(MIN) Input Voltage Relative to VSS VSS–0.3 – V VIN(MAX) Input Voltage Relative to VDD – VDD+0.3 V VREF(MAX) Reference Input Voltage VDD = 3.3V 5.5 V VREF(MAX) Reference Input Voltage VDD = 2.5V 4.6 V TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – 155 °C ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 42 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 74 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level FIT Failure in Time V–0 1 Manufacturing Testing 10 ppm Notes: 7. LL disables outputs if TEST = MID and sOE# = HIGH. 8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW. 9. Please refer to “DC Parameters” section for IOH/IOL specifications. 10. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V. Document #: 38-07337 Rev. *A Page 4 of 11 CY7B995 DC Specifications @ 2.5V . Parameter Description VDD 2.5 Operating Voltage VIL Input LOW Voltage VIH Input HIGH Voltage VIHH[11] Input HIGH Voltage VIMM[11] Input MID Voltage VILL[11] Input LOW Voltage IIL Input Leakage Current Conditions 2.5V ± 5% 3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD). (These pins are normally wired to VDD, GND, or unconnected) Unit 2.375 2.625 V – 0.7 V 1.7 – V VDD – –0.4 – V VDD/2 – 0.2 VDD/2 + 0.2 V – 0.4 V VIN = VDD/GND,VDD = Max; (REF and FB inputs) –5 5 µA HIGH, VIN = VDD – 200 µA –50 50 µA 3-Level Input DC Current MID, VIN = VDD/2 LOW, VIN = VSS IPU Input Pull-Up Current VIN = VSS, VDD = Max IPD Input Pull-Down Current Output LOW Voltage Max. REF, FB and sOE# Inputs I3 VOL Min. 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) –200 – µA –25 – µA VIN = VDD, VDD = Max, (sOE#) – 100 µA IOL = 12mA (PE/HD = L/H), (nQ[0:1]) – 0.4 V IOL = 20mA (PE/HD = MID),(nQ[0:1]) – IOL = 2mA (LOCK) VOH Output HIGH Voltage 0.4 V 0.4 V IOH = –12mA (PE/HD = L/H),(nQ[0:1]) 2.0 – V IOH = –20mA (PE/HD = MID),(nQ[0:1]) 2.0 – V IOH = –2mA (LOCK) 2.0 IDDQ VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Quiescent Supply Current Outputs not loaded IDDPD Power-down Current PD#/DIV, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH; VDD = Max IDD Dynamic Supply Current @100MHz CIN Input Pin Capacitance V – 2 mA 10(typ.) 25 µA 150 mA 4 pF DC Specifications @ 3.3V Parameter Description VDD 3.3 Operating Voltage VIL Input LOW Voltage VIH Input HIGH Voltage VIHH[11] Input HIGH Voltage VIMM[11] VILL[11] Input MID Voltage IIL Input Leakage Current Input LOW Voltage Condition 3.3V ± 10% REF, FB and sOE# Inputs Max. Unit 2.97 3.63 V – 0.8 V 2.0 – V 3-Level Inputs VDD– –0.6 – (TEST, FS, nF[1:0], DS[1:0],PD#/DIV, V /2 – 0.3 V /2 + 0.3 DD DD PE/HD); (These pins are normally – 0.6 wired to VDD,GND or unconected V VIN = VDD/GND,VDD = Max (REF and FB inputs) –5 5 µA HIGH, VIN = VDD – 200 µA –50 50 µA –200 – µA MID, VIN = VDD/2 I3 Min. 3-Level Input DC Current LOW, VIN = VSS 3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) IPU Input Pull-Up Current VIN = VSS, VDD = Max IPD Input Pull-Down Current VIN = VDD, VDD = Max, (sOE#) V V –25 – µA – 100 µA Note: 11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. Document #: 38-07337 Rev. *A Page 5 of 11 CY7B995 DC Specifications @ 3.3V (continued) Parameter VOL Description Output LOW Voltage Condition Min. Max. Unit IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) – 0.4 V IOL = 24 mA (PE/HD = MID),(nQ[0:1]) – 0.4 V 0.4 V IOL = 2 mA (LOCK) VOH Output HIGH Voltage IOH = –12 mA (PE/HD = L/H),(nQ[0:1]) 2.4 – V IOH = –24 mA (PE/HD = MID),(nQ[0:1]) 2.4 – V IOH = –2 mA (LOCK) 2.4 IDDQ Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded IDDPD Power Down Current PD#/DIV, sOE# = LOW, Test,nF[1:0],DS[1:0] = HIGH, VDD = Max IDD Dynamic Supply Current @100 MHz CIN Input Pin Capacitance V – 2 mA 10(typ.) 25 µA 230 mA 4 pF AC Input Specifications Parameter Description Condition TR,TF Input Rise/Fall Time 0.8V – 2.0V TPWC Input Clock Pulse HIGH or LOW TDCIN Input Duty Cycle FREF Reference Input Frequency[12] Min. Max. Unit – 10 ns/V 2 – ns 10 90 % FS = LOW 2 50 FS = MID 4 100 FS = HIGH 8 200 Min. Max. Unit 6 200 MHz MHz Switching Characteristics Parameter Description Condition FOR Output frequency range VCOLR VCO Lock Range 200 400 MHz VCOLBW VCO Loop Bandwidth 0.25 3.5 MHz tSKEWPR Matched-Pair Skew[13] Skew between the earliest and the latest output transitions within the same bank. – 100 ps tSKEW0 Skew between the earliest and the latest output transitions among all outputs at 0tU. – 200 ps tSKEW1 Skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. – 200 ps tSKEW2 Skew between the nominal output rising edge to the inverted output falling edge – 500 ps tSKEW3 Skew between non-inverted outputs running at different frequencies – 500 ps Skew between nominal to inverted outputs running at different frequencies – 500 ps Skew between nominal outputs at different power supply levels – 650 ps Output-Output Skew[13] tSKEW4 [13] Output-Output Skew tSKEW5 Notes: 12. IF PD#/DIV is in HIGH level (R-reference divider = 1). Reference Input Frequency = FREF. IF PD#/DIV is in MID level (R-reference divider = 2). Reference Input Frequency = FREFx2. 13. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded. Document #: 38-07337 Rev. *A Page 6 of 11 CY7B995 Switching Characteristics (continued) Parameter Description tPART Part-Part Skew tPD0 Ref to FB Propagation Delay[14] tODCV Output Duty Cycle tPWH Condition Skew between the outputs of any two devices under identical settings and conditions (VDDQ, VDD, temp, air flow, frequency, etc.) Min. Max. Unit – 750 ps –250 +250 ps Fout < 100 MHz, Measured at VDD/2 48 52 Fout > 100 MHz, Measured at VDD/2 45 55 Output High Time Deviation from 50% Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. – 1.5 ns tPWL Output Low Time Deviation from 50% Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. – 2.0 ns tR/tF Output Rise/Fall Time Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V–1.7V for VDD = 2.5V 0.15 1.5 ns tLOCK PLL lock time[15,16] tCCJ Cycle-Cycle Jitter % – 0.5 ms Divide by 1 output frequency, FS = L, FB = divide by any – 100 ps Divide by 1 output frequency, FS = M/H, FB = divide by any – 150 ps Notes: 14. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V–2.0V. 15. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 16. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter. Document #: 38-07337 Rev. *A Page 7 of 11 CY7B995 AC Timing Definitions tREF tPWL tPWH REF tPD t0DCV t0DCV FB tCCJ1-12 Q tSKEWPR tSKEW0,1 tSKEWPR tSKEW0,1 OTHER Q tSKEW1 tSKEW1 INVERTED Q tSKEW3 tSKEW3 tSKEW3 REF DIVIDED BY 2 tSKEW1,3,4 tSKEW1,3,4 REF DIVIDED BY 4 Document #: 38-07337 Rev. *A Page 8 of 11 CY7B995 AC TEST LOADS AND WAVEFORMS VDDQ Output 150Ω 20pF Output 20pF 150Ω For Lock Output For All Other Outputs Figure 1. tORISE tORISE tOFALL tPWH 2.0V tOFALL tPWH 1.7V VTH =1.25V VTH =1.5V tPWL 0.8V tPWL 0.7V 2.5V LVTTL OUTPUT WAVEFORM 3.3V LVTTL OUTPUT WAVEFORM Figure 2. ≤ 1ns ≤ 1ns ≤ 1ns ≤ 1ns 2.5V 3.0V 1.7V 2.0V VTH =1.25V VTH =1.5V 0.7V 0V 0.8V 0V 2.5V LVTTL INPUT TEST WAVEFORM 3.3V LVTTL INPUT TEST WAVEFORM Figure 3. Ordering Information Part Number Package Type Product Flow CY7B995AC 44 TQFP Commercial, 0° to 70°C CY7B995ACT 44 TQFP – Tape and Reel Commercial, 0° to 70°C CY7B995AI 44 TQFP Industrial, –40° to 85°C CY7B995AIT 44 TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07337 Rev. *A Page 9 of 11 CY7B995 Package Drawing and Dimension 44-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB 51-85155*A RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07337 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7B995 Document History Page Document Title:CY7B995 Roboclock® 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer Document Number: 38-07337 REV. ECN No. Issue Date Orig. of Change ** 122626 01/10/03 RGL New Data Sheet *A 205743 See ECN RGL Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29 from VDD to VDDQ1 Added pin 1 indicator in the Pin Configuration Drawing Document #: 38-07337 Rev. *A Description of Change Page 11 of 11