PRELIMINARY W161 133-MHz Spread Spectrum FTG for Pentium® II Platforms Features Spread Spectrum Modulation:..................................... –0.5% • Maximized EMI Suppression using Cypress’s Spread Spectrum Technology • Three copies of CPU outputs at 100 or 133 MHz • Three copies of 66-MHz output at 3.3V • Ten copies of PCI clocks at 33 MHz, 3.3V • Two copies of 14.318-MHz reference output at 3.3V • One copy of 48-MHz USB clock • One copy of CPU-divide-by-2 output as reference input to Direct Rambus™ Clock Generator (Cypress W134) • Available in 48-pin SSOP (300 mils) CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads) 3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads) CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads) Table 1. Pin Selectable Frequency SEL133/100# SEL1 SEL0 Function 0 0 0 All outputs Three-State 0 0 1 (Reserved) 0 1 0 Active 100-MHz, 48-MHz PLL inactive Key Specifications 0 1 1 Active 100-MHz, 48-MHz PLL active Supply Voltages: ...................................... VDDQ2 = 2.5V±5% VDDQ3 = 3.3V±5% 1 0 0 Test Mode 1 0 1 (Reserved) 1 1 0 Active 133-MHz, 48-MHz PLL inactive 1 1 1 Active 133-MHz, 48-MHz PLL active CPU, CPUdiv2 Output Jitter:....................................... 250 ps CPU, CPUdiv2 Output Skew: ...................................... 175 ps IOAPIC, 3V66 Output Skew: ....................................... 250 ps PCI0:9 Output Skew: .................................................. 500 ps Duty Cycle: ................................................................... 45/55 Pin Configuration [1] Block Diagram X1 X2 2 XTAL OSC 3 CPU_[0:2] SPREAD# SEL0 ÷2 CPUdiv2 PLL 1 SEL1 3 SEL133/100# 3V66_[0:2] ÷2/÷1.5 9 ÷2 PWRDWN# Power Down Logic PCI_[0:9] ÷2 IOAPIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W161 REF0 REF1 VDDQ3 X1 X2 GND PCI0 PCI1 VDDQ3 PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDDQ3 PCI8 PCI9 GND 3V66_0 3V66_1 3V66_2 VDDQ3 REF_[0:1] 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND VDDQ2 IOAPIC GND VDDQ2 CPUdiv2 GND VDDQ2 CPU2 GND VDDQ2 CPU1 CPU0 GND VDDQ3 GND PWRDWN#* SPREAD#* SEL1* SEL0* VDDQ3 48MHz GND SEL133/100# Note: 1. Internal 250-kΩ pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. Three-state Logic PLL2 48MHz Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 13, 1999, rev. ** PRELIMINARY W161 Pin Definitions Pin No. Pin Type CPU0:2 36, 37, 40 O CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage swing is controlled by voltage applied to VDDQ2. PCI0:9 7, 8, 10, 11, 12, 13, 15, 16, 18, 19 O PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. CPUdiv2 43 O CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134). The output voltage is determined by VDDQ2. 3V66_0:2 21, 22, 23 O 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. IOAPIC 46 O I/O APIC Clock Output: Provides an output synchronous to CPU clock. See Table 1 for their relation to other system clock outputs. 48 MHz 27 O 48-MHz Output: Fixed clock output at 48 MHz. SPREAD# 31 I Spread Spectrum Enable: This input enables spread spectrum modulation on the PLL1 generated frequency outputs of the W161. Modulation range is –0.5%. PWRDWN# 32 I Power Down Control REF0:1 1, 2 I Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by voltage applied to VDDQ3. SEL0:1 29, 30 I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output modes. As shown in Table 1. SEL133/100# 25 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Pin Name Pin Description VDDQ2 38, 41, 44, 47 P Power Connection: Connected to 2.5V power supply. VDDQ3 3, 9, 17, 24, 28, 34 P Power Connection: Connected to 3.3V power supply. GND 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 G Ground Connection: Connect all ground pins to the common system ground plane. Overview Crystal Oscillator The W161 requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The W161, a motherboard clock synthesizer, provides 2.5V CPU clock outputs for advanced CPU and a CPU-divide-by-2 reference frequency for Direct Rambus Clock Generator (such Cypress W134) interface. Fixed output frequencies are provided for other system functions. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W161 incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference frequency accuracies within ±100 ppm. CPU Frequency Selection CPU frequency is selected with input pins 25, 29, and 30 (SEL133/100#, SEL0, and SEL1, respectively). Refer to Table 1 for details. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W161 outputs are CMOS-type, which provide rail-to-rail output swing. 2 PRELIMINARY W161 Spread Spectrum Feature Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is –0.5% downspread. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Time Figure 2. Typical Modulation Profile 3 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift Figure 1. Typical Clock and SSFTG Comparison PRELIMINARY W161 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 2 (min.) kV TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias ESDPROT Input ESD Protection DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD-3.3V Combined 3.3V Supply Current CPU0:3 =133 MHz[2] 160 mA IDD-2.5 Combined 2.5V Supply Current CPU0:3 =133 MHz[2] 90 mA GND – 0.3 0.8 V 2.0 VDD + 0.3 V –25 µA 10 µA –5 µA 5 µA Max. Unit 50 mV Logic Inputs (All referenced to VDDQ3 = 3.3V) Input Low Voltage VIL VIH Input High Voltage IIL Input Low Current[3] IIH IIL IIH [3] Input High Current [3] Input Low Current, SEL133/100# [3] Input High Current, SEL133/100# Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) Test Condition Min. Typ. VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 2.2 IOL Output Low Current VOL = 1.25V 45 65 100 mA IOH Output High Current VOH = 1.25V 45 65 100 mA Min. Typ. Max. Unit 50 mV 48MHz, REF (Referenced to VDDQ3) Test Condition V VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 45 65 100 mA IOH Output High Current VOH = 1.5V 45 65 100 mA Min. Typ. Max. Unit 50 mV PCI, 3V66 (Referenced to VDDQ3) Test Condition V VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 70 100 145 mA IOH Output High Current VOH = 1.5V 65 95 135 mA Notes: 2. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 3. W161 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level). 4 V PRELIMINARY W161 DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input threshold Voltage[4] CLOAD Load Capacitance, Imposed on External Crystal[5] CIN,X1 X1 Input Capacitance[6] Pin X2 unconnected 1.65 V 18 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Except X1 and X2 5 pF 3.3V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[7] 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. 66.6 Unit f Frequency Note 8 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 MHz Ω Notes: 4. X1 input threshold voltage (typical) is VDD/2. 5. The W161 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Period, jitter, offset, and skew measured on rising edge at 1.5V. 8. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz. 5 PRELIMINARY W161 PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments [9] Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps Output Skew Measured on rising edge at 1.5V. 500 ps tO 3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. 3 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.5 Ω 15 REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 25 48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Note: 9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz. 6 48.008 MHz +167 ppm 57/17 25 Ω PRELIMINARY W161 2.5V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, V DDQ2= 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[10] CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 7.5 tH High Time Duration of clock cycle above 2.0V 1.87 3.0 ns tL Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms 7.65 10 10.2 ns CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 15 tH High Time Duration of clock cycle above 2.0V 5.25 7.5 ns tL Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.25V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Note: 10. Period, Jitter, offset. and skew measured on rising edge at 1.25V. 7 15.3 1 4 20 20 20.4 1 ns 4 V/ns 1 4 V/ns 45 55 % 250 250 ps 175 175 ps 3 3 ms 20 Ω PRELIMINARY W161 IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments f Frequency Note 11 tR Output Rise Edge Rate Measured from 0.4V to 2.0V tF Output Fall Edge Rate Measured from 2.0V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.25V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information W161 Package Name H Typ Max 16.67 Note: 11. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz. Ordering Code Min Package Type 48-pin SSOP (300 mils) Document #: 38-00817 8 1 Unit MHz 4 V/ns 1 4 V/ns 45 55 % 3 ms 20 Ω PRELIMINARY W161 Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.