CYPRESS CY7C1041BNV33

1CY7C1041BNV33
CY7C1041BNV33
256K x 16 Static RAM
Features
Functional Description
• High speed
The CY7C1041BNV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
— tAA = 12 ns
• Low active power
— 612 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BNV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
I/O0 – I/O7
I/O8 – I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 001-06434 Rev. **
•
198 Champion Court
•
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
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CY7C1041BNV33
Selection Guide
-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
12
15
190
170
Ind’l
-
190
Com’l/Ind’l
8
8
0.5
0.5
Comm’l
Maximum CMOS Standby Current (mA)
-15
Com’l
L
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Range
Ambient
Temperature[2]
VCC
0°C to +70°C
3.3V ± 0.3V
Commercial
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range
-12
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
Min.
-15
Max.
2.4
Min.
Max.
Unit
2.4
0.4
V
0.4
V
VIH
Input HIGH Voltage
2.2
VCC+0.5
2.2
VCC+0.5
V
VIL
Input LOW Voltage[1]
–0.5
0.8
–0.5
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
mA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
mA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
190
170
mA
-
190
mA
Comm’l
Ind’l
ISB1
Automatic CE Power-Down Max. VCC, CE > VIH
Current —TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
40
40
mA
ISB2
Automatic CE Power-Down Max. VCC, CE > VCC – 0.3V, Com’l/Ind’l
Current —CMOS Inputs
VIN > VCC – 0.3V,or
Com’l L
VIN < 0.3V, f = 0
8
8
mA
0.5
0.5
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz, VCC = 3.3V
Unit
8
pF
8
pF
AC Test Loads and Waveforms
R1 317Ω
3.3V
ALL INPUT PULSES
THÉVENIN EQUIVALENT
3.3V
167Ω
OUTPUT
R2
351Ω
30 pF
INCLUDING
JIG AND
SCOPE
90%
1.73V
OUTPUT
(b)
GND
Rise time: 1 V/ns
(a)
10%
90%
10%
Fall time:
1 V/ns
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06434 Rev. **
Page 2 of 8
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CY7C1041BNV33
Switching Characteristics[4] Over the Operating Range
-12
Parameter
Description
Min.
-15
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
15
12
ns
15
3
3
ns
ns
tACE
CE LOW to Data Valid
12
15
ns
tDOE
OE LOW to Data Valid
6
7
ns
tLZOE
OE LOW to Low Z
0
[5, 6]
OE HIGH to High Z
tHZOE
[6]
tLZCE
CE LOW to Low Z
tHZCE
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
6
3
ns
7
ns
7
ns
3
6
0
ns
0
12
6
0
Byte Disable to High Z
tHZBE
0
ns
15
ns
7
ns
0
6
ns
7
ns
[7, 8]
WRITE CYCLE
tWC
Write Cycle Time
12
15
ns
tSCE
CE LOW to Write End
10
12
ns
tAW
Address Set-Up to Write End
10
12
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
0
0
ns
[6]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z[5, 6]
tBW
Byte Enable to End of Write
3
3
6
ns
7
10
12
ns
ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
VDR
tR[9]
Conditions[10]
VCC for Data Retention
ICCDR
tCDR
Description
[3]
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Min.
Max.
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Unit
V
330
µA
0
ns
tRC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
9. tr < 3 ns for the -12 and -15 speeds.
10. No input may exceed VCC + 0.5V.
Document #: 001-06434 Rev. **
Page 3 of 8
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CY7C1041BNV33
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06434 Rev. **
Page 4 of 8
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CY7C1041BNV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Notes:
14. Data I/O is high-impedance if OE or BHE and/or BLE= VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state.
Document #: 001-06434 Rev. **
Page 5 of 8
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CY7C1041BNV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
L
I/O0–I/O7
I/O8–I/O15
Mode
Power
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
12
15
Ordering Code
CY7C1041BNV33-12VXC
CY7C1041BNV33L-12VXC
CY7C1041BNV33L-12VC
CY7C1041BNV33L-12ZC
CY7C1041BNV33L-12ZXC
CY7C1041BNV33-15VXC
CY7C1041BNV33L-15VXC
CY7C1041BNV33L-15ZXC
CY7C1041BNV33-15VXI
Package
Diagram
51-85082
51-85082
51-85082
51-85087
51-85087
51-85082
51-85082
51-85087
51-85082
Package Type
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44 (Pb-free)
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Pin TSOP II Z44 (Pb-free)
44-Lead (400-Mil) Molded SOJ (Pb-free)
Operating
Range
Commercial
Commercial
Industrial
Please contact local sales representative regarding availability of these parts.
Document #: 001-06434 Rev. **
Page 6 of 8
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CY7C1041BNV33
Package Diagrams
44-Lead (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-Pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06434 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1041BNV33
Document History Page
Document Title: CY7C1041BNV33 256K x 16 Static RAM
Document Number: 001-06434
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
423877
See ECN
NXR
Document #: 001-06434 Rev. **
Description of Change
New Data Sheet
Page 8 of 8
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