1 W234 Dual Direct Rambus™ Clock Generator Features Overview • Differential clock source for Direct Rambus™ memory subsystem for up to 1.6-Gb/s serial data transfer rate • Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock • Power managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications • Works with Cypress CY2210-2, CY2210-3, CY2215, W133, W158, W159, W161, and W167B to support Intel® architecture platforms • Low-power CMOS design packaged in a 28-pin, 173-mil TSSOP package The Cypress W234 provides dual channel differential clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock but can also be used in systems that do not require synchronization of the Rambus clock. Key Specifications Supply Voltage:.................................... VDD = 3.3V ± 0.165V Operating Temperature:.................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: .......................................VDD + 0.5V Maximum Input Frequency: ..................................... 100 MHz Output Duty Cycle: .................................. 40/60% worst case Output Type: ............................Rambus signaling level (RSL) Block Diagram PCLKM0 SYNCLKN0 REFCLK MULT0:2 S0:2 Pin Configuration Phase Alignment Output Logic 1 28 S0 REFCLK VDD 2 27 S1 3 26 S2 SYNCLKN0 4 25 GND PCLKM0 5 24 CLK0# GND 6 23 CLK0 VDD 7 22 VDD GND 8 21 VDD SYNCLKN1 9 20 CLK1 PCLKM1 10 19 CLK1# VDD 11 18 GND 12 13 17 MULT0 16 MULT1 14 15 MULT2 CLK0 VDDIR CLK0# PLL Test Logic VDDIPD STOP# PWR_DWN# PCLKM1 SYNCLKN1 Phase Alignment Output Logic CLK1 CLK1# PWR_DWN# STOP# Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 7, 2001, Rev. ** W234 Pin Definitions Pin No. 2 Pin Type I PCLKM0:1 5, 10 I SYNCLKN0:1 4, 9 I STOP# 13 I PWR_DWN# 14 I 17, 16, 15 I Pin Name REFCLK MULT 0:2 Pin Description Reference Clock Input: Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). Phase Detector Input 0:1: The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If the Gear Ratio Logic is not used, this pin would be connected to ground. Phase Detector Input 0:1: The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If the Gear Ratio Logic is not used, this pin would be connected to ground. Clock Output Enable: When this input is driven to active LOW, it disables the differential Rambus Channel clocks. Active LOW Power-Down: When this input is driven to active LOW, it disables the differential Rambus Channel clocks and places the W234 in Power-Down mode. PLL Multiplier Select: These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK. MULT0 0 0 0 0 1 1 1 1 CLK0, CLK0#, CLK1, CLK1# S0, S1, S2 23, 24, 20, 19 28, 27, 26 VDD GND B 1 2 1 TBD 3 3 1 TBD A 4 9 6 TBD 8 16 8 TBD O Complementary Output Clock: Differential Rambus Channel clock outputs. I Mode Control Input: These inputs control the operating mode of the W234. S0 0 1 1 0 1 1 0 VDDIR VDDIPD MULT2 0 1 0 1 0 1 0 1 MULT1 0 0 1 1 0 0 1 1 1 12 RefV RefV 3, 7, 11, 21, 22 6, 8, 18, 25 P G S1 0 0 1 0 0 1 1 S2 0 0 0 1 1 1 X MODE Normal Bypass Test Vendor Test A Vendor Test B Reserved Output Test (OE) Reference for Refclk: Voltage reference for input reference clock. Reference for Phase Detector: Voltage reference for phase detector inputs and STOP#. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. 2 W234 W234 Refclk Phase Align PLL Busclk D RAC Pclk/M RMC Synclk/N CY2210-2 CY2210-3 CY2215 W133 W158 W159 W161 W167B M N Pclk 4 DLL Synclk Gear Ratio Logic Figure 1. DDLL System Architecture DDLL System Architecture and Gear Ratio Logic face of the RAC. The DDLL together with the Gear Ratio Logic enables users to exchange data directly from the Pclk domain to the Synclk domain without incurring additional latency for synchronization. In general, Pclk and Synclk can be of different frequencies, so the Gear Ratio Logic must select the appropriate M and N dividers such that the frequencies of Pclk/M and Synclk/N are equal. In one interesting example, Pclk=133 MHz, Synclk=100 MHz, and M=4 while N=3, giving Pclk/M=Synclk/N=33 MHz. This example of the clock waveforms with the Gear Ratio Logic is shown in Figure 2. Figure 1 shows the Distributed Delay Lock Loop (DDLL) system architecture, including the main system clock source, the Direct Rambus clock generator (DRCG), and the core logic that contains the Rambus Access Cell (RAC), the Rambus Memory Controller (RMC), and the Gear Ratio Logic. (This diagram abstractly represents the differential clocks as a single Busclk wire.) The purpose of the DDLL is to frequency-lock and phase-align the core logic and Rambus clocks (PCLK and SYNCLK) at the RMC/RAC boundary in order to allow data transfers without incurring additional latency. In the DDLL architecture, a PLL is used to generate the desired Busclk frequency, while a distributed loop forms a DLL to align the phase of Pclk and Synclk at the RMC/RAC boundary. The output clocks from the Gear Ratio Logic, Pclk/M, and Synclk/N, are output from the core logic and routed to the DRCG Phase Detector (φD) inputs. The routing of Pclk/M and Synclk/N must be matched in the core logic as well as on the board. After comparing the phase of Pclk/M vs. Synclk/N, the DRCG Phase Detector (φD) drives a phase aligner that adjusts the phase of the DRCG output clock, Busclk. Since everything else in the distributed loop is fixed delay, adjusting Busclk adjusts the phase of Synclk and thus the phase of Synclk/N. In this manner the distributed loop adjusts the phase of Synclk/N to match that of Pclk/M, nulling the phase error at the input of the DRCG Phase Detector (φD). When the clocks are aligned, data can be exchanged directly from the Pclk domain to the Synclk domain. The main clock source drives the system clock (Pclk) to the core logic, and also drives the reference clock (Refclk) to the DRCG. For typical Intel architecture platforms, Refclk will be half the CPU front side bus frequency. A PLL inside the DRCG multiplies Refclk to generate the desired frequency for Busclk, and Busclk is driven through a terminated transmission line (Rambus Channel). At the mid-point of the channel, the RAC senses Busclk using its own DLL for clock alignment, followed by a fixed divide-by-4 that generates Synclk. Pclk is the clock used in the memory controller (RMC) in the core logic, and Synclk is the clock used at the core logic inter- Pclk Synclk Pclk/M = Synclk/N Figure 2. Gear Ratio Timing Diagram 3 W234 CY2210-2 CY2210-3 CY2215 W133 Refclk W158 W159 W161 W167B W234 Phase Align PLL Busclk D RAC Synclk/N Pclk/M RMC S0/S1/S2 STOP# M N 4 Pclk DLL Synclk Gear Ratio Logic Figure 3. DDLL Including Details of DRCG Phase Detector Signals Table 1. PLL Divider Selection The DRCG Phase Detector (φD) receives two inputs from the core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M and N dividers in the core logic are chosen so that the frequencies of PCLKM and SYNCLKN are identical. The Phase Detector (φD) detects the phase difference between the two input clocks, and drives the DRCG Phase Aligner to null the input phase error through the distributed loop. When the loop is locked, the input phase error between PCLKM and SYNCLKN is within the specification tERR,PD given in Table 13 after the lock time given in the State Transition Section. The Phase Detector (φD) aligns the rising edge of PCLKM to the rising edge of SYNCLKN. The duty cycle of the phase detector input clocks will be within the specification DCIN,PD given in Table 12. Because the duty cycles of the two phase detector input clocks will not necessarily be identical, the falling edges of PCLKM and SYNCLKN may not be aligned when the rising edges are aligned. MULT0 MULT1 MULT2 A B 0 0 0 4 1 0 0 1 9 2 0 1 0 6 1 0 1 1 1 0 0 8 3 1 0 1 16 3 1 1 0 8 1 1 1 1 TBD TBD Table 2 shows the logic for enabling the clock outputs, using the STOP# input signal. When STOP# is HIGH, the DRCG is in its normal mode, and CLK and CLK# are complementary outputs following the Phase Aligner output (PAclk). When STOP# is LOW, the DRCG is in the Clk Stop mode, the output clock drivers are disabled (set to Hi-Z), and the CLK and CLK# settle to the DC voltage VX,STOP as given in Table 13. The level of VX,STOP is set by an external resistor network. The voltage levels of the PCLKM and SYNCLKN signals are determined by the controller. The pin VDDIPD is used as the voltage reference for the phase detector inputs and should be connected to the output voltage supply of the controller. In some applications, the DRCG PLL output clock will be used directly, by bypassing the Phase Aligner. If PCLKM and SYNCLKN are not used, those inputs must be grounded. Table 2. Clk Stop Mode Selection Selection Logic Table 1 shows the logic for selecting the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL from the input Refclk. Divider A sets the feedback and divider B sets the prescaler, so the PLL output clock frequency is set by: PLLClk=Refclk*A/B. Mode STOP# CLK CLK# Normal 1 PACLK PACLK# Clk Stop 0 VX,STOP VX,STOP Table 3 shows the logic for selecting the Bypass and Test modes. The select bits, S0, S1, and S2 control the selection of these modes. The Bypass mode brings out the full-speed PLL output clock, bypassing the Phase Aligner. The Test mode brings the REFCLK input all the way to the output, bypassing both the PLL and the Phase Aligner. In the Output Test mode (OE), both the CLK and CLK# outputs are put into a highimpedance state (Hi-Z). This can be used for component testing and for board-level testing. 4 W234 and the corresponding M and N dividers in the gear ratio logic. The column Ratio gives the Gear Ratio as defined Pclk/Synclk (same as M and N). The column [email protected] gives the divided down frequency (in MHz) at the Phase Detector (φD), where [email protected]=PCLK/M=SYNCLK/N. Table 3. Bypass and Test Mode Selection Mode By Pclk (int.) S0 S1 S2 CLK CLK# Normal 0 0 0 Gnd PAClk PAClk# Bypass 1 0 0 PLLClk PLLClk PLLClk# State Transitions The clock source has three fundamental operating states. Figure 4 shows the state diagram with each transition labelled A through H. Note that the clock source output may NOT be glitch-free during state transitions. Test 1 1 0 RefClk RefClk RefClk# Vendor Test A 0 0 1 - - - Vendor Test B 1 0 1 - - - Reserved 1 1 1 - - - Output Test (OE) 0 1 X - Hi-Z RefClk# Upon powering up the device, the device can enter any state, depending on the settings of the control signals, PWR_DWN# and STOP#. In Power-Down mode, the clock source is powered down with the control signal, PWR_DWN#, equal to 0. The control signals S0, S1 and S2 must be stable before power is applied to the device, and can only be changed in Power-Down mode (PWR_DWN#=0). The reference inputs, VDDIR and VDDIPD, may remain on or may be grounded during the Power-Down mode. Table 4 shows the logic for selecting the Power-Down mode, using the PWR_DWN# input signal. PWR_DWN# is active LOW (enabled when 0). When PWR_DWN# is disabled, the DRCG is in its normal mode. When PWR_DWN# is enabled, the DRCG is put into a powered-off state, and the CLK and CLK# outputs are three-stated. Table 4. PWR_DWN# Mode Selection Mode PWR_DWN# CLK CLK# Normal 1 PAClk PAClk# Power-Down 0 GND GND The control signals MULT0, MULT1, and MULT2 can be used in two ways. If they are changed during Power-Down mode, then the Power-Down transition timings determine the settling time of the DRCG. However, the MULT0, MULT1, and MULT2 control signals can also be changed during Normal mode. When the MULT control signals are “hot swapped” in this manner, the MULT transition timings determine the settling time of the DRCG. Table of Frequencies and Gear Ratios Table 5 shows several supported Pclk and Busclk frequencies, the corresponding A and B dividers required in the DRCG PLL, Table 5. Frequencies, Dividers, and Gear Ratios Pclk Refclk Busclk Synclk A B M N Ratio [email protected] 67 33 267 67 8 1 2 2 1.0 33 100 50 300 75 6 1 8 6 1.33 12.5 100 50 400 100 8 1 4 4 1.0 25 133 67 267 67 4 1 4 2 2.0 33 133 67 400 100 6 1 8 6 1.33 16.7 VDD Turn-On M VDD Turn-On G J L Test Normal N F B K A E VDD Turn-On VDD Turn-On D Power-Down Clk Stop C Figure 4. Clock Source State Diagram 5 H W234 In Clk Stop mode, the clock source is on, but the output is disabled (STOP# asserted). The VDDIPD reference input may remain on or may be grounded during the Clk Stop mode. The VDDIR reference input must remain on during the Clk Stop mode. Figure 5 shows the timing diagrams for the various transitions between states, and Table 7 specifies the latencies of each state transition. Note that these transition latencies assume the following: • REFCLK input has settled and meets specification shown in Table 12. • MULT0, MULT1, MULT2, S0, S1, and S2 control signals are stable. In Normal mode, the clock source is on, and the output is enabled. Table 6 lists the control signals for each state. Table 6. Control Signals for Clock Source States State PWR_DWN# STOP# Clock Source Output Buffer Power-Down 0 X OFF Ground Clk Stop 1 0 ON Disabled Normal 1 1 ON Enabled Timing Diagrams Power-Down Exit and Entry PWR_DWN# tPOWERDN tPOWERUP CLK0/CLK0# CLK1/CLK1# Output Enable Control tON tSTOP tCLKON STOP# tCLKOFF tCLKSETL CLK0/CLK0# CLK1/CLK1# output clock clock enabled not specified and glitch free glitches may occur. clock output settled within 50 ps of the phase before disabled Figure 5. State Transition Timing Diagrams MULT0 and/or MULT1 and/or MULT2 tMULT CLK0/CLK0# CLK1/CLK1# Figure 6. Multiply Transition Timing 6 W234 Table 7. State Transition Latency Specifications Transition Latency Transition From To Symbol Max. A Power-Down Normal tPOWERUP 3 ms Time from PWR_DWN# to rising edge CLK/CLK# output settled (excluding tDISTLOCK) C Power-Down Clk Stop tPOWERUP 3 ms Time from PWR_DWN# rising edge until the internal PLL and clock has turned ON and settled. K Power-Down Test tPOWERUP 3 ms Time from PWR_DWN# rising edge to CLK/CLK# output settled (excluding tDISTLOCK). G VDD ON Normal tPOWERUP 3 ms Time from VDD is applied and settled until CLK/CLK# output settled (excluding tDISTLOCK). H VDD ON Clk Stop tPOWERUP 3 ms Time from VDD is applied and settled until internal PLL and clock has turned ON and settled. M VDD ON Test tPOWERUP 3 ms Time from VDD is applied and settled until internal PLL and clock has turned ON and settled. J Normal Normal tMULT 1 ms Time from when MULT0, MULT1, or MULT2 changed until CLK/CLK# output resettled (excluding tDISTLOCK). E Clk Stop Normal tCLKON 10 ns Time from STOP# rising edge until CLK/CLK# provides glitch-free clock edges. E Clk Stop Normal tCLKSETL 20 cycles Time from STOP# rising edge to CLK/CLK# output settled to within 50 ps of the phase before CLK/CLK# was disabled. F Normal Clk Stop tCLKOFF 5 ns Time from STOP# falling edge to CLK/CLK# output disabled. L Test Normal tCTL 3 ms Time from when S0, S1, or S2 is changed until CLK/CLK# output has resettled (excluding tDISTLOCK). N Normal Test tCTL 3 ms Time from when S0, S1, or S2 is changed until CLK/CLK# output has resettled (excluding tDISTLOCK). B,D Normal or Clk Stop PWR_DWN# tPOWERDN 1 ms Time from PWR_DWN# falling edge to the device in PWR_DWN#. Figure 5 shows that the CLK Stop to Normal transition goes through three phases. During tCLKON, the clock output is not specified and can have glitches. For tCLKON<t<tCLKSETL, the clock output is enabled and must be glitch-free. For t>tCLKSETL, the clock output phase must be settled to within Description 50 ps of the phase before the clock output was disabled. At this time, the clock output must also meet the voltage and timing specifications of Table 13. The outputs are in a high-impedance state during the Clk Stop mode. Table 8. Distributed Loop Lock Time Specification Symbol tDISTLOCK Min. Max. Unit Description 5 ms Time from when CLK/CLK# output is settled to when the phase error between SYNCLKN and PCLKM falls within the tERR,PD spec in Table 13. 7 W234 Table 9. Supply and Reference Current Specification Parameter Description Min. Max. Unit IPOWERDOWN “Supply” current in Power-Down state (PWR_DWN#=0) -- 1.2 mA ICLKSTOP “Supply” current in Clk Stop state (STOP#=0) -- 175 mA INORMAL “Supply” current in Normal state (STOP#=1,PWR_DWN#=1) -- 225 mA IREF,PWDN Current at VDDIR or VDDIPD reference pin in PWR_DWN# state (PWR_DWN#=0) -- 50 µA IREF,NORM Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PWR_DWN#=1) -- 4 mA Min. Max. Unit Table 10 represents stress ratings only, and functional operation at the maximums is not guaranteed. Table 10. Absolute Maximum Ratings Parameter Description VDD, ABS Max. voltage on VDD with respect to ground –0.5 4.0 V VI, ABS Max. voltage on any pin with respect to ground –0.5 VDD+0.5 V Table 11 gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH=28Ω. Table 11. External Component Values Parameter Description Min. Max. Unit RS Serial Resistor 39 ±5% Ω RP Parallel Resistor 51 ±5% Ω CF Edge Rate Filter Capacitor CMID AC Ground Capacitor Note: 1. Do not populate CF. Leave pads for future use. 8 4–15 ±10% pF 0.1 ±20% µF W234 Table 12. Operating Conditions Parameter Description Min. Max. Unit VDD Supply Voltage 3.135 3.465 V TA Ambient Operating Temperature 0 70 °C tCYCLE,IN Refclk Input Cycle Time 10 40 ns – 250 ps  tJ,IN Input Cycle-to-Cycle Jitter DCIN Input Duty Cycle over 10,000 Cycles 40 60 %tCYCLE FMIN Input Frequency of Modulation 30 33 kHz PMIN Modulation Index for Triangular Modulation – 0.6 % Modulation Index for Non-Triangular Modulation tCYCLE,PD Phase Detector Input Cycle Time at PCLKM & SYNCLKN tERR,INIT Initial Phase error at Phase Detector Inputs DCIN,PD – 0.5  % 30 100 ns –0.5 0.5 tCYCLE,PD Phase Detector Input Duty Cycle over 10,000 Cycles 25 75 tCYCLE,PD tI,SR Input Slew Rate (measured at 20%-80% of input voltage) for PCLKM, SYNCLKN, and REFCLK 1 4 V/ns CIN,PD Input Capacitance at PCLKM, SYNCLKN, and REFCLK – 7 pF – 0.5 pF ∆CIN,PD Input Capacitance matching at PCLKM and CIN,CMOS Input Capacitance at CMOS pins (excluding PCLKM, SYNCLKN, and REFCLK) – 10 pF VIL Input (CMOS) Signal Low Voltage – 0.3 VDD VIH Input (CMOS) Signal High Voltage 0.7 - VDD VIL,R Refclk Input Low Voltage - 0.3 VDDIR VIH,R Refclk Input High Voltage 0.7 – VDDIR VIL,PD Input Signal Low Voltage for PD Inputs and STOP# – 0.3 VDDIPD VIH,PD Input Signal High Voltage for PD Inputs and STOP# 0.7 – VDDIPD VDDIR Input Supply Reference for REFCLK 1.235 3.465 V SYNCLKN Input Supply Reference for PD Inputs 1.235 2.625 V VDDIPD Notes: 2. Refclk jitter measured at VDDIR (nom)/2. 3. If input modulation is used: input modulation is allowed but not required. 4. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. 5. Capacitance measured at Freq=1 MHz, DC bias=0.9V and VAC<100 mV. 9 W234 Table 13. Device Characteristics Parameter Description Min. Max. Unit tCYCLE Clock Cycle Time 2.5 3.75 ns tJ Cycle-to-Cycle Jitter at CLK/CLK# - 60 ps Total Jitter over 2, 3, or 4 Clock Cycles - 75 ps - 60 ps 266-MHz Cycle-to-Cycle Jitter   - 75 ps VX,STOP Output Voltage during Clk Stop (STOP#=0) 1.1 2.0 V VX Differential Output Crossing-Point Voltage 1.3 1.8 V 1.1 1.5 V 266-MHz Total Jitter over 2, 3, or 4 Clock Cycles single-ended) VCOS Output Voltage Swing (p-p VOH Output High Voltage - 2.5 V VOL Output Low voltage 0.6 - V IOZ,STOP Output Current during Clk Stop (STOP# = 0) - 500 µA DC Output Duty Cycle over 10,000 Cycles 40 60 %tCYCLE tDC,ERR Output Cycle-to-Cycle Duty Cycle Error - 50 ps tR,tF Output Rise and Fall Times (measured at 20%–80% of output voltage) 300 550 ps tCR,CF Difference between Output Rise and Fall Times on the Same Pin of a Single Device (20%–80%) - 100 ps Notes: 6. Output Jitter spec measured at tCYCLE = 2.5 ns. 7. Output Jitter Spec measured at tCYCLE = 3.75 ns. 8. VCOS = VOH–VOL. Ordering Information Ordering Code W234 Package Name X Package Type 28-pin TSSOP (173 mils) Document #: 38-00921-*A 10 W234 Layout Example +3.3V Supply FB C4 0.005 µF 10 µF G C3 G VDDIR G G G G G 28 27 26 G25 24 23 22 21 20 19 G 18 17 16 15 1 2 3 4 5 6G 7 8G 9 10 G G VDDIPD 11 12 13 14 Internal Power Supply Plane FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) G = VIA to GND plane layer All Bypass cap = 0.1 Ceramic XR7 11 G G G G W234 Package Diagram 28-Pin Thin Small Shrink Outline Package (TSSOP, 173 mils) © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.