Power Supply ICs for TFT-LCD Panels Multi-channel System Power Supply IC for Small to Middle PANEL BD8184MUV No.11035EAT18 Description The BD8184MUV is a system power supply for the TFT-LCD panels used for liquid crystal Monitors and Note Display. Incorporates high-power FET with low on resistance for large currents that employ high-power packages, thus driving large current loads while suppressing the generation of heat. A charge pump controller is incorporated as well, thus greatly reducing the number of application components. Also Gate Shading Function is included. Features 1) Boost DC/DC converter; 18 V / 2.5 A switch current. (Target specification is ±1% accurate.) 2) Switching frequency: 1.2 MHz 3) Operational Amplifier (short current 200mA) 4) Incorporates Positive / Negative Charge-pump Controllers. 5) Gate Shading Function 6) VQFN024V4040 Package (4.0 mm x 4.0 mm) 7) Protection circuits: Under Voltage Lockout Protection Circuit Thermal Shutdown Circuit (Latch Mode) Over Current Protection Circuit (AVDD) Timer Latch Mode Short Circuit Protection (AVDD SRC VGL) Over / Under Voltage Protection Circuit for Boost DC/DC Output No SCP time included (160ms from UVLO-off) Applications Power supply for the TFT-LCD panels used for LCD Monitors and Note Display www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/17 2011.11 - Rev.A Technical Note BD8184MUV ●Absolute Maximum Ratings (TA = 25℃) Parameter Symbol LIMIT Unit Supply Voltage 1 VIN +7 V Supply Voltage 2 AVDD +20 V Supply Voltage 3 SRC +36 V Switching Voltage SW, DRP, DRN +20 V Input Voltage 1 RSTIN, DLY, CTL, FB, FBP, FBN VIN+0.3 V Input Voltage 2 INN, INP +20 V Output Voltage 1 RST, COMP, VREF +7 V Output Voltage 2 VCOM +20 V Output Voltage 3_1 GSOUT +36 V Output Voltage 3_2 SRC - GSOUT +40 V Tjmax 150 ℃ Junction Temperature Power Dissipation *1 Pd 3560 mW Operating Temperature Range Topr -40～85 ℃ Storage Temperature Range Tstg -55～150 ℃ *1 Derating in done 28.5mW/℃ for operating above Ta≧25℃(On 4-layer 74.2mm×74.2mm×1.6mm board) ●Operating Range (Ta=-40℃～85℃) Symbol MIN MAX Unit Supply Voltage 1 VIN 2.0 5.5 V Supply Voltage 2 AVDD 6 18 V Supply Voltage 3 SRC 12 34 V Parameter www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 2/17 2011.11 - Rev.A Technical Note BD8184MUV ●Electrical characteristics (unless otherwise specified VIN = 3.3V, AVDD = 10V and TA=25℃) Limits Parameter Symbol Unit Min Typ Max Condition GENERAL Circuit Current IVIN - 1.2 3 mA No Switching Under Voltage Lockout Threshold VUVLO 1.75 1.85 1.95 V VIN rising Internal Reference Output Voltage VREF 1.238 1.250 1.262 V No laod Thermal Shutdown (rising) TSD - 160 - ℃ Junction Temp Duration to Trigger Fault Condition TSCP - 55 - ms FB , FBP or FBN below threshold VFB 1.238 1.250 1.262 V Voltage follower VTL_FB 0.95 1.0 1.05 V VFB falling FB Input Bias Current IFB - 0.1 1 µA VFB= 1.5V SW Leakage Current ISW_L - 0 10 µA VSW=20V Maximum switching Duty Cycle MDUTY 85 90 95 % VFB= 1.0V RSW - 200 - mΩ SW Current Limit ISWLIM 2.5 - - A Over Voltage Protection VOVP - 20 - V AVDD rising Under Voltage Protection VUVP 1.3 1.6 1.9 V AVDD falling TSS_FB - 13.6 - ms FSW 1.0 1.2 1.4 MHz RST Output Low Voltage VRST - 0.05 0.2 V IRST =1.2mA RSTIN Threshold Voltage VTH_L 1.18 1.25 1.32 V RSTIN falling RSTIN Input Current IRSTIN - 0 - µA VRSTIN=0 to VIN-0.3 RST Blanking Time TNO_SCP 146 163 180 ms No SCP Zone VRANGE 0 - AVDD V Offset Voltage VOS - 2 15 mV VINP= 5.0V Input Current IINP - 0 - µA VINP= 5.0V VOH - 5.03 5.06 V ICOM = +50mA VOL 4.94 4.97 - V ICOM = -50mA ISHT_VCOM - 200 - mA SR - 40 - V/us BOOST CONVERTER (AVDD) FB Regulation Voltage FB Fault Trip Level SW ON-Resistance BOOST Soft Start Time Oscillator frequency ISW= 200mA RESET Operational Amp rifer Input Range Output Swing Voltage (VINP= 5.0V) Short Circuit Current Slew Rate www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 3/17 2011.11 - Rev.A Technical Note BD8184MUV ●Electrical characteristics (unless otherwise specified VIN = 3.3V, AVDD = 10V and TA=25℃) (Continued) Limits Parameter Symbol Unit Condition Min Typ Max Negative Charge pump driver (VGL) FBN Regulation Voltage VFBN 235 250 265 mV VTL_FBN 400 450 500 mV VFBN rising FBN Input Bias Current IFBN - 0.1 1 µA VFBN= 0.1V Oscillator frequency FCPN 500 600 700 kHz DRN Leakage Current IDRN_L - 0 10 µA VFBP 1.23 1.25 1.27 V VTL_FBP 0.95 1.0 1.05 V VFBP falling FBP Input Bias Current IFBP - 0.1 1 µA VFBP= 1.5V Oscillator frequency FCPP 500 600 700 kHz DRP Leakage Current IDRP_L - 0 10 µA Soft-Start Time TSSP - 3.4 - ms IDLY 4 5 6 µA DLY Threshold Voltage VTL_DLY 1.22 1.25 1.28 V CTL Input Voltage High VIN_H 2.0 - - V CTL Input Voltage Low VIN_L - - 0.5 V CTL Input Bias Current ICTL - 0 - µA VRSTIN=0 to VIN-0.3 Propagation delay time (Rising) TGS_R - 100 - ns VSRC= 25V Propagation delay time (Falling) TGS_F - 100 - ns VSRC= 25V SRC -GSOUT ON Resistance RGS_H - 15 - Ω VDLY = 1.5V GSOUT-RE ON Resistance RGS_M - 30 - Ω VDLY = 1.5V GSOUT-GND ON Resistance RGS_L - 2.5 - kΩ VDLY = 1.0V FBN Fault Trip Level VFBN=1.0V Positive Charge pump driver (SRC) FBP Regulation Voltage FBP Fault Trip Level VFBP= 1.5V Gate Shading Function (GSOUT) DLY Source Current VDLY falling ○This product is not designed for protection against radio active rays. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 4/17 2011.11 - Rev.A Technical Note BD8184MUV ●Electrical characteristic curves (Reference data) (Unless otherwise specified VIN = 3.3V, AVDD = 10V and TA=25℃) 50 2.0 1.40 45 40 25℃ 1.30 85℃ 35 85℃ 30 IVIN [mA] IVIN [mA] 1.2 25℃ 25 -40℃ 0.8 Fsw [MHz] 1.6 -40℃ 20 15 0.4 1.10 10 5 0.0 1.00 0 0 1 2 3 4 5 -40 0 1 2 3 4 -15 10 5 Fig.1 Curcuit Current Fig.2 Curcuit Current (No switching) (Switching) 35 60 85 Ta [℃] VIN [V] VIN [V] Fig.3 Dependent on Temparactue Freqency 1.30 1.40 1.30 1.29 1.28 1.30 85℃ 1.27 25℃ 1.25 1.26 1.20 VREF [V] VREF [V] Fsw [MHz] 1.20 1.25 1.24 1.10 -40℃ 1.23 25℃ -40℃ 1.20 1.22 85℃ 1.21 1.00 2 2.5 3 3.5 4 4.5 5 5.5 1.15 1.20 2 VIN [V] 2.5 3 3.5 4 4.5 5 0 5.5 5 10 VIN [V] Fig.4 Dependent on Input 15 20 25 30 IVREF[mA] Fig.5 VREF Line Regulation Fig.6 VREF Load Regulation Voltage Freqency 100 85℃ 80 10 10 6 6 ICOMP [uA] 60 2 -40℃ ICOMP [uA] Duty [%] 25℃ 40 20 -2 2 -2 -6 0 -6 -10 0 1 2 VCOMP [V] 3 Fig.7 COMP V.S.CDUTY 0 1 2 VCOMP [V] 3 -10 0 Fig.8 COMP Sink Current 1 2 VCOMP [V] 3 Fig.9 COMP Source Current 100 IAVDD 90 Efficiency [%] IAVDD AVDD AVDD 80 VIN=3.3V AVDD=9.8V Fsw=1.177MHz VGH,VGL→NoLoad 70 60 0 100 200 300 400 500 IAVDD [mA] Fig.10 Load Transient Response Falling www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. Fig.11 Load Transient Response Rising 5/17 Fig.12 Boost Converter Efficiency 2011.11 - Rev.A Technical Note BD8184MUV ●Electrical characteristic curves (Reference data) – Continued (Unless otherwise specified VIN = 3.3V, AVDD = 10V and TA=25℃) 10 VINP VINP DLY Time [s] 1 INN=VCOM INN=VCOM 0.1 0.01 0.001 0.001 0.01 0.1 1 10 C_DLY [uF] Fig.13 VCOM Slew Rate （Rising） CTL Fig.14 VCOM Slew Rate Fig.15 C_DLY vs. delay time （falling） SRC CTL AVDD VIN VGL GSOUT(RE pull down to AVDD) Fig. 16 Gate Sharding Wave form1 GSOUT(RE pull down to GND) Fig.17 Gate Sharding Wave form2 Fig.18 Power On Sequence1 (Main Output) SRC SRC AVDD AVDD VIN DLY CTL GSOUT Fig.19 Power On Sequence2 (CTL=signal, RE pull down to AVDD) VIN VIN GSOUT GSOUT RST RST Fig.20 Power Off Sequence1 (R_RST_U=10k,R_RST_D=10k) Fig.21 Power Off Sequence2 (R_RST_U=10k,R_RST_D=OPEN) SRC AVDD VIN VGL Fig.22 Power On Sequence3 (Main Output) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 6/17 2011.11 - Rev.A Technical Note BD8184MUV ●Block Diagram ●Pin Configuration Digital Control Block 1.25V COMP Current Sense and Limit AVDD 1.25V 21 16 COMP 15 RSTIN 14 AGND2 13 VIN RE SW PGND 20 19 4 7 AGND1 AVDD Positive Charge pump AVDD 5 DRP 6 DRP 6 AGND1 AVDD VCOM High Voltage Switch Control RE SRC GSOUT RST 22 12 11 DLY 4 VREF AGND1 FBN INP 3 10 INN CTL FB DRN FBP 8 BD8184MUV 9 24 17 3 7 1 PGND 2 DRN 2 AGND1 AVDD Negative Charge Pump FBP VCOM 5 0.25V 10 INN 19 Sequence Control FBN 18 PGND Oscillator 11 1 18 RST 16 INP PGND Comparator 2 3 21 20 CTL 17 24 SW Error Amplifier FB GSOUT Fall/Thermal Control 23 Fall DLY (1.25V) 8 12 0.25V Reference Voltage SRC VIN VREF 22 13 23 Fig.24 Pin Configuration 9 1.25V 15 160ms RSTIN 14 AGND2 Fig.23 Block Diagram ●Package Dimension VQFN024V4040 4.0±0.1 4.0±0.1 Marking D8184 LOT 1.0MAX 1PIN MARK 0.08 S 2.4±0.1 1 6 0.4±0.1 24 7 12 19 18 0.75 0.5 2.4±0.1 C0.2 (0.22) +0.03 0.02 -0.02 S 13 +0.05 0.25 -0.04 (Unit : mm) Fig.25 Package Dimension (UNIT : mm) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 7/17 2011.11 - Rev.A Technical Note BD8184MUV ●Pin Assignments PINNO. Pin name Function 1 INP COM Amplifier input + 2 INN COM Amplifier input - 3 VCOM COM Amplifier output 4 AGND1 Ground 5 AVDD Supply voltage input for com, charge pump 6 DRP Drive pin of the positive charge pump 7 DRN Drive pin of the negative charge pump 8 CTL High voltage switch control pin 9 RST Open drain reset output 10 FBP Positive charge pump feed back 11 FBN Negative charge pump feed back 12 VREF Internal Reference voltage output 13 VIN Supply voltage input for PWM 14 AGND2 Ground 15 RSTIN Reset comparator input 16 COMP BOOST amplifier output 17 FB BOOST amplifier input 18 PGND1 BOOST FET ground 19 PGND2 BOOST FET ground 20 SW BOOST FET Drain 21 RE Gate High voltage Fall set pin 22 GSOUT Gate High voltage output set pin 23 SRC Gate High voltage input set pin 24 DLY GSOUT Delay Adjust pin www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 8/17 2011.11 - Rev.A Technical Note BD8184MUV ●Main Block Function ・Boost Converter A controller circuit for DC/DC boosting. The switching duty is controlled so that the feedback voltage FB is set to 1.25 V (typ.). A soft start operates at the time of starting. ・Positive Charge Pump A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage FBP will be set to 1.25 V (typ.). ・Negative Charge Pump A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage FBN will be set to 0.25 V (Typ.). ・Gate Shading Controller A controller circuit for P-MOS FET Switch The GSOUT switching synchronize with CTL input. When VIN drops below UVLO threshold or RST=Low(=RSTIN<1.25V), GSOUT is pulled High(=SRC). ・VCOM A 1-channel operational amplifier block. ・Reset A open-drain output(RST) refer from RSTIN voltage(up to threshold voltage 1.25V) RST is keep High(need a pull-up resistor connected to VIN) dulling to 163ms from start-up. ・VREF A block that generates internal reference voltage of 1.25V (Typ.). VREF is keep High when the thermal/short-current-protection shutdown circuit. ・TSD/UVLO/OVP/UVP The thermal shutdown circuit is shut down at an IC internal temperature of 160℃. The under-voltage lockout protection circuit shuts down the IC when the VIN is 1.85 V (Typ.) or below. The over-voltage protection circuit when the SW is 19 V (Typ.) or over. The under-voltage protection circuit when the SW is 1.3 V (Typ.) or under ・Start-up Controller A control circuit for the starting sequence. Controls to start in order of VCC VGL VDDSRC (Please refer to Fig.4 of next page for details.) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 9/17 2011.11 - Rev.A Technical Note BD8184MUV ●Power Sequence Fig.26 Power Sequence www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 10/17 2011.11 - Rev.A Technical Note BD8184MUV ●How to select parts of application (1-1) Setting the Output L Constant (Boost Converter) The coil to use for output is decided by the rating current ILR and input current maximum value IINMAX of the coil. VIN IINMAX + ∆IL should not reach the rating value level IL L IL ILR VDD IINMAX average current Fig.27 Coil Current Waveform Co Fig. 28 Output Application Circuit Diagram Adjust so that IINMAX +∆IL does not reach the rating current value ILR. At this time, ∆IL can be obtained by the following equation. 1 VDD-VIN 1 [A] Here, f is the switching frequency. VIN ∆IL = L VIN f Set with sufficient margin because the coil value may have the dispersion of 30%. If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element. BD8164MUV uses the current mode DC/DC converter control and has the optimized design at the coil value. A coil inductance (L) of 4.7 uH to 15 uH is recommended from viewpoints of electric power efficiency, response, and stability. (2) Output Capacity Settings For the capacitor to use for the output, select the capacitor which has the larger value in the ripple voltage VPP allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is decided by the following equation. Here, f is the switching frequency. ∆VPP = ILMAX RESR + 1 fCo VIN (ILMAX - AVDD ∆IL 2 ) [V] Perform setting so that the voltage is within the allowable ripple voltage range. For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation. VDR = ∆I Co 10 us [V] However, 10 s is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the Input Capacitor Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than 10 F and less than 100 m. If a capacitor out of this range is selected, the excessive ripple voltage is superposed on the input voltage, accordingly it may cause the malfunction of IC. However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching frequency. Be sure to perform the margin check using the actual product. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/17 2011.11 - Rev.A Technical Note BD8184MUV (4) Setting RC, CC of the Phase Compensation Circuit In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power amplifier, it is easy to compensate by adding the zero point with CC and RC to the output from the error amp as shown in the illustration. Open loop gain characteristics 1 Fp = fp(Min) A fp(Max) fz(ESR) = 0 Gain [Hz] 2 RO CO 1 [Hz] 2 ESR CO [dB] lOUTMin fz(ESR) lOUTMax Pole at the power amplification stage When the output current reduces, the load resistance Ro increases and the pole frequency lowers. 0 Phase [deg] -90 fp(Min) = Error amp phase compensation characteristics fz(Max) = A 1 [Hz] at light load 2 ROMax CO 1 [Hz] at heavy load 2 ROMin CO Gain [dB] Zero at the power amplification stage When the output capacitor is set larger, the pole frequency lowers but the zero frequency will not change. (This is because the capacitor ESR becomes 1/2 when the capacitor becomes 2 times.) 0 Phase [deg] 0 -90 fp(Amp.) = Fig. 29 Gain vs Phase L VIN VIN Rc [Hz] AVDD Ro ESR Cin SW COMP 1 2 Rc Cc Co GND,PGND Cc Fig. 30 Application Circuit Diagram It is possible to realize the stable feedback loop by canceling the pole fp(Min.), which is created by the output capacitor and load resistor, with CR zero compensation of the error amp as shown below. fz(Amp.) = fp(Min.) 1 2 Rc Cc www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. = 1 2 Romax Co 12/17 [Hz] 2011.11 - Rev.A Technical Note BD8184MUV (5) Design of the Feedback Resistor Constant Refer to the following equation to set the feedback resistor. As the setting range, 6.8 k to 330 k is recommended. If the resistor is set lower than a 6.8 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.1 µA(Typ.) in the internal error amplifier. Reference voltage 1.25 V Vo AVDD = R1 + R2 R2 R1 FB ＋ [V] ERR 17 FB R2 － Fig. 31 Application Circuit Diagram (6) Positive-side Charge Pump Settings The IC incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 6.8 k to 330 k is recommended. If the resistor is set lower than a 6.8k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.1 µA (Typ.) in the internal error amp. SRC SRC = R3 + R4 R4 FBP [V] C3 Reference voltage 1.25 V R3 ＋ ERR 10 1000 pF to 4700 pF FBP R4 － Fig. 32 Application Circuit Diagram In order to prevent output voltage overshooting, add capacitor C3 in parallel with R3. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate. (7) Negative-side Charge Pump Settings This IC incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 6.8 k to 330 k is recommended. If the resistor is set lower than a 6.8 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.1 µA (Typ.) in the internal error amp. VGL 1000 pF to 4700 pF VGL = (FBN－VREF) R5 R6 + FBN C5 [V] 0.25V R5 R6 VREF (1.25V ±1%) － 11 FBN ERR ＋ 12 Fig. 33 Application Circuit Diagram In order to prevent output voltage overshooting, insert capacitor C5 in parallel with R5. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 13/17 2011.11 - Rev.A Technical Note BD8184MUV ●Application Circuit TDK SLF7055T-100M2R5(10μH,2.5A) VIN 10V/0.5Amax AVDD RSX301LA-30 10uF 10uF AVDD 10uF 10uF 10uF 1k INP 5.5V VCOM 21 20 19 PGND 1 22 SW DLY 22k 23 SRC 24 GSOUT RE SRC 33nF GSOUT 18k 91k PGND 2 FB 17 INN 10 3 VCOM COMP 4 1uF 13k 16 3.9k 15 AGND1 AVDD 18 RSTIN 10k 5 DA227 AVDD AGND2 10nF 10k 14 6 DRP 8 9 10 VREF FBN FBP RST CTL DRN 7 0.1uF VIN VIN 13 0.1uF 11 3.3V 1uF 12 0.1uF DA227 10k CTL 20V/20mA max SRC RST 1uF 15k 0.22μF 110k 1uF 150k 10k 0.1uF VGL DA227 1uF -7.1V/20mA max Fig. 34 Application Circuit www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/17 2011.11 - Rev.A Technical Note BD8184MUV ●I/O Equivalent Circuit Diagrams (Except for 4.AGND1, 5.AVDD, 13.VIN, 14.AGND2, 18･19.PGND, 23.SRC) 1.INP 2.INN 3.VCOM 6.DRP 7.DRN AVDD AVDD 9.RST AVDD AVDD 10.FBP 11.FBN 15.RSTIN VIN 8.CTL VIN 16.COMP VIN 17.FB 18.SW VIN VIN 21.RE VIN SRC 22.GSOUT 24.DLY SRC VIN RE www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 15/17 2011.11 - Rev.A Technical Note BD8184MUV ●Operation Notes 1. Absolute maximum range This product are produced with strict quality control, but might be destroyed in using beyond absolute maximum ratings. Open IC destroyed a failure mode cannot be defined (like Short mode, or Open mode). Therefore physical security countermeasure, like fuse, is to be given when a specified mode to be beyond absolute maximum ratings is considered. 2. About Rush Current Rush current might flow momentarily by the order of turning on the power supply and rise time in IC with two or more power supplies. Therefore, please note drawing the width of the power supply and the GND pattern wiring, the output capacity, and the pattern and the current abilities. 3. Setting of heat Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4. Short Circuit between Terminal and Soldering Don’t short-circuit between Output pin and VIN pin, Output pin and GND pin, or VIN pin and GND pin. When soldering the IC on circuit board, please be unusually cautious about the orientation and the position of the IC. When the orientation is mistaken the IC may be destroyed. 5. Electromagnetic Field Mal-function may happen when the device is used in the strong electromagnetic field. 6. Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 7. This IC is a monolithic IC which has P+ isolation in the P substrate and between the various pins. A P-N junction is formed from this P layer and the N layer of each pin. For example, when a resistor and a transistor is connected to a pin. Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly, you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND. (P substrate) voltage to an input pin. Please make sure all pins which is over GND even if include transient feature. （PinＢ） Ｂ （PinＢ） Ｃ ～ ～ resister （PinＡ） Ｅ Ｃ ～ ～ Ｂ ＧＮＤ Ｎ Ｐ＋ Ｐ＋ Ｐ Ｐ＋ near-by other element Ｐ＋ Ｎ Ｎ （PinＡ） Ｐsubstrate parasitic diode GND GND parasitic diode or transistor Ｎ Ｎ Ｅ ～ ～ SIMPLIFIED STRUCTURE OF BI-POLAR IC Parasitic diode GND parasitic diode or transistor GND 8. Over current protection circuit The over-current protection circuits are built in at output, according to their respective current outputs and prevent the IC from being damaged when the load is short-circuited or over-current. But, these protection circuits are effective for preventing destruction by unexpected accident. When it’s in continuous protection circuit moving period don’t use please. And for ability, because this chip has minus characteristic, be careful for heat plan. 9. Built-in thermal circuit A temperature control circuit is built in the IC to prevent the damage due to overheat. Therefore, all the outputs are turned off when the thermal circuit works and are turned on when the temperature goes down to the specified level. 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 16/17 2011.11 - Rev.A Technical Note BD8184MUV ●Ordering part number B D 8 Part No. 1 8 4 M Part No. U V Package MUV:VQFN024V4040 - E 2 Packaging and forming specification E2: Embossed tape and reel VQFN024V4040 <Tape and Reel information> 4.0±0.1 4.0±0.1 1.0MAX 2.4±0.1 0.4±0.1 7 12 19 18 0.5 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 6 24 0.75 E2 2.4±0.1 1 2500pcs (0.22) +0.03 0.02 -0.02 S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape 13 +0.05 0.25 -0.04 1pin (Unit : mm) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. Reel 17/17 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2011.11 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. R1120A