A3942 Quad High-Side Gate Driver for Automotive Applications Features and Benefits Description ▪ Drives four N-channel high-side MOSFETS ▪ Charge pump for 100% duty cycle operation ▪ Serial and discrete inputs ▪ SPI port for control and fault diagnostics ▪ 4.5 to 60 V input voltage range ▪ Sleep function for minimum power drain ▪ Thin profile 38-lead TSSOP with internally fused leads for enhanced thermal dissipation ▪ Lead (Pb) free ▪ Device protection features: ▫ Short-to-ground detection (latched) ▫ Short-to-battery protection (latched) ▫ Open load detection (latched) ▫ VDD undervoltage lockout ▫ VCP undervoltage lockout ▫ Thermal monitor The A3942 is a highly-integrated gate driver IC that can drive up to four N-Channel MOSFETs in a high-side configuration. The device is designed to withstand the harsh environmental conditions and high reliability standards of automotive applications. Serial Peripheral Interface (SPI) compatibility makes the device easily integrated into existing applications. The MOSFETs in such applications are typically used to drive gasoline or diesel engine management actuators, transmission actuators, body control actuators and other general-purpose automotive or industrial loads. In particular, the A3942 is suited for driving glow plugs, valves, solenoids, and other inductive loads in engine management and transmission systems. The device is available in a 38-lead thin (1.20 mm maximum overall height) TSSOP package with six pins that are fused internally to provide enhanced thermal dissipation (package LG). It is lead (Pb) free with 100% matte tin leadframe plating. Package: 38 pin TSSOP (suffix LG) Approximate Scale 1:1 Typical Application VDD CP1 CP2 CP3 CP4 VDD VCP VBB IREF VREG FAULTZ SDO SDI System Control Logic D1 A3942 G1 S1 D2 CSZ SCLK G2 S2 RESETZ ENB IN1 IN2 IN3 D3 G3 S3 D4 IN4 G4 GND GND GND GND GND GND S4 3942-DS, Rev. 5 VBAT Quad High-Side Gate Driver for Automotive Applications A3942 Selection Guide Part Number A3942KLGTR-T Packing 4000 pieces per reel Absolute Maximum Ratings* Characteristic Symbol Notes VBB, CP1, CP3 Pins Voltage Dx (Drain Detect) Pins Voltage VDx Sx (Output Source) Pins Voltage VSx Rating Units –0.3 to 60 V VBB – 6 V to VBB + 0.5 V V –10 to 60 V VCP, CP2, CP4, Gx Pins Voltage –0.3 to 74 V All Other Pins –0.3 to 7 V –40 to 125 ºC 150 ºC Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) Range K –55 to 150 ºC ESD Rating, Human Body Model AEC-Q100-002, all pins 2500 V ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V Storage Temperature Tstg *With respect to ground. Exceeding maximum ratings may cause permanent damage. Correct operation is not guaranteed when absolute maximum conditions are applied. Thermal Characteristics Characteristic Package Thermal Resistance, Junction to Ambient Symbol RθJA Test Conditions* 4-layer PCB based on JEDEC standard, with no thermal vias Rating Units 47 ºC/W *For additional information, refer to the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Quad High-Side Gate Driver for Automotive Applications A3942 Functional Block Diagram CP4 C34 CDD VDD CP3 Charge Pump Reference Current IREF VDD UVLO CP2 C12 Thermal Warning CP1 60.4 kΩ CREF VCP UVLO VCP CCP Fault Monitor FAULTZ U V Internal L Regulator O SDO SDI CBB2 VBB CBB1 VREG CREG VDD CSZ SCLK Control Logic RESETZ Vds Monitor Voltage to VBB pin and to Qx MOSFETs must come from the same supply One of Four High-Side Drivers RDx Dx VCP ENB IN1 High Side Driver IN2 RGx Gx Qx IN3 Open Load Detect IN4 Sx L GND Name GND GND GND Suitable Characteristics GND L GND Representative Device C12, C34 0.33 μF or 0.47 μF, 25 V, X7R ceramic CBB1 47 μF, 63 V, electrolytic CBB2 0.22 μF, 100 V, X7R ceramic CCP 1 μF, 16V, X7R ceramic CDD 0.47 μF, 16 V, X7R ceramic CREF 47 pF, 16 V, X7R ceramic CREG 0.22 μF, 16 V, X7R ceramic EGXE630ELL470MJC5S Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Quad High-Side Gate Driver for Automotive Applications A3942 ELECTRICAL CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Units 4.5 – 60 V VBB = 60 V – – 10 mA VBB = 36 V – – 8 mA VBB = 36 V – – 15 μA VBB = 36 V, TJ = 25°C – – 1 μA 3 – 5.5 V Supplies and Regulators Operating Voltage Quiescent Current VBB IBB(Q) Charge pump on, outputs disabled Sleep mode Logic Supply (voltage supplied to logic circuits) VDD Logic Supply Current IDD VDD = 5.5 V, serial port switching – – 3 mA VDD = 5.5 V, device quiescent or in sleep mode – – 0.5 mA 2.6 – 2.9 V VDD falling, FAULTZ pin held active (low) for 1.5 V ≤ VDD ≤ VDDUV Logic Supply UVLO Threshold VDD(UV) Logic Supply UVLO Hysteresis VDD(hys) 100 150 200 mV Charge Pump Switching Frequency fCP – 100 – kHz VBB = 12 V, ICP = 10 mA 10 – 13 V Charge Pump Output Voltage VCP VBB = 6.0 V, ICP = 5 mA 10 – 13 V VBB = 4.5 V, ICP = 5 mA 7 – 11 V 5.1 – 5.8 V – 4 – V Charge Pump UVLO Internal Regulator Voltage VCP(UV) VREG Regulator Voltage UVLO VREG(UV) Regulator Voltage UVLO Hysteresis VREG(hys) Measured relative to VBB pin Relative to VBB pin, VCP falling CREG = 0.22 μF VREG falling 3 – 3.8 V 100 – 400 mV Control Circuits Current Reference Source Voltage VREF 1.14 1.2 1.26 V Master Reset Pulse tRESET RESETZ pin pulsed low 0.3 – 5 μs Sleep Command tSLEEP RESETZ pin held low 20 – – μs Wake-Up Delay tWAKE RESETZ pin held high; CCP = 1 μF – – 2 ms Logic I/O Logic Input Voltage, High VIH 0.7 × VDD – VDD V Logic Input Voltage, Low VIL 0 – 0.3 × VDD V Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Quad High-Side Gate Driver for Automotive Applications A3942 ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted Characteristics Logic Input Hysteresis Symbol Test Conditions Vhys CSZ pin II(HI) FAULTZ Pin Inactive (High) Current Typ. Max. Units 0.1 × VDD – – V – – 10 μA – – 5 μA – – 100 μA – – –100 μA – – –5 μA All other pins – – –10 μA VOUT(HI) IOUT = –1 mA VDD – 0.5 – VDD V VOUT(LO) IOUT = 1 mA – – 0.4 V CSZ pin II(LO) FAULTZ Pin Active (Low) Voltage VI = VDD = 5.5 V All other pins Logic Input Current1 Logic Output Voltage, SDO Pin (CMOS push-pull circuit) SDI and SCLK Pins Min. VFAULTZ(LO) IFAULTZ(HI) SDI and SCLK Pins VI = 0 V IFAULTZ = 1 mA, VDD = 1.5 V, VBB = 4.5 V – – 0.4 V VFAULTZ = 5 V – – 10 μA Drivers Gate Voltage, High VG(HI) Measured relative to Sx pin, capacitive load–fully charged VCP –1 – VCP V Gate Voltage, Low VG(LO) Measured relative to Sx pin, capacitive load–fully discharged – – 0.1 V VBB = 4.5 V, VCP = 9 V –10 – – mA VBB ≥ 9 V, VCP = 13 V –15 – – mA RG = 0 Ω, VGS = 1 V, VSx = 0 V 10 – – mA RG = 0 Ω, 2 V ≤ VGS ≤ 4 V, VSx = 0 V 25 – – mA IG(HI) Peak Gate Current1,2 IG(LO) Propagation Delay Gate-to-Source Resistance Gate-to-Source Zener Diode Voltage Drain Leakage Current RG = 0 Ω, 1 V ≤ VGS ≤ 4 V, VSx = VBB tp(on) From 90% VINx to VGx – VSx = 200 mV – 0.6 – μs tp(off) From 10% VINx to VCP – VGx = 200 mV – 0.6 – μs RGS RESETZ pin held low; VGSZ = 10 V 300 500 800 kΩ IG = 2 mA 15 – 18 V RESETZ pin held low, VBB = VDx = 60 V – – 10 μA TJ = 150°C – – 5 μA TJ = 25°C – – 1 μA VGS(Z) IDlkg RESETZ pin held low, VBB = VDx = 36 V Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Quad High-Side Gate Driver for Automotive Applications A3942 ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Units 75 100 125 μA VBB = 36 V 85 100 120 μA VBB ≥ 9 V VBB –3 – VBB + 0.2 V VBB = 6 V 5 – VBB + 0.2 V VBB = 4.5 V 4 – VBB + 0.2 V –48 – –82 μA 1.4 1.5 1.6 V Driver Fault Detection Drain Fault Detect Current Drain Fault Detect Voltage3 IDx VDx Open Load Detect Source Current1 IOL Open Load Detect Voltage VOL Open Load VSx Clamp Turn-On Blank Time VBB = 60 V VSx = 1.35 V; 4.5 V ≤ VBB ≤ 36 V VCLAMP Active (when an open load fault is active), VBB ≤ 36 V – – 5 V ICLAMP Current limit in short-to-battery; VSx =VBB = 36 V – – 200 μA tON(00) 2.5 – 3.4 μs tON(01) 3.7 – 5.9 μs 5.6 – 11.2 μs tON(10) tON(00) is the default, TJ = 150°C tON(11) 8.9 – 22.3 μs Turn-Off Blank Time tOFF – tON – μs Short-to-Ground Fault Detect Filter Delay tSTG – 1 1.2 μs From VSx < VDx to 90% VFAULTZ STB Comparator Offset Voltage VOS(STB) – – 60 mV STG Comparator Offset Voltage VOS(STG) – – 45 mV 155 165 175 °C – 15 – °C Temperature Monitor Thermal Warning Threshold4 TWARN Thermal Warning Hysteresis TWARN(hys) Temperature rising 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2For IG(HI) , VCP relative to VBB. 3Minimum values of VDx are specified only to avoid short-to-battery nuisance faults. For more information, refer to the Open Load Fault Level topic in the Applications Information section. 4Minimum and maximum not tested; guaranteed by design. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Quad High-Side Gate Driver for Automotive Applications A3942 SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C and VBB and VDD within limits, unless otherwise noted Characteristics Transfer Frequency Symbol Test Conditions Min. Typ. Max. Units f – – 8 MHz Setup Lead Time tlead 375 – – ns Setup Lag Time tlag 50 – – ns Setup Time Before Read tsu 15 – – ns Access Time Before Write ta – – 340 ns 2 – – μs – – 100 ns TSCLK 125 – – ns Serial Clock Pulse Width, High tw(HI) 50 – – ns Serial Clock Pulse Width, Low tw(LO) 50 – – ns th(SCLK) 300 – – ns Chip Selection Inactive Time Delay Before Output Disabled Serial Clock Period Serial Clock Hold Time tCSZN tdis Serial Data In Hold Time th(SDI) Serial Data Out Hold Time th(SDO) Serial Data Out Time Before Valid State CSDO = 100 pF tvs CSDO = 0 pF 20 – – ns CSDO = 0 pF 0 – – ns CSDO = 100 pF, VDD = 3 V – – 120 ns CSDO = 100 pF, VDD = 4.75 V – – 80 ns Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Quad High-Side Gate Driver for Automotive Applications A3942 Serial Peripheral Interface (SPI) Timing Diagram tCSZN CSZ TSCLK tlead SCLK tw(HI) tw(LO) tvs ta SDO th(SCLK) tlag HI-Z D7 D6 DON’T CARE D0 th(SDI) tsu SDI tdis th(SDO) D7 D6 D0 Fault System Block Diagram VBB Short to Battery Gx Off 8V System and Load Faults FAULTZ Mask Gx On Gx On VDS Delay Sport OSC Write Gx On RGx Gx Gx Off RGS IOL Clear Read Dx VCP Short to Ground Logic Serial Port RDx IDx Sx VBB Open Load Gx Off VOL Vclamp L O A D Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Quad High-Side Gate Driver for Automotive Applications A3942 Input SettingsTiming Chart Timer is running for turn-on blank time Timer is running for turn-off blank time INx tp(on) IGx tp(off) Gate begins to charge VGS = VTH VGSx Set blank time to expire after VSx nears VBB Set blank time to expire after VSx nears 0 V VBB VSx Fault Logic Table Circled data cells indicate default settings, X indicates “don’t care”, Z indicates high impedance state Causes Effects RESETZ ENB VDD UVLO VCP UVLO Open Load Short-to-Battery Short-to-Ground Off-State Faults Masked Thermal Warning FAULTZ Gx VCP VREG Channel-Specific 1 0 0 0 0 0 0 X 0 1 0 1 1 Gates actively pulled low 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X 0 0 X 0 0 0 X X 1 0 1 0 1 0 1 INx INx INx 1 1 1 1 1 1 Normal operation FAULTZ issued but A3942 fully operational Normal operation, OL and STB masked 1 1 1 X X X 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 X 0 0 X X X 0 0 0 0 0 0 1 1 1 1 1 1 STG cannot be masked STB OL 1 1 X X 0 1 1 0 X X X X X X X X X X 0 0 0 0 UV 1 1 1 VCP UVLO disables outputs only VDD UVLO disables outputs only 0 X X X X X X X X 0 Z 0 0 Sleep mode Mode of Operation Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Quad High-Side Gate Driver for Automotive Applications A3942 Serial Port Registers Description There are two 8-bit registers served by the serial port, the Input register and the Output Fault register. The structure of the registers is shown in the table at the bottom of this page. The function of each bit in the registers is described in this section. time for the VDS monitor, according to the following table: D2 D1 tON Selected 0 0 tON(00)* 0 1 tON(01) Input Register 1 0 tON(10) D0 Gate On/Off Bit This bit is used to control the gate 1 1 tON(11) drive output. It is logically ORed with the signal on the discrete input pin, INx, corresponding to each of the four channels, according to the following table: *default state at device power-on D3 Clear Faults Bit This bit is used to clear a latched Bit D0 Pin INx Result on Gx Pin 0 0 Off 0 1 On fault. After the fault is cleared, the gate output can again follow the input logic to determine if the fault is still present. Faults are cleared on a channel specific basis. 1 0 On D4 Mask Off-State Faults Bit [See asterisks (*) in 1 1 On the table below.] When the application requires that Short-to-Battery (STB) and Open Load (OL) faults be checked primarily before output is enabled for the first time, this bit can be used to allow STB and Open Load faults to be ignored during normal operation (Short-toGround faults can not be masked). This bit is applied ORed Settings D1, D2 Short-to-Ground (STG) Turn-On Blank Time MSB and LSB Bits The blank time, ton(xx), delay allows switching transients to settle before the A3942 STG function checks for a short. For each individual channel, the combination of these bits sets the wait Serial Port Bit Definition All bits active high, except WriteZ Bits Register D7 D6 Input Address MSB Address LSB Output Fault Address MSB Address LSB D5 Input Read Enable D4 Mask Off-State Faults (*) WriteZ Charge Pump UVLO D3 Clear Faults Thermal Warning D2 STG Blank Time MSB D1 STG Blank Time LSB D0 Gate On/Off Open Load Fault (*) STB Fault (*) STG Fault Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 Quad High-Side Gate Driver for Automotive Applications A3942 on a channel-specific basis, according to the following table: D4 Setting Handling of Off-State Faults 0 Registered 1 Ignored D5 Read Enable Bit This bit enables or disables read- ing on the serial inputs, according to the following table: Handling of Serial Input D5 Setting 0 Ignored 1 Registered D6, D7 Address MSB and LSB Bits (Input and Output Fault registers) For channel-specific bits, these bits are used to specify which channel is indicated. The channel-specific bits are: Register Channel-Specific Bits Input D0, D1, D2, D3, D4 Output D0, D1, D2 These bits determine the channel, according to the following table: D7 D6 Channel Selected 0 0 1 0 1 2 1 0 3 1 1 4 Output FAULT Register D0 Short-to-Ground (STG) Fault Bit The voltage from drain to source for each MOSFET is monitored. An internal current source sinks IDx from the Dx pins to set the VDS threshold for each channel, the level at which an STG fault condition is evaluated. The A3942 enables monitoring for an STG fault after the MOSFET is turned on and the turn-on blank time, tON , expires. (The MOSFET is turned on via the Input register D0 bit, ORed with the INx discrete input pin for the channel of the MOSFET, and tON is set by Input register D1 and D2 bits). If the MOSFET gateto-source voltage exceeds the VDS threshold, then an STG fault will be registered for that channel, the MOSFET gate will be discharged, and the FAULTZ pin will be set low (active). An STG fault is latched until cleared (using the Input register D3 bit). In the meantime, the other channels can continue to operate normally. D1 Short to Battery (STB) Fault Bit When a chan- nel turns off, STB fault detection is blanked for tOFF. Subsequently, if the Sx pin voltage exceeds the VDS threshold voltage for that channel, an STB fault is latched. The output for that channel is disabled until the fault is either cleared (via the Input register D3 bit) or the off-state fault diagnostics are masked (via the Input register D4 bit). Because the output is disabled, there is no active pull-down during an STB event. Note that, in general, when the voltage on SX is high enough to trip the STB comparator, it also trips the OL comparator, and both the STB and the OL faults are latched. D2 Open Load (OL) Fault Bit When a channel turns off, the OL fault is blanked for tOFF. A small bias current, IOL , is sourced to the Sx pin of the channel. There it divides between RSx and the load. If the load is open, the Sx voltage will rise above the OL fault detection threshold. In that case, the output is disabled until the fault is cleared (via the Input register D3 bit) or the off-state fault diagnostics are masked (via the Input register D4 bit). D3 Thermal Warning Bit A die temperature monitor is integrated on the A3942 chip. If the die temperature Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A3942 approaches the maximum allowable level, a thermal warning signal will be triggered. Note that this fault sets the FAULTZ pin low (active), but does not disable the outputs or operation of the chip. D4 Charge Pump UVLO Bit The charge pump must maintain a voltage guard band above VBB , in order to charge the gates when commanded to turn on the MOSFETs. If an undervoltage (UVLO) condition is detected on the charge pump, the FAULTZ pin will be set low (active), and all outputs will be disabled. D5 WriteZ (Not Write) Bit In a written byte, D5 = 0. D6, D7 Address Bits See description, above. Pin Descriptions In this section, the functions of the individual terminals of the A3942 are described. VBB Supply Voltage (Power) The A3942 is fully operational over the specified range of VBB. The external MOSFETs must be supplied by the same voltage source as the A3942. A bypass capacitor should be placed as close as practicable to the A3942. VDD Supply Voltage (Logic) Logic voltage must be Quad High-Side Gate Driver for Automotive Applications IN1 through IN4 Discrete Inputs For each output channel, the gate pin, Gx, sources voltage when the corresponding INx pin is set high. Gx sinks voltage to ground when the corresponding INx pin is set low. The INx setting is logically ORed with the Gate On/Off bit (Input register bit D0) for the respective output. D1 through D4 Output Drains For each output channel, the voltage on the corresponding Dx pin is used to evaluate STB and STG fault conditions. The A3942 compares the Dx voltage level to the VDS threshold of the MOSFET to determine if a fault condition exists. The trip voltage level is set by selecting an appropriate value for the resistor, RDx, connected to the corresponding current sink. Because both the Dx pins and RDx are high impedance, each RDx must be placed as close to the corresponding A3942 Dx pin as practicable. G1 through G4 Output Gates These pins drive the gates of the high-side external MOSFETs. They source voltage from VCP and sink to GND. The corresponding external gate resistors, RGx, should be ≥ 2 kΩ for consistent switching times between A3942s when applicable (see IG(HI) and IG(LO) in the Electrical Characteristics table). supplied to the A3942. The wide allowable range of input voltages allows both 3.3 V and 5 V supplies. A bypass capacitor should be placed as close as practicable to the A3942. If negative voltages are applied, Gx is clamped to GND by internal diodes. Back-to-back Zener diodes are internally connected between Gx and Sx. VCP Charge Pump The integrated charge pump is source terminal of the external MOSFET. The pins may be tied directly to the MOSFET. Although the Sx pins can survive large negative transients, it is recommended to connect a clamp diode between the Sx pin and ground to limit any negative transients at the Sx pin when a load is switched off. This helps to avoid false fault detection caused by transient noise coupling into adjacent channels which may not be switching and therefore have no fault blanking during the transient. This is especially recommended when there is significant wiring between the load and the Sx pin even if the load incorporates a recirculation diode. used to generate a supply above VBB to drive the gates of the external power MOSFETs. This tripler keeps the part functional over a wide range of VBB. CP1 through CP4 Charge Pump Capacitor Connections These are the connections for the two exter- nal capacitors that level-shift the charge up to VCP . VREG Internal Linear Voltage Regulator This pro- vides a connection for an external capacitor that sets the regulation value for voltage supplied to internal logic circuits. Sx Output Sources These are used to measure the Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A3942 RESETZ Master Reset and Sleep Mode Pulsing this pin low clears all latched faults in the channel-specific fault registers. It also clears the serial port registers (they return to their default values). When RESETZ is held low long enough (t > tSLEEP) the A3942 goes to sleep, as described in the Sleep topic in the Functional Description section. ENB Enable Set low to actively pull low all outputs. FAULTZ Fault Active low open drain output. Signals a Quad High-Side Gate Driver for Automotive Applications be charged at typically 240μA until it reaches VREF. The time taken to charge the capacitor will be approximately: tCHARGE = 5 × C where tCHARGE is in μs and C is the capacitor value in nF. At least twice this time should be allowed, after power-on or after coming out of sleep mode, before the A3942 is used to switch any loads. Functional Description section. GND Ground All GND pins are internally fused to the metal die pad to which the chip is soldered. This allows for high thermal conductance through the GND pins. Connecting to these pins to a PCB ground plane improves thermal performance. CSZ SPI Chip Select input. Functional Description SDO SPI Data Output connection. Power On When power is applied to either VDD or fault. Allows parallel connection with FAULTZ signals from other devices when required. SCLK SPI Clock See Serial Port Operation topic in SDI SPI Data Input connection. IREF Current Reference Defines the current used as a reference to set gate drive currents, diagnostic currents and internal timers. A resistor, RREF, connected between the IREF pin and the adjacent GND pin is selected to set the reference current to 20μA. The IREF pin is a voltage source at a voltage, VREF, of typically 1.2V. The resistor required is therefore 60.4kOhm, which is the standard resistor value that provides a typical current closest to the 20μA target. Any variation in RREF will affect the internal settings as described in the section below on RREF selection. Being a high impedance node, the IREF pin is susceptible to external sources of noise and transients and should be decoupled with a capacitor across RREF between the IREF pin and the adjacent GND pin. The capacitor value should be less than 100pF to avoid any delay when power is first applied to the A3942 or when coming out of sleep mode. When controlling large load currents a larger capacitor may be required to suppress any transient noise. At power-on or when coming out of sleep mode this capacitor will VBB, the Output Fault register is initially loaded with default values, all zeros (0). However, as individual internal circuits are initially powered on, they may latch spurious faults in the fault registers for each channel. Therefore, before operating the A3942 all fault registers must be cleared by pulsing the RESETZ pin. Sleep Mode This mode disables various internal circuits including the charge pump, VREG, and the logic circuits. The serial port also is disabled. All Input and Output Fault register bits are cleared. To leave sleep mode, pull RESETZ high and then allow a delay for the charge pump to stabilize. Before sending commands, clear any spurious faults as described in the Power On topic. Faults Faults are categorized either as system faults or load faults. All faults are ORed to the FAULTZ pin. System faults are VREG UVLO, CP UVLO, VDD UVLO, and Thermal Warning. They are not latched in the channel-specific self-protection circuit fault registers, however, the flags in the Output Fault register Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A3942 bits D3, D4, and D5, are latched. If the fault condition is resolved, these flags are latched until they are read, at which time they are cleared. Load faults are OL, STB, and STG. They are latched into the channel-specific self-protection circuit fault registers, and shifted into Output Fault register bits D0, D1, and D2 when called. Thus, load faults may be masked or cleared on a channel-specific basis. Serial Port Operation The serial port is compatible with the full duplex Serial Peripheral Interface (SPI) conventions. The inputs to the SPI port are logically ORed with the discrete input pins, INx, settings. This allows independent operation using only the discrete inputs, only the serial inputs, or both. Timing is clocked by an onboard 4 MHz oscillator. When a Chip Select event occurs, the Output Fault register loads one eight-bit byte into the shift register, and the byte is then shifted out through the SDO pin. Simultaneously, bits at the SDI pin are shifted into the shift register (full duplex). At the end of a Chip Select event, the shift register contents are latched into the Input register. Quad High-Side Gate Driver for Automotive Applications • Daisy Chain Connection The master shifts n bytes (eight bits each) during n × 8 clock cycles. Regardless of the position of an individual A3942 slave in the daisy chain, the slaves shift the output byte during the first eight clock cycles after CSZ goes low. When CSZ goes high, the eight bits in the Shift register are latched into the Input register. Serial Port Disabling Disable the serial port by setting the CSZ pin high while in sleep mode. This loads the Input register with default values, all zeroes (0). Serial Port Error Handling Input data is discarded if the number of bits in an input stream are not a multiple of eight. Furthermore, unless the number of clock cycles is a multiple of eight while CSZ is active, any bits shifted in from the SDI pin are discarded. Input Register Operation After a valid byte is latched into the Input register from the shift register, bit D5 is evaluated to determine if the byte is to be read. An inactive (0) bit value causes all other bits to be ignored. Alternative Configurations Multiple A3942s can be If bit D5 is active (1) the other bits are read and decoded. Bits D6 and D7 are used to determine which output channel is updated. Bits D0 through D4 set the channel-specific operation, including clearing and masking of faults. configured together. Output Fault Register Operation This register is • Standalone Connection In this configuration, the master simultaneously shifts eight bits in through the SDI pin and shifts eight bits out of the SDO pin. First, the CSZ pin is set low. Then, the Output Fault register is loaded with the relevant fault byte (see the Output Fault Register topic below). Eight clock cycles are used to perform the shifts. • Parallel Connection Because each slave has a CSZ pin, operation is identical to the Standalone configuration. When CSZ is inactive, SDI is “don’t care” and SDO is high impedance. loaded with fault data to be shifted out through the SDO pin. No handshaking is required. The Output Fault register contains data on active faults. Four internal channel-specific fault registers contain any latched fault data for each respective channel. The following describes how the A3942 determines which channel-specific fault register to transfer into the Output Fault register. • No Faults If there are no current faults, the Output Fault register is loaded with all zeros: 00 000 000 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A3942 • Single Fault If there is only one fault detected, the Output Fault register is filled to indicate that fault. For a load fault, the Address bits are set to indicate the affected channel; for example, a short-to-battery on channel 3 would be written: 10 000 010 On the other hand, for system faults, the Address bits are irrelevant, and a CP UVLO fault would be loaded as: 00 010 000 with the Address bits defaulting to 0 0. • Multiple System Faults If there are multiple system faults, the Output Fault register is loaded with the setting for each system fault (the Address bits remain irrelevant, as in the case of a single fault). For example, when CP UVLO and Thermal Warning faults both have occurred, the Output Fault register is loaded with: 00 011 000 • Multiple System Faults and Single Channel Load Fault If one or more system faults and one or more load faults from a single channel have occurred, all faults are loaded into the Output Fault register, with the channel of the load faults indicated in the Address bits. For example, a CP UVLO system fault and an STG load fault on Channel 2 would be written as: 01 010 001 • Multiple Channel Load Faults When load faults occur on more than one channel, the data cannot be signalled in a single SDO byte. However, the data can still be retrieved. The A3942 polls each channelspecific fault register, in ascending order by channel number. Each output is delimited by the appropriate CSZ event. For example, assume an OL on channel 2 and an STG on Channel 4. The first CSZ event writes: 01 000 100 Quad High-Side Gate Driver for Automotive Applications and the second CSZ writes: 11 000 001 In summary, all faults are retrieved by issuing consecutive CSZ events until the channel number stops increasing. • If there are no faults, this byte will be shifted out each time: 00 000 000 • If there are only system faults, this byte will be shifted out each time: 0 0 [1|0] [1|0] [1|0] 0 0 0 • If there are system faults and only one load fault, one byte contains all of the fault data. • If there are load faults on more than one channel, these bytes would be shifted out in succession, and any existing system faults will be indicated. For example, if there were no system faults and load faults on channels 2, 3, and 4, the following series of bytes would be shifted out: 0 1 0 0 0 [1|0] [1|0] [1|0] 1 0 0 0 0 [1|0] [1|0] [1|0] 1 1 0 0 0 [1|0] [1|0] [1|0] 0 1 0 0 0 [1|0] [1|0] [1|0] . . . Applications Unused Outputs When any of the four output chan- nels are not used, the related pins should be connected as follows: Unused Channel Pin Connection INx GND Sx GND Dx VBB Gx Floating RREF Selection The tolerance on RREF can be as high as ±4%. Depending on how a specific part Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Quad High-Side Gate Driver for Automotive Applications A3942 changes over temperature changes and lifetime, the ±4% range generally covers nominal 1% resistors. The parameters which are affected by changes in RREF are listed in the following table: Change as RREF Tolerance Parameter Increases Decreases IREF – + tRESET + – tSLEEP + – tWAKE + – IG(HI) and IG(LO) – + IOL – + tON and tOFF + – Setting Fault Circuit Trip Levels The load faults, Short-to-Battery (STB), Short-to-Ground (STG), and Open Load (OL), are all latched. The thresholds for STG and OL faults can be set by the value for the RDx resistor. Open Load Fault Level When the gate is commanded off, a commanded current, IOL , is sourced to Sx to detect if the load is still in the circuit. VOL is compared to IOL × [RL // RGS] to evaluate an OL fault. If the load has been removed, VSx exceeds VOL and a fault is registered. VSx would drift to VBB when an open load exists and thereby inadvertantly trip a nuisance STB fault. To prevent this, the Sx pin is clamped to VCLAMP . The operating limits specified in the Electrical Characteristics table allow the fault circuitry to distinguish all faults within the operating range of VBB. If, however, the specified limits on VDx are too restrictive at low VBB levels, the only repercussion is a nuisance STB fault, and this only occurs when an OL condition exists. The limit on VDx can be ignored either if the off-state faults are masked or if it is acceptable to latch the nuisance fault and clear it when the OL fault is cleared. Because VOS << VOL , a fault is registered if IOL × RL // RGS > VOL . Hence, the trip level, RL(trip) is: 1 ⎛ –1 ⎛ IOL ⎜ ⎜ – RL(trip) = ⎜ ⎜ ⎝ VOL RGS ⎝ The OL circuit and its tolerances are designed to ensure that external loads above 50 kΩ are identified as open load and that loads below 10 kΩ are identified as valid. Note that these numbers are valid in steady state. As a result, blanking times must be set appropriately for a given load. Under normal conditions, when the external MOSFET is off, and the load is in circuit, IOL × RL < VOL. Short-to-Battery Fault Level The STB comparator compares the load voltage IOL × RL // RGS] to the voltage set by RDx, VBB –ID × RD . The comparator is active only when the gate is commanded off. During an STB condition, IOL = 0 because the current source has run out of headroom. A fault is registered when VL > VBB –ID × RD ± VOS. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Quad High-Side Gate Driver for Automotive Applications A3942 That is, the load voltage is within ∆V = ID × RD volts of VBB. Using VDS = VBB – VL and rearranging, we find that VDS < ID × RD ± VOS . Therefore, RD = (VDS(trip) ±VOS) / ID , Power Limits Power dissipation, PD, is limited by thermal constraints. The maximum junction temperature, TJ(max), and the thermal resistance, RθJA , are given in this datasheet. The maximum allowed power is then found for a given ambient, TA , from this equation: TJ = PD × RθJA + TA , or PD = (TJ – TA ) / RθJA . which is also the case for STG faults, described below. Note that an STB condition generally latches the OL flag as well. The three main contributions to power dissipation are: Under normal conditions RL << RGS and IOL flows through the load, given • driver outputs, PDRV , and IOL × (RD + RL ) < VBB –ID × RD ± VOS . Because IOL × (RD + RL ) ≈ 0 when the external MOSFET is off, no fault is registered. Short-to-Ground Fault Level The effect of the STG comparator is to compare the external MOSFET VDS (VL) to the set trip voltage VBB –ID × RD . The comparator is active only when the gate is commanded on. Also, the sourced current IOL is deactivated. If VDS is too large, an STG fault is registered when VL < VBB –ID × RD ± VOS , or, because the external MOSFET VDS = VBB – VL , VDS > ID × RD ± VOS . Therefore, the STG trip level in the on state is the same as the STB level in the off state: RD = (VDS(trip) ±VOS) / ID . Converse to the preceding, in normal operation • quiescent supply, PBB(Q) • logic level supply, PDD . These three terms appear in the following equation: PD = PBB(Q) + PDRV + PDD . The quiescent supply current leads to a baseline power loss: PBB(Q) = VBB × IBB(Q) . In general, the losses in a driver can be quantified as follows. Given that the driver current leaves Gx to charge a gate, and assuming that the external circuit is approximately lossless, then the same charge is sunk back into Gx. Therefore, all driver current can be treated as going to heat the chip. Total current into VBB includes the quiescent current, IBB(Q) , plus additional current, ∆IBB, to energize the gates. The latter is three times the average gate current: ∆IBB = 3 × IGx(av) . VL > VBB –ID × RD ± VOS , The average load current is calculated using the gate charge, QG , from the external MOSFET datasheet and the switching frequency: VDS < ID × RD ± VOS . IGx(av) = fsw × QG . or Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Quad High-Side Gate Driver for Automotive Applications A3942 If all four outputs are supplying this current, ∆IBB = 4 (3 × IGx) = 12 × fSW × QG, and PDRV = VBB × ∆IBB = 12 × fSW × QG × VBB . Finally, loss in the logic circuits is PDD = VDD × IDD. Example: Find the junction temperature with one IRFZ44ES MOSFET at each output, being switched at 5 kHz, and given VBB = 14 V and VDD = 5.5 V. Answer: The IRFZ44ES datasheet gives QG(max) = 60 nC (note that this parameter depends on circuit design constraints, such as VDS). The Electrical Characteristics table gives the following maximum values for the A3942: IBB(Q) = 10 mA, VDD = 5.5 V, and IDD = 3 mA. First, calculate total power loss: PD = VBB IBB(Q) + 12 fswQGVBB+VDDIDD = 14 V × 11 mA + 4 × 3 × 5 kHz ×60 nC × 14 V + 5.5 V × 3 mA = 221 mW . Then, the junction temperature can be found for a given ambient temperature; TA = 125°C is assumed here. Thermal resistance depends significantly on the board design; RθJA = 100 °C/W is assumed here. Substituting these values: TJ = PD × RθJA + TA = 221 mW × 100 °C/W + 125°C = 147°C . LAYOUT AND COMPONENTS General good practices should be followed. In addition, the following are recommended: • Locate bypass capacitors (VBB, VDD, VREG, and IREF) as close to the A3942 as practicable. • Traces to bypass capacitors should be as wide as practicable; minimize the number of vias. • Use both bulk storage capacitors (for example, electrolytic) and low impedance bypass capacitors (for example, ceramic) on all supply pins. See the Functional Block Diagram for recommended values. • Input and output lines should not be in close proximity. If they do overlap, it should be at right angles. • Use ample copper in the ground and power paths. Use planes or fills where possible. • The A3942 ground and VBB supply should be starconnected to the power ground and supply. • The trace connecting the RDx resistors to the A3942 Dx pins should be as short as possible. • The trace leaving the other side of the RDx resistors can be long because it has a low impedance path to ground; however, it must run independently to the respective external MOSFET in order to make a Kelvin connection. • All support capacitors are to be referenced to the A3942 ground plane or ground fill. Minimize loop area of traces. • These traces should be as wide as practicable: VBB, VDD, VREG, VCP, and Gx. Secondarily, it is also preferred that the traces to the charge pump caps be as wide as practicable. In both cases, the number of vias should be minimized. • Minimize the distance connecting to ground pins in order to minimize ground loops. Finally, a note about thermals. Because the A3942 ground pins are internally fused to the die mounting pad, they are the main path for heat dissipation. In applications producing high junction temperatures, care must be given to designing the thermal path. For example, multiple thermal vias should be run from ground pins down to the ground plane. If space allows, wide traces from ground pins to exposed copper fills on the top layer efficiently release heat through convection cooling. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Quad High-Side Gate Driver for Automotive Applications A3942 Terminal List No. Name 1 SDO Serial Data Out Pin Description 2 SDI Serial Data In 3 SCLK 4 CSZ Serial Clock Chip Select – NOT 5 FAULTZ Fault – NOT (Open Drain) 6 RESETZ Reset – NOT (Discrete) 7 ENB Enable (Discrete) 8 VDD Logic Supply Current Reference Pin 9 IREF 10 GND 11 IN2 Discrete Input Channel 2 12 IN1 Discrete Input Channel 1 13 D2 Channel 2: Drain 14 D1 Channel 1: Drain 15 GND 16 S1 Channel 1: Source 17 G1 Channel 1: Gate 18 G2 Channel 2: Gate 19 S2 Channel 2: Source 20 S3 Channel 3: Source 21 G3 Channel 3: Gate 22 G4 Channel 4: Gate 23 S4 Channel 4: Source 24 GND 25 D3 Channel 3: Drain 26 D4 Channel 4: Drain 27 IN3 Discrete Input Channel 3 28 IN4 Discrete Input Channel 4 29 VREG 30 VBB 31 GND 32 VCP Reservoir Capacitor Terminal 33 CP1 Charge Pump Capacitor Terminal 34 CP3 Charge Pump Capacitor Terminal 35 CP2 Charge Pump Capacitor Terminal 36 CP4 Charge Pump Capacitor Terminal 37 GND 38 GND Internal Regulator Power Supply Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Quad High-Side Gate Driver for Automotive Applications A3942 LG Package, 38-Pin TSSOP 1.60 9.70 ±0.10 4º 0.50 38 0.30 38 +0.06 0.15 –0.05 4.40 ±0.10 6.40 ±0.20 6.00 A 1 2 1 2 0.25 38X SEATING PLANE 0.10 C 0.22 ±0.05 0.50 C B SEATING PLANE GAUGE PLANE All dimensions nominal, not for tooling use (reference JEDEC MO-153 BD-1) Dimensions in millimeters Pins 10, 15, 24, 31, 37, and 38 fused internally 1.20 MAX 0.10 ±0.05 PCB Layout Reference View A Terminal #1 mark area B Reference pad layout (reference IPC SOP50P640X110-38M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20