74VHC14 Hex Schmitt Inverter General Description Features The VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margin than conventional inverters. ■ High Speed: tPD = 5.5 ns (typ) at VCC = 5V ■ Low power dissipation: ICC = 2 μA (Max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (Max) ■ Pin and function compatible with 74HC14 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Order Number Package Number Package Description 74VHC14M (Note 1) M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC14MX_NL (Note 2) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC14SJ (Note 1) M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC14MTC (Note 1) MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14MTC_NL (Note 3) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14MTCX_NL (Note 2) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14N (Obsolete) N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free package per JEDEC J-STD-020B. Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only. Note 3: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Logic Symbol/s Connection Diagram/s IEEE/IEC Pin Descriptions Truth Table/s Pin Names Description An Inputs On Outputs www.fairchildsemi.com 2 A O L H H L Absolute Maximum Ratings(Note 4) Recommended Operating Conditions (Note 5) −0.5V to +7.0V Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) DC Output Voltage (VOUT) +2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA DC VCC/GND Current (ICC) ±50 mA Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The data book specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. −65°C to +150°C Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 0V to VCC −40°C to +85°C 260°C Note 5: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VP VN VH VOH VOL TA = 25°C TA = −40°C to +85°C Parameter VCC Positive Threshold Voltage 3.0 2.20 2.20 4.5 3.15 3.15 5.5 3.85 3.85 Negative Threshold Voltage Hysteresis Voltage HIGH Level Output Voltage LOW Level Output Voltage IIN Input Leakage Current ICC Quiescent Supply Current Min Typ Max Min Max 3.0 0.90 0.90 4.5 1.35 1.35 5.5 1.65 1.65 3.0 0.30 1.20 0.30 1.20 4.5 0.40 1.40 0.40 1.40 5.5 0.50 1.60 0.50 1.60 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 Units Conditions V V V VIN =VIL IOH = −50 μA V IOH = −4 mA V IOH = −8 mA VIN = VIH 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 0–5.5 ±0.1 ±1.0 μA VIN = 5.5V or GND 5.5 2.0 20.0 μA VIN = VCC or GND IOL = 50 μA V IOL = 4 mA V IOL = 8 mA Noise Characteristics Symbol Parameter TA = 25°C VCC Typ Limits Units Conditions VOLP (Note 6) Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL = 50 pF VOLV (Note 6) Quiet Output Minimum Dynamic VOL 5.0 −0.4 −0.8 V CL = 50 pF VIHD (Note 6) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF VILD (Note 6) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF Note 6: Parameter guaranteed by design. 3 www.fairchildsemi.com AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Time VCC 3.3 ± 0.3 5.0 ± 0.5 TA = 25°C Min TA = −40°C to +85°C Typ Max Min Max 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 5.5 8.6 1.0 10.0 7.0 10.6 1.0 12.0 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 21 10 Units ns Conditions CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 7) Note 7: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr) = CPD * VCC * fIN + ICC/6 (per Gate) www.fairchildsemi.com 4 Physical Dimensions 8 .7 5 8 .5 0 0 .6 5 A 7 .6 2 14 8 B 5 .6 0 4 .0 0 3 .8 0 6 .0 0 P IN O N E IN D IC A T O R 1 1 .7 0 7 0 .5 1 0 .3 5 1 .2 7 0 .2 5 (0 .3 3 ) 1 .7 5 M A X 1 .5 0 1 .2 5 1 .2 7 L A N D P A T T E R N R E C O M M E N D A T IO N M C B A S E E D E T A IL A 0 .2 5 0 .1 0 0 .2 5 0 .1 9 C 0 .1 0 C N O T E S : U N LE S S O T H E R W IS E S P E C IF IE D R 0 .1 0 A ) T H IS P A C K A G E C O N F O R M S T O JE D E C M S -0 1 2 , V A R IA T IO N A B , IS S U E C , B ) A L L D IM E N S IO N S A R E IN M ILLIM E T E R S . C ) D IM E N S IO N S D O N O T IN C LU D E M O L D G AG E PLANE FLASH O R BU R R S. D ) LA N D P A T T E R N S T A N D A R D : S O IC 1 2 7 P 6 0 0 X 1 4 5 -1 4 M 0 .3 6 E ) D R A W IN G C O N F O R M S T O A S M E Y 14.5M -1994 F ) D R A W IN G F IL E N A M E : M 14A R E V 13 0 .5 0 0 .2 5 X 4 5 ° R 0 .1 0 8° 0° 0 .9 0 0 .5 0 (1 .0 4 ) S E A T IN G P L A N E D E T A IL A S C A L E : 2 0 :1 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 0 .6 5 0 .4 3 T Y P 1 .6 5 6 .1 0 0 .4 5 12 .00°T O P & BOTTOM R 0.09 m in A . C O N F O R M S T O JE D E C R E G IS T R A T IO N M O -15 3, V A R IA T IO N A B , R E F N O T E 6 B . D IM E N S IO N S A R E IN M ILL IM E T E R S C . D IM E N S IO N S A R E E X C LU S IV E O F B U R R S , M O LD F LA S H , A N D T IE B A R E X T R U S IO N S D . D IM E N S IO N IN G A N D T O L E R A N C E S P E R A N S I Y 14.5M , 1982 E . LA N D P A T T E R N S T A N D A R D : S O P 6 5P 640X 110-14M F . D R A W IN G F ILE N A M E : M T C 14 R E V 6 1.00 R 0 .0 9m in 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 14 1 9 .5 6 1 8 .8 0 8 6 .6 0 6 .0 9 1 7 (1 .7 4 ) 8 .1 2 7 .6 2 1 .7 7 1 .1 4 3 .5 6 3 .3 0 0 .3 5 0 .2 0 5 .3 3 M A X 0 .3 8 M IN 3 .8 1 3 .1 7 0 .5 8 0 .3 5 8 .8 2 2 .5 4 N O T E S : U N LE S S O T H E R W IS E S P E C IF IE D T H IS P A C K A G E C O N F O R M S T O A ) JE D E C M S -001 V A R IA T IO N B A B ) A L L D IM E N S IO N S A R E IN M ILLIM E T E R S . D IM E N S IO N S A R E E X C L U S IV E O F B U R R S , C ) M O LD F LA S H , A N D T IE B A R E X T R U S IO N S . D ) D IM E N S IO N S A N D T O LE R A N C E S P E R A S M E Y 14.5-1994 E ) D R A W IN G F ILE N A M E : M K T -N 14 A R E V 7 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A www.fairchildsemi.com 8 9 www.fairchildsemi.com