DTS6401 www.din-tek.jp Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • P-Channel • 175 °C Operating Temperature • Dynamic dV/dt Rating • Low Thermal Resistance • Lead (Pb)-free Available - 60 RDS(on) (Ω) VGS = - 10 V 0.40 Qg (Max.) (nC) 12 Qgs (nC) 3.8 Qgd (nC) 5.1 Configuration Single TO-236 (SOT-23) G RoHS* COMPLIANT S 1 G 3 S Available D 2 D Top View P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at - 10 V TC = 25 °C TC = 100 °C SYMBOL LIMIT VDS VGS - 60 ± 20 - 5.2 - 3.8 - 21 0.18 120 - 5.2 2.7 27 - 4.5 - 55 to + 175 300d 10 1.1 ID IDM TC = 25 °C for 10 s 6-32 or M3 screw EAS IAR EAR PD dV/dt TJ, Tstg UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m Notes a. b. c. d. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). VDD = - 25 V, starting TJ = 25 °C, L = 5.0 mH, RG = 25 Ω, IAS = - 5.3 A (see fig. 12). ISD ≤ - 6.7 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 175 °C. 1.6 mm from case. 1 DTS6401 www.din-tek.jp THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 5.5 PARAMETER UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = - 250 µA - 60 - - V ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.060 - V/°C VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VDS = - 60 V, VGS = 0 V - - - 100 VDS = - 48 VGS = 0 V, TJ = 150 °C - - - 500 - - 0.40 Ω 1.6 - - S ID = - 3.2 Ab VGS = - 10 V VDS = - 25 V, ID = - 3.2 Ab µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Drain to Sink Capacitance VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 - 270 - - 170 - - 31 - f = 1.0 MHz - 12 - C Total Gate Charge Qg Gate-Source Charge Qgs VGS = - 10 V ID = - 4.7 A, VDS = - 48 V, see fig. 6 and 13b - - 12 - - 3.8 Gate-Drain Charge Qgd - - 5.1 Turn-On Delay Time td(on) - 11 - - 63 - - 9.6 - - 31 - - 4.5 - - 7.5 - - - - 5.2 - - - 21 - - - 5 .5 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = - 30 V, ID = - 4.7 A, RG = 24 Ω, RD= 4.0 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = - 5.2 A, VGS = 0 Vb TJ = 25 °C, IF = - 4.7 A, dI/dt = 100 A/µsb V - 80 160 ns - 0.096 0.19 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. 2 D DTS6401 www.din-tek.jp TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC= 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC= 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature 3 DTS6401 www.din-tek.jp Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area DTS6401 www.din-tek.jp RD VDS VGS D.U.T. RG +VDD - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit td(on) td(off) tf tr VGS 10 % 90 % VDS Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS IAS VDS D.U.T. RG VDS + V DD VDD IAS tp - 10 V tp 0.01 Ω VDS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms 5 DTS6401 www.din-tek.jp Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform 6 Fig. 13b - Gate Charge Test Circuit DTS6401 www.din-tek.jp Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel 7 Package Information www.din-tek.jp SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS INCHES Min Max Min Max A 0.89 1.12 0.035 0.044 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.95 BSC 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 1 Application Note www.din-tek.jp 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE 1 Legal Disclaimer Notice Disclaimer www.din-tek.jp ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Din-Tek Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Din-Tek”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Din-Tek makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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