A3958 DMOS Full-Bridge PWM Motor Driver Features and Benefits Description ▪ ±2 A, 50 V continuous output rating ▪ Low rDS(on) outputs (270 mΩ, typical) ▪ Programmable mixed, fast, and slow current-decay modes ▪ Serial interface controls chip functions ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal-shutdown circuitry ▪ Crossover-current protection Designed for pulse width modulated (PWM) current control of DC motors, the A3958 is capable of continuous output currents to ±2 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed currentdecay modes. Packages: PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required. Package B, 24-pin DIP with exposed tabs The A3958 is supplied in a choice of two power packages, a 24-pin plastic DIP with exposed thermal tabs (package suffix ‘B’), and a 24-pin SOIC with internally fused pins (package suffix ‘LB’). In both cases, the power pins are at ground potential and need no electrical isolation. Each package type is lead (Pb) free, with 100% matte tin leadframe. Package LB, 24-pin SOIC with internally fused pins Not to scale Functional Block Diagram VBB VDD LOAD SUPPLY CP CP1 CHARGE PUMP BANDGAP VDD CREG TSD CP2 + LOGIC SUPPLY CHARGE PUMP UNDERVOLTAGE & FAULT DETECT BANDGAP REGULATOR VREG CONTROL LOGIC OSC CLOCK DATA STROBE PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT PHASE ENABLE GATE DRIVE OUTA MODE SENSE ZERO CURRENT DETECT FIXED OFF PROGRAMMABLE BLANK DECAY PWM TIMER SERIAL PORT OUTB SLEEP MODE CURRENT SENSE RANGE CS RS REFERENCE BUFFER & DIVIDER REF VREF RANGE Dwg. FP-048 29319.31F A3958 DMOS Full-Bridge PWM Motor Driver Selection Guide Part Number Packing Package A3958SB-T* 24-pin DIP with exposed thermal tabs 15 per Tube A3958SLBTR-T 24-pin SOICW with internally fused pins 1000 per reel Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 2009. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 50 V Logic Supply Voltage VDD 7.0 V Input Voltage VIN –0.3 to VCC + 0.3 V Sense Voltage VS 0.5 V Reference Voltage VREF 2.7 V Output Current IOUT Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. ±2.0 mA Package Power Dissipation PD B package, per SEMI G42-88 Specification, TA= 25°C 3.1 W Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) Storage Temperature LB package, per SEMI G42-88 Specification, TA= 25°C Range S 1.6 W –20 to 85 ºC 150 ºC –55 to 150 ºC Value Units 40 ºC/W 77 ºC/W 6 ºC/W Fault conditions that produce excessive junction temperature will activate the device’s thermal shutdown circuitry. These conditions can be tolerated but should be avoided. Tstg Thermal Characteristics Characteristic Symbol Package Thermal Resistance, Junction to Ambient RθJA Package Thermal Resistance, Junction to Tab RθJT Test Conditions* B Package, single-layer PCB, 1 in.2 2-oz. exposed copper LB Package, single-layer PCB, minimal exposed copper area ALLOWABLE PACKAGE POWER DISSIPATION (W) *Additional thermal information available on Allegro website. 4 RQJT = 6.0oC/W 3 SUFFIX 'B', R QJA = 40oC/W 2 1 SUFFIX 'LB', R QJA = 77oC/W 0 25 50 75 100 TEMPERATURE IN o C 125 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Copyright © 2000, 2002 Allegro MicroSystems, Inc. 2 A3958 DMOS Full-Bridge PWM Motor Driver ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Load Supply Current VBB IDSS rDS(on) VF IBB Operating 20 – 50 V During sleep mode 0 – 50 V VOUT = VBB – <1.0 20 μA VOUT = 0 V – <-1.0 -20 μA Source driver, IOUT = -2 A – 270 300 mΩ Sink driver, IOUT = 2 A – 270 300 mΩ Source diode, IF = -2 A – 1.2 1.6 V Sink diode, IF = 2 A – 1.2 1.6 V fPWM < 50 kHz – 4.0 7.0 mA Charge pump on, outputs disabled – 2.0 5.0 mA Sleep Mode – – 20 μA 4.5 5.0 5.5 V Control Logic Logic Supply Voltage Range VDD Logic Input Voltage VIN(1) 2.0 – – V VIN(0) – – 0.8 V Operating Logic Input Current IIN(1) VIN = 2.0 V – <1.0 20 μA (all inputs except ENABLE) IIN(0) VIN = 0.8 V – <-2.0 -20 μA ENABLE Input Current IIN(1) VIN = 2.0 V – 40 100 μA IIN(0) VIN = 0.8 V – 16 40 μA OSC input frequency fOSC Operating 2.9 – 6.1 MHz OSC input duty cycle dcOSC Operating 40 – 60 % OSC input hysteresis – Operating 200 – 400 mV Input Hysteresis – All digital inputs except OSC 50 – 100 mV 0.0 – 2.6 V Reference Input Volt. Range VREF Operating Reference Input Current IREF VREF = 2.5 V – – ±0.5 μA Comparator Input Offset Volt. VIO VREF = 0 V – 0 ±5.0 mV Continued next page … Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3958 DMOS Full-Bridge PWM Motor Driver ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic Buffer Input Offset Volt. VIO Reference Divider Ratio – Propagation Delay Times Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current – 0 ±15 mV D14 = High 9.9 10 10.2 – D14 = Low 4.95 5.0 5.05 – PWM change to source ON – 600 – ns PWM change to source OFF – 100 – ns PWM change to sink ON – 600 – ns PWM change to sink OFF – 100 – ns Phase change to sink ON – 600 – ns Phase change to sink OFF – 100 – ns Phase change to source ON – 600 – ns Phase change to source OFF – 100 – ns TJ – 165 – °C ∆TJ – 15 – °C 3.90 4.2 4.45 V 0.05 0.10 – V fPWM < 50 kHz – 6.0 10 mA Sleep Mode, Inputs < 0.5 V – – 2.0 mA tpd UVLO Increasing VDD ∆UVLO IDD NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3958 DMOS Full-Bridge PWM Motor Driver FUNCTIONAL DESCRIPTION Serial Interface. The A3958 is controlled via a 3-wire (clock, data, strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is clocked in starting with D19. Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Function Blank Time LSB Blank Time MSB Off Time LSB Off Time Bit 1 Off Time Bit 2 Off Time Bit 3 Off Time MSB Fast Decay Time LSB Fast Decay Time Bit 1 Fast Decay Time Bit 2 Fast Decay Time MSB Sync. Rect. Mode Sync. Rect. Enable External PWM Mode Enable Phase Reference Range Select Internal PWM Mode Test Use Only Sleep Mode D0 – D1 Blank Time. The current-sense comparator is blanked when any output driver is switched on, according to the table below. fosc is the oscillator input frequency. D1 0 0 1 1 D0 0 1 0 1 Blank Time 4/fosc 6/fosc 12/fosc 24/fosc D2 – D6 Fixed-Off Time. A five-bit word sets the fixedoff time for internal PWM current control. The off time is defined by toff = (8[1 + N]/fosc) - 1/fosc where N = 0 … 31 For example, with an oscillator frequency of 4 MHz, the off time will be adjustable from 1.75 μs to 63.75 μs in increments of 2 μs. D7 – D10 Fast Decay Time. A four-bit word sets the fast-decay portion of the fixed-off time for the internal PWM control circuitry. This will only have impact if the mixed-decay mode is selected (via bit D17 and the MODE input terminal). For tfd > toff, the device will effectively operate in the fast-decay mode. The fast decay portion is defined by tfd = (8[1 + N]/fosc) - 1/fosc where N = 0 … 15 For example, with an oscillator frequency of 4 MHz, the fast decay time will be adjustable from 1.75 μs to 31.75 μs in increments of 2 μs. D11 Synchronous Rectification Mode. The active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. The passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by VREF/RS. D11 0 1 Mode Active Passive D12 Synchronous Rectification Enable. D12 0 1 Synchronous Rect. Disabled Enabled D13 External PWM Decay Mode. Bit D13 determines the current-decay mode when using ENABLE chopping for external PWM current control. D13 0 1 Mode Fast Slow D14 Enable Logic. Bit D14, in conjunction with ENABLE, determines if the output drivers are in the chopped (OFF)(ENABLE = D14) or ON (ENABLE ≠ D14) state. ENABLE 0 1 0 1 D14 0 0 1 1 Mode Chopped On On Chopped Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3958 DMOS Full-Bridge PWM Motor Driver FUNCTIONAL DESCRIPTION (continued) D15 Phase Logic. Bit D15, in conjunction with PHASE, determines if the device is operating in the forward (PHASE ≠ D15) or reverse (PHASE = D15) state. PHASE D15 State 0 0 Reverse 1 0 Forward 0 1 Forward 1 1 Reverse D19 Sleep Mode. Bit D19 selects a Sleep mode to minimize power consumption when not in use. This disables much of the internal circuitry including the regulator and charge pump. On power up the serial port is initialized to all 0s. Bit D19 should be programmed high for 1 ms before attempting to enable any output driver. OUTA OUTB Low High High Low High Low Low High D16 Gm Range Select. Bit D16, in conjunction with RANGE, determines if VREF is divided by 5 (RANGE ≠ D16) or by 10 (RANGE = D16). RANGE 0 1 0 1 D16 0 0 1 1 D19 0 1 Divider ÷10 ÷5 ÷5 ÷10 D17 Internal PWM Mode. Bit D17, in conjunction with MODE, selects slow (MODE ≠ D17) or mixed (MODE = D17) current decay. MODE D17 0 0 1 0 0 1 1 1 D18 Test Mode. Bit D18 low (default) operates the device in normal mode. D18 is only used for testing purposes. The user should never change this bit. Current-Decay Mode Mixed Slow Slow Mixed Sleep Mode Sleep Normal Serial Port Write Timing Operation. Data is clocked into the shift register on the rising edge of the CLOCK signal. Normally STROBE will be held high, only brought low to initiate a write cycle. Refer to diagram below and these specifications for the minimum timing requirements. A. DATA setup time ........................................... 15 ns B. DATA hold time ............................................ 10 ns C. Setup STROBE to CLOCK rising edge ........ 50 ns D. CLOCK high pulse width ............................. 50 ns E. CLOCK low pulse width ............................... 50 ns F. Setup CLOCK rising edge to STROBE ........ 50 ns G. STROBE pulse width ................................... 50 ns VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 μF capacitor to ground. VREG is Serial Port Write Timing STROBE C D E F G CLOCK A DATA B D19 D18 D0 Dwg. WP-038 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3958 DMOS Full-Bridge PWM Motor Driver FUNCTIONAL DESCRIPTION (continued) internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 μF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 μF ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on CP or VREG) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers and resets the data in the serial port to all zeros. PWM Timer Function. The PWM timer is programmable via the serial port (bits D2 – D10) to provide off-time PWM signals to the control circuitry. In the mixed current-decay mode, the first portion of the off time operates in fast decay, until the fast decay time count (serial bits D7 – D10) is reached, followed by slow decay for the rest of the off-time period (bits D2 – D6). If the fast decay time is set longer than the off time, the device effectively operates in fast decay mode. Bit D17, in conjunction with MODE, selects mixed or slow decay. PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter (see bits D2 – D6) to provide the programmable blanking function. The blank timer is reset when ENABLE is chopped or PHASE is changed. For external PWM control, a PHASE change or ENABLE on will trigger the blanking function. Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3958 synchronous rectification feature will turn on the opposite pair of DMOS outputs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits D11 and D12). The active or passive mode selection has no impact in slowdecay mode. With synchronous rectification enabled, the slow-decay mode serves as an effective brake mode. Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the RANGE logic level, and serial data bit D16: When RANGE = D16 ....................... ITRIP = VREF/10RS When RANGE ≠ D16 ......................... ITRIP = VREF/5RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the serial-port-programmed fixed off-time period. The current path during recirculation is determined by the configuration of slow/mixed current-decay mode (D17) and the synchronous rectification control bits (D11 and D12). Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3958 DMOS Full-Bridge PWM Motor Driver APPLICATIONS INFORMATION Current Sensing. To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors the IR drops in the PCB sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. The maximum value of RS is given as RS ≤ 0.5/ITRIP. Braking. The braking function is implemented by driving the device in slow-decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping with the combination of D14 and the ENABLE input terminal. Because it is possible to drive current in either direction through the DMOS drivers, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance*, the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground terminals of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 μF capacitor be placed between SENSE and ground as close to the device as possible; the load supply terminal, VBB, should be decoupled with an electrolytic capacitor (> 47 μF is recommended) placed as close to the device as is possible. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3958 DMOS Full-Bridge PWM Motor Driver A3958SB 2 θ 24 CP 23 VREG 22 RANGE 21 OUTB 20 LOAD SUPPLY 19 GROUND PHASE 3 OSC 4 GROUND 5 GROUND 6 GROUND 7 18 GROUND GROUND 8 17 SENSE LOGIC SUPPLY 99 16 OUTA ENABLE 10 15 MODE DATA 11 14 REF CLOCK 12 13 STROBE LOGIC VBB V DD ÷ SERIAL PORT CP 1 CP2 2 CP1 3 PHASE 4 OSC 5 GROUND 6 GROUND 7 LOGIC SUPPLY 8 ENABLE 99 Dwg. PP-069-1A DATA 10 CLOCK 11 STROBE CHARGE PUMP CP1 CHARGE PUMP NC Q VBB LOGIC 1 V DD SERIAL PORT CP2 A3958SLB 12 NC ÷ 24 VREG 23 RANGE 22 NO CONNECTION 21 OUTB 20 LOAD SUPPLY 19 GROUND 18 GROUND 17 SENSE 16 OUTA 15 NO CONNECTION 14 MODE 13 REF Dwg. PP-069A Terminal List Terminal Name Terminal Description A3958SB (DIP) A3958SLB (SOIC) CP Reservoir capacitor (typically 0.22 μF) 24 1 CP1 & CP2 The charge pump capacitor (typically 0.22 μF) 1&2 2&3 PHASE Logic input for direction control (see also D15) 3 4 OSC Logic-level oscillator (square wave) input 4 5 GROUND Grounds 5, 6, 7, 8* 6, 7 LOGIC SUPPLY VDD, the low voltage (typically 5 V) supply 9 8 ENABLE Logic input for enable control (see also D14) 10 9 DATA Logic-level input for serial interface 11 10 CLOCK Logic input for serial port (data is entered on rising edge) 12 11 STROBE Logic input for serial port (active on rising edge) 13 12 REF VREF, the load current reference input volt. (see also D16) 14 13 MODE Logic input for PWM mode control (see also D17) 15 14 NO CONNECT No (Internal) Connection — 15 OUTA One of two DMOS bridge outputs to the motor 16 16 SENSE Sense resistor 17 17 GROUND Grounds 18, 19* 18, 19 LOAD SUPPLY VBB, the high-current, 20 V to 50 V, motor supply 20 20 OUTB One of two DMOS bridge outputs to the motor 21 21 NO CONNECT No (Internal) connection — 22 RANGE Logic Input for VREF range control (see also D16) 22 23 VREG Regulator decoupling capacitor (typically 0.22 μF) 23 24 * For the A3958SB DIP only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3958 DMOS Full-Bridge PWM Motor Driver B package 24-pin DIP +0.25 30.10 –0.64 24 +0.10 0.38 –0.05 +0.76 6.35 –0.25 +0.38 10.92 –0.25 5.33 MAX For Reference Only (reference JEDEC MS-001 BE) Dimensions in millimeters 7.62 A 1 2 +0.51 3.30 –0.38 1.27 MIN 2.54 +0.25 1.52 –0.38 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.018 0.46 ±0.12 LB package 24-pin SOICW 15.40±0.20 4° ±4 24 +0.07 0.27 –0.06 10.30±0.33 7.50±0.10 A 9.60 +0.44 0.84 –0.43 2.20 1 2 0.25 24X SEATING PLANE 0.10 C 0.41 ±0.10 1.27 C SEATING PLANE GAUGE PLANE 1.27 0.65 B PCB Layout Reference View 2.65 MAX 0.20 ±0.10 For reference only Pins 6 and 7, and 18 and 19 internally fused Dimensions in millimeters (Reference JEDEC MS-013 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-24M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©2000-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10