Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer ICS85304-01 DATA SHEET General Description Features The ICS85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer. The ICS85304-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. • • • Five 3.3V differential LVPECL output pairs • • Maximum output frequency: 650MHz • • • • • Output skew: 35ps (maximum) Guaranteed output and part-to-part skew characteristics make the ICS85304-01 ideal for those applications demanding well defined performance and repeatability. Q LE 00 CLK1 Pulldown nCLK1 Pullup 11 Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs Part-to-part skew: 150ps (maximum) Propagation delay: 2.1ns (maximum) Full 3.3V supply mode 0°C to 70°C ambient operating temperature Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 D CLK0 Pulldown nCLK0 Pullup CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels Pin Assignment Block Diagram CLK_EN Pullup Selectable differential CLKx, nCLKx input pairs CLK_SEL Pulldown Q0 nQ0 Q1 nQ1 nQ3 Q4 nQ4 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 VCC CLK_EN VCC nCLK1 CLK1 VEE nCLK0 CLK0 CLK_SEL VCC ICS85304-01 Q3 nQ3 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Q4 nQ4 ICS843N001BGI REVISION E DECEMBER 19, 2012 1 2 3 4 5 6 7 8 9 10 1 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 18, 20 VCC Power Power supply pins. 12 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup 15 VEE Power 16 CLK1 Input Pulldown 17 nCLK1 Input Pullup Inverting differential clock input. 19 CLK_EN Input Pullup Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels. Inverting differential clock input. Negative supply pin. Non-inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k ICS843N001BGI REVISION E DECEMBER 19, 2012 Test Conditions 2 Minimum Typical Maximum Units ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q4 nQ0:nQ4 0 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH 0 1 CLK1, nCLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0, nCLK0 Enabled Enabled 1 1 CLK1, nCLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B. Enabled Disabled nCLK[0:1] CLK[0:1] CLK_EN nQ[0:4] Q[0:4] Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK0 or CLK1 nCLK0 or nCLK1 Q[0:4] nQ[0:4] Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. ICS843N001BGI REVISION E DECEMBER 19, 2012 3 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 55 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 3.765 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current CLK_EN VCC = VIN = 3.465V 5 µA CLK_SEL VCC = VIN = 3.465V 150 µA CLK_EN VCC = 3.465V, VIN = 0V -150 µA CLK_SEL VCC = 3.465V, VIN = 0V -5 µA Table 4C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units nCLK0, nCLK1 VCC = VIN = 3.465V 5 µA CLK0, CLK1 VCC = VIN = 3.465V 150 µA nCLK0, nCLK1 VCC = 3.465V, VIN = 0V -150 µA CLK0, CLK1 VCC = 3.465V, VIN = 0V -5 µA 0.15 1.3 V VEE + 0.5 VCC – 0.85 V NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. ICS843N001BGI REVISION E DECEMBER 19, 2012 4 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.4 VCC – 1.0 µA VCC – 2.0 VCC – 1.7 µA 0.6 0.85 V NOTE 1: Outputs terminated with 50 to VCC – 2V. AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE =0V, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) tsk(pp) tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Maximum Units 650 MHz 2.1 ns Output Skew; NOTE 2, 3 35 ps Part-to-Part Skew; NOTE 3, 4 150 ps 700 ps 52 % ƒ 650MHz 20% to 80% @ 50MHz Minimum Typical 1.0 300 48 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 500MHz unless noted otherwise NOTE: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured at the output differential cross points. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. ICS843N001BGI REVISION E DECEMBER 19, 2012 5 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Parameter Measurement Information 2V VCC VCC Qx SCOPE nCLK0, nCLK1 V Cross Points PP V CMR CLK0, CLK1 nQx VEE VEE -1.3V ± 0.165V 3.3V Output Load Test Circuit Differential Input Level nQx Par t 1 nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Output Skew Part-to-Part Skew nCLK0, nCLK1 nQ[0:4] CLK0, CLK1 Q[0:4] t PW t nQ[0:4] Q[0:4] odc = tPD PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Duty Cycle/Pulse Width/Period nQ[0:4] 80% 80% VSW I N G Q[0:4] 20% 20% tR tF Output Rise/Fall Time ICS843N001BGI REVISION E DECEMBER 19, 2012 6 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS843N001BGI REVISION E DECEMBER 19, 2012 7 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT’s open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for theCLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver Differential Input LVPECL R2 50Ω R1 50Ω R2 50Ω R2 50Ω Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V R4 125Ω 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK Differential Input LVPECL R1 84Ω R2 84Ω Receiver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V nCLK Zo = 50Ω LVDS 2.5V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS843N001BGI REVISION E DECEMBER 19, 2012 8 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullup or pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V R3 125Ω 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 Input Zo = 50Ω R2 84Ω RTT Figure 3A. 3.3V LVPECL Output Termination ICS843N001BGI REVISION E DECEMBER 19, 2012 Figure 3B. 3.3V LVPECL Output Termination 9 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS85304-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85304-01 is the sum of the core power plus the output power dissipated due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.57mW • Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.342W * 73.2°C/W = 95°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS843N001BGI REVISION E DECEMBER 19, 2012 10 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate output power dissipated due to loading, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 1.0V (VCC_MAX – VOH_MAX) = 1.0V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 1.0V)/50] * 1.0V = 20mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW ICS843N001BGI REVISION E DECEMBER 19, 2012 11 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS85304-01 is: 489 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS843N001BGI REVISION E DECEMBER 19, 2012 12 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 85304AG-01LF 85304AG-01LFT Marking ICS85304A01L ICS85304A01L ICS843N001BGI REVISION E DECEMBER 19, 2012 Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP 13 Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER Revision History Sheet Rev Table Page T4B T4D T5 4 5 5 VCMR values changed from 1.5V min. to 0.5V min.; VDD max. to VCC - 0.85V max. VOH values changed from 1.9µA min. to VCC - 1.4µA min.; 2.3µA max. to VCC - 1.0µA. VOL values changed from 1.2µA min. to VCC - 2.0µA; 1.6µA max. to VCC - 1.7µA max. Replaced tpLH and tpHL with tPD at the same values. Replaced tPW and values of tCYCLE/2 - 40 min., tCYCLE/2 typ., tCYCLE/2 + 40 max. with odc at values of 48% min., 50% typ., 52% max. 5/14/01 T4D T5 5 B LVPECL DC Characteristics Table - added IIH, IIL, VPP, and VCMR rows. AC Characteristics Table - tR and tF values changed from 275ps min to 300ps min; 650ps max. to 700ps max. 5/22/01 C T4D 5 Differential DC Characteristics Table - VCMR values changed from VCC - 0.85V max. to VCC. 8/21/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 10/17/01 C 3 Revised Figure 1, CLK_EN Timing Diagram. 11/2/01 3 Revised Inputs heading from CLK or CLK, nPCLK or nPCLK to CLK or PCLK, nCLK or nPCLK. 12/28/01 8 Added Termination for LVEPCL Output section. 5/30/02 6 8/26/02 7 3.3V Output Load Test Circuit Diagram - corrected VEE = -1.3V ± 0.135V to VEE = -1.3V ± 0.165V. Updated Output Rise/Fall Time Diagram. 1 2 4 6 8 9 14 Added Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Updated Parameter Measurement Information. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Ordering Information table - added Lead Free part number. 6/17/04 Per Document Errata, NEN-08-03, corrected name of PCLK/nPCLK to CLK1/nCLK1 and changed CLK/nCLK to CLK0/nCLK0 throughout the datasheet. Updated Differential Clock Input Interface section. Deleted LVPECL Clock Input Interface section. Added Recommendations for Unused Input and Output Pins section. Power Considerations - corrected Junction Temperature calculations. Ordering Information Table - corrected marking. Updated format throughout the datasheet. 6/20/08 Corrected Figure 1, CLK_EN Timing Diagram. 7/8/08 A C T3B C C T2 D T9 8 E T9 E E 9 10 13 3 T4[A:D] 1 4-5 T5 5 T9 7 13 Description of Change Date Features section - deleted package information DC Characteristic Tables - corrected table heading temperature from -40C to 85C to 0C to 70C. AC Characteristic Table - corrected table heading temperature from -40C to 85C to 0C to 70C. Added general note to table. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Ordering Information Table - deleted non lead-free parts. Deleted Tape & Reel quantity from Shipping Packaging column. ICS843N001BGI REVISION E DECEMBER 19, 2012 14 12/19/12 ©2012 Integrated Device Technology, Inc. ICS85304-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LEVPECL FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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