54AC377,54ACT377 54AC377 54ACT377 Octal D Flip-Flop with Clock Enable Literature Number: SNOS106 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features n ICC reduced by 50% n Ideal for addressable register applications n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n Outputs source/sink 24 mA n See ’273 for master reset version n See ’373 for transparent latch version n See ’374 for TRI-STATE ® version n ’ACT377 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) — ’AC377: 5962-88702 — ’ACT377: 5962-87697 Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names Description D0–D7 Data Inputs CE Clock Enable (Active LOW) Q0–Q7 Data Outputs CP Clock Pulse Input TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100290 www.national.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable February 1999 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100290-4 DS100290-3 Mode Select-Function Table Operating Mode Inputs Outputs CP CE Dn Qn Load ‘1’ N L H H Load ‘0’ N L L Hold (Do Nothing) N H X No Change X H X No Change L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Logic Diagram DS100290-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C Note 2: See individual datasheets for those devices which differ from the typical input rise and fall times noted here. DC Characteristics for ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = 12 mA V µA IOL = 24 mA IOL = 24 mA VI = VCC, GND Leakage Current 3 www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter (Continued) VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions 50 mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Guaranteed Limits IOLD (Note 4) 5.5 Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current or GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 6) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 6) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD (Note 7) Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current or GND Note 6: *All outputs loaded; thresholds on input associated with output under test. Note 7: †Maximum test duration 2.0 ms, one output loaded at a time. Note 8: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Min fmax tPLH tPHL Fig. Units No. Max Maximum Clock 3.3 75 Frequency 5.0 95 MHz Propagation Delay 3.3 1.0 14.0 CP to Qn 5.0 1.5 10.0 Propagation Delay 3.3 1.0 15.0 CP to Qn 5.0 1.5 11.0 ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Fig. Units No. Guaranteed Minimum ts th ts th tw Setup Time, HIGH or LOW 3.3 7.5 Dn to CP 5.0 6.0 Hold Time, HIGH or LOW 3.3 1.5 Dn to CP 5.0 2.5 Setup Time, HIGH or LOW 3.3 9.5 CE to CP 5.0 6.0 Hold Time, HIGH or LOW 3.3 1.0 CE to CP 5.0 2.0 CP Pulse Width 3.3 6.5 HIGH or LOW 5.0 5.0 ns ns ns ns ns Note 10: Voltage Range 3.3 is 3.0V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Min fmax Maximum Clock Fig. Units No. Max 5.0 85 MHz 5.0 1.5 11.0 ns 5.0 1.5 12.0 ns Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn Note 11: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 12) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 7.0 ns 5.0 1.0 ns 5.0 7.0 ns 5.0 1.0 ns 5.0 5.5 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP ts Setup Time, HIGH or LOW CE to CP th Hold Time, HIGH or LOW CE to CP tw CP Pulse Width HIGH or LOW Note 12: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 90.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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