CSD75207W15 www.ti.com SLPS418 – JUNE 2013 Dual P-Channel NexFET™ Power MOSFET Check for Samples: CSD75207W15 FEATURES 1 • • • • • • • Dual P-Ch MOSFETs Common Source Configuration Small Footprint 1.5-mm × 1.5-mm Gate-Source Voltage Clamp Gate ESD Protection >4kV – HBM JEDEC standard JESD22-A114 Pb and Halogen Free RoHS Compliant PRODUCT SUMMARY VD1D2 Drain to Drain Voltage –20 V Qg Gate Charge Total (-4.5V) 2.9 nC Qgd Gate Charge Gate to Drain RD1D2(on) Drain to Drain On Resistance VGS(th) Battery Management Battery Protection Load and Input Switching nC 119 mΩ VGS = –2.5V 64 mΩ VGS = –4.5V 45 mΩ Threshold Voltage –0.8 V ORDERING INFORMATION Device Package Media Qty Ship CSD75207W15 1.5-mm × 1.5-mm Wafer Level Package 7-Inch Reel 3000 Tape and Reel APPLICATIONS • • • 0.4 VGS = –1.8V ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated DESCRIPTION The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182. VALUE UNIT VD1D2 Drain to Drain Voltage –20 V VGS Gate to Source Voltage -6.0 V Continuous Drain to Drain Current, TC = 25°C(1) –2.4 A Pulsed Drain to Drain Current, TC = 25°C(2) -24 A Continuous Source Pin Current -1.2 A Pulsed Source Pin Current(2) -15 A Continuous Gate Clamp Current -0.5 A ID1D2 IS IG Pulsed Gate Clamp Current(2) -7 A Text added for space PD Power Dissipation(1) 0.7 W Text added for space TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C Text added for space (1) Per device, both sides in conduction (2) Pulse duration 10μs, duty cycle ≤2% Top View RD1D2(on) vs VGS G1 SS G2 D1 D2 D2 RD1D2(on) - On-State Resistance (mΩ) 140 D1 D1 D2 120 110 100 90 80 70 60 50 40 30 P0109-01 TC = 25°C Id = −1A TC = 125ºC Id = −1A 130 0 1 2 3 4 5 − VGS - Gate-to- Source Voltage (V) 6 G001 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD75207W15 SLPS418 – JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated). Specifications and graphs are Per MOSFET unless otherwise stated. Drain to Drain measurements are done with both MOSFETs in series (common source configuration. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVD1D2 Drain to Drain Voltage VGS = 0V, ID1D2 = –250μA –20 BVGSS Gate to Source Voltage VD1D2 = 0V, IG = -250μA -6.0 IDDS Drain to Drain Leakage Current VGS = 0V, VD1D2 = –16V IGSS Gate to Source Leakage Current VD1D2 = 0V, VGS = -6V VGS(th) Gate to Source Threshold Voltage VD1D2 = VGS, IDS = –250μA RD1D2(on) Drain to Drain On Resistance gfs Transconductance -0.6 V V –1 μA -100 nA –0.8 -1.1 V VGS = –1.8V, ID1D2 = –1A 119 162 mΩ VGS = –2.5V, ID1D2 = –1A 64 77 mΩ VGS = –4.5V, ID1D2 = –1A 45 54 mΩ VD1D2 = –10V, ID1D2 = –1A 6.2 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Rg Series Gate Resistance 27 Qg Gate Charge Total (–4.5V) 2.9 Qgd Gate Charge - Gate to Drain 0.4 nC Qgs Gate Charge - Gate to Source 0.7 nC Qg(th) Gate Charge at Vth 0.4 nC QOSS Output Charge 3.1 nC td(on) Turn On Delay Time 12.8 ns tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VD1D2 = –10V, f = 1MHz VD1D2 = –10V, ID1D2 = –1A VD1D2 = –9.5V, VGS = 0V VD1D2 = –10V, VGS = –4.5V, ID1D2 = –1A, RG = 30Ω 458 595 pF 225 293 pF 10.4 13.5 pF Ω 3.7 nC 8.6 ns 32.1 ns 16.0 ns Diode Characteristics VSD Diode Forward Voltage ID1D2 = –1A, VGS = 0V -0.8 Qrr Reverse Recovery Charge Vdd = –10V, IF = –1A, di/dt = 200A/μs 10.5 -1 nC V trr Reverse Recovery Time Vdd = –10V, IF = –1A, di/dt = 200A/μs 23 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER R θJA (1) (2) (3) 2 Thermal Resistance Junction to Ambient (1) Thermal Resistance Junction to Ambient (2) (3) (2) Typical Value UNIT 70 °C/W 165 °C/W Device mounted on FR4 material with Minimum Cu mounting area. Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1-inch2 of Cu (2oz). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418 – JUNE 2013 Typ RθJA = 165°C/W when mounted on minimum pad area of 2 oz. Cu. Typ RθJA = 70°C/W when mounted on 1inch2 of 2 oz. Cu. G1 S G2 D2 D1 G1 S G2 D2 D1 M0169-01 M0170-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 3 CSD75207W15 SLPS418 – JUNE 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 15 − ID1D2 - Drain 1 to Drain 2 Current (A) − ID1D2 - Drain 1 to Drain 2 Current (A) 10 VGS = −4.5V VGS = −2.5V VGS = −1.8V 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 − VD1D2 - Drain 1 to Drain 2 Voltage (V) VD1D2 = −5V 12 9 6 0 1.4 TC = 125°C TC = 25°C TC = −55°C 3 0 0.5 G001 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd f = 1MHz VGS = 0V 600 4 C − Capacitance (nF) − VGS - Gate-to-Source Voltage (V) G001 700 ID = −1A VD1D2 =−10V 3 2 500 400 300 200 1 100 0 0 0.5 1 1.5 2 2.5 Qg - Gate Charge (nC) 3 0 3.5 0 1 2 3 4 5 6 − VD1D2 - Drain 1 to Drain 2 Voltage (V) G001 Figure 4. Gate Charge 7 8 G001 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 140 RD1D2(on) - On-State Resistance (mΩ) 1.1 ID = −250uA − VGS(th) - Threshold Voltage (V) 3 Figure 3. Transfer Characteristics 5 1 0.9 0.8 0.7 0.6 0.5 0.4 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs. Temperature 4 1 1.5 2 2.5 − VGS - Gate-to-Source Voltage (V) 175 TC = 25°C Id = −1A TC = 125ºC Id = −1A 130 120 110 100 90 80 70 60 50 40 30 0 G001 1 2 3 4 5 − VGS - Gate-to- Source Voltage (V) 6 G001 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418 – JUNE 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.4 10 VGS = −2.5V VGS = −4.5V ID = −1A − ISD − Source-to-Drain Current (A) Normalized On-State Resistance 1.5 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 100ms 1s DC − IAV - Peak Avalanche Current (A) − ID1D2 - Drain 1 to Drain 2 Current (A) G001 Figure 9. Typical Diode Forward Voltage 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =165ºC/W(min Cu) 0.01 0.1 1 1 10 − VD1D2 - Drain 1 to Drain 2 Voltage (V) 10 TC = 25ºC TC = 125ºC 1 0.01 100 0.1 TAV - Time in Avalanche (ms) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING − ID1D2 - Drain 1 to Drain 2 Current (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Typical RthetaJA =70ºC/W(max Cu) 0.0 −50 −25 0 25 50 75 100 125 TA - Ambient Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 5 CSD75207W15 SLPS418 – JUNE 2013 www.ti.com MECHANICAL DATA CSD75207W15 Package Dimensions Solder Ball Ø 0.31 ±0.075 Pin 1 Mark 1 2 3 2 3 1 A B 1.50 B 1.00 +0.00 –0.08 0.50 A C C 1.50 +0.00 –0.08 0.62 Max Top View 0.50 Bottom View 0.04 0.62 Max 0.35 ±0.10 Side View Seating Plate Front View M0171-01 NOTE: All dimensions are in mm (unless otherwise specified) Pinout POSITION 6 DESIGNATION A1 Gate1 A2, A3, B3 Drain1 C1 Gate2 C2, C3, B2 Drain2 B1 Source Sense Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418 – JUNE 2013 Figure 13. Land Pattern Recommendation Ø 0.25 1 2 3 1.00 0.50 A B C 0.50 M0172-01 NOTE: All dimensions are in mm (unless otherwise specified) Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 0.50 ±0.05 0.86 ±0.05 1.60 ±0.05 5° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 1.60 ±0.05 5° Max M0173-01 NOTE: All dimensions are in mm (unless otherwise specified) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD75207W15 7 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD75207W15 ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YZF 9 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) SNAGCU Level-1-260C-UNLIM (4/5) -55 to 150 75207 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD75207W15 Package Package Pins Type Drawing SPQ DSBGA 3000 YZF 9 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 1.65 B0 (mm) K0 (mm) P1 (mm) 1.65 0.81 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD75207W15 DSBGA YZF 9 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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