IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT TRANSPARENT LATCH IDT74FCT163373A/C FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • Rail-to-rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components • Available in SSOP and TSSOP packages The FCT163373 16-bit transparent D-type latches are built using advanced dual metal CMOS technology. These high-speed, low-power latches are ideal for temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The inputs of FCT163373 can be driven from either 3.3V or 5V devices. This feature allows the use of these transparent latches as translators in a mixed 3.3V/5V supply system. With xLE inputs high, the FCT163373 can be used as a buffer to connect 5V components to a 3.3V bus. FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 25 48 2LE 1LE 1D 1 47 36 D 2D1 2 D 13 1O1 2O1 C C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 2008 1 © 2002 Integrated Device Technology, Inc. DSC-5416/5 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 1OE 1 48 1LE 1O1 2 47 1 D1 1O2 3 46 1 D2 GND 4 45 GND 1O3 5 44 1 D3 1O4 6 43 1 D4 VCC 7 42 VCC 1O5 8 41 1 D5 1O6 9 40 1 D6 GND 10 39 GND 1O7 11 38 1 D7 1O8 12 37 1 D8 2O1 13 36 2 D1 2O2 14 35 2 D2 GND 15 34 GND 2O3 16 33 2 D3 2O4 17 32 2 D4 VCC 18 31 VCC 2O5 19 30 2 D5 2O6 20 29 2 D6 GND 21 28 GND 2O7 22 27 2 D7 2O8 23 26 2 D8 24 25 2LE 2OE Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to 7 V VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names xDx xLE xOE xOx Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs FUNCTION TABLE(1) xDx H L X X SSOP/ TSSOP TOP VIEW Inputs xLE H H L X xOE L L L H Outputs xBx H L O(2) Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Test Conditions(1) Min. Typ.(2) Max. Unit 2 — 5.5 V 2 — VCC+0.5 –0.5 — 0.8 VI = 5.5V — — ±1 Input HIGH Current (I/O pins) VI = VCC — — ±1 Input LOW Current (Input pins) VI = GND — — ±1 Input LOW Current (I/O pins) VI = GND — — ±1 VO = VCC — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA mA Parameter Input HIGH Level (Input pins) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level IIH Input HIGH Current (Input pins) IIL IOZH High Impedance Output Current IOZL (3-State Output pins) VIK Clamp Diode Voltage IODH Output HIGH Current VCC = Max. VCC = Max. VCC = Min., IIN = –18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) (3) IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VIN = VIH or VIL IOH = –3mA VCC = 3V 50 90 200 VCC-0.2 — — 2.4 3 — 3 — (5) IOH = –8mA 2.4 V µA µA V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 VIN = VIH or VIL IOL = 16mA — 0.2 0.4 IOL = 24mA — 0.3 0.55 VCC = 3V IOL = 24mA — 0.3 0.5 –60 –135 –240 mA — 150 — mV — 0.1 10 µA V VIN = VIH or VIL (4) IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VO = GND(3) — VCC = Max. VIN = GND or VCC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC–0.6V at rated current. 3 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions(1) ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC –0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open xOE = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) Min. Typ.(2) Max. Unit — 2 30 µA VIN = VCC VIN = GND — 50 75 µA/ MHz VCC = Max., Outputs Open fi = 10MHz 50% Duty Cycle xOE = GND xLE = VCC One Bit Toggling VIN = VCC VIN = GND — 0.5 0.8 mA VIN = VCC –0.6V VIN = GND — 0.5 0.8 VCC = Max., Outputs Open fi = 2.5MHz 50% Duty Cycle xOE = GND xLE = VCC Sixteen Bits Toggling VIN = VCC VIN = GND — 2 3(5) VIN = VCC –0.6V VIN = GND — 2 3.3(5) NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ΔICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xOx Propagation Delay xLE to xOx Output Enable Time FCT163373A Min.(3) Max. 1.5 5.2 Condition(2) CL = 50pF RL = 500Ω FCT163373C Min.(3) Max. 1.5 4.2 Unit ns 2 8.5 2 5.5 ns 1.5 6.5 1.5 5.5 ns Output Disable Time 1.5 5.5 1.5 5 ns Set-up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(4) 2 1.5 5 — — — — 0.5 2 1.5 5 — — — — 0.5 ns ns ns ns NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 5 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION 6v Open V CC 500Ω GND V OUT VIN Pulse Generator D.U.T. 50pF RT 500Ω CL Test Switch Open Drain Disable Low Enable Low 6V Disable High Enable High GND All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Propagation Delay SWITCH 6V tPZH SWITCH GND 0V tPLZ tPZL VOH 1.5V VOL 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 6 IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION FCT XX XXX XXXX Temp. Range Family Device Type X Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 PV PVG PA PAG Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green 373A 373C Non-Inverting 16-Bit Transparent Latch 163 Double-Density 3.3Volt 74 − 40°C to +85°C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: [email protected]