LM3101 Secondary-Side PWM Controller General Description Features The LM3101 is a precision high-speed PWM controller. It is designed to provide secondary-side feedback for offline Switch-Mode Power Supplies (SMPS) using pulse communication to the primary-side driver. The LM3101 is applicable in all of the popular converter topologies such as flyback or forward. The LM3101 combined with its companion LM3001 PrimarySide Driver forms a regulator chip-set that provides precision control of offline or other isolated DC/DC converters. The communication is realized between the two chips by a small pulse transformer, with one or two turns on its primary and secondary. This type of communication does not introduce any poles or zeroes in the control loop and yields the fastest possible loop response for the isolated switching regulator. The secondary-side controller contains a precision 1.242V reference, an error amplifier, and a trimmed oscillator which is programmed with a single resistor. The LM3101 can realize voltage, current or charge mode control. Power supply monitor features include power-on reset with programmable delay and overvoltage protection. Y Y Y Y Y Y Y Y Y g 2% precision voltage reference Wide-bandwidth (8 MHz) error amplifier External synchronization Frequency shift during an output short circuit Power-on reset flag with programmable delay Overvoltage crowbar trigger circuit Ramped reference Soft-Start Operation beyond 1 MHz Voltage, current, or charge mode control Typical Applications Y Y Y Y Isolated offline switching power supplies Isolated DC/DC power converters Flyback regulator Forward converter Block Diagram TL/H/11436 – 1 C1995 National Semiconductor Corporation TL/H/11436 RRD-B30M75/Printed in U. S. A. LM3101 Secondary-Side PWM Controller January 1995 Absolute Maximum Ratings (Note 1) Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Junction Temperature Range Supply Voltage 4.5V s VS s 15V b 40§ C s TJ s a 125§ C Supply Voltage (VS) 16V b 65§ C s TJ s a 150§ C Junction Temperature Range ESD 1 kV Lead Temperature (Soldering, 5 sec.) 260§ C Electrical Characteristics Specifications with standard typeface are for TJ e 25§ C, and those in bold typeface apply over full Operating Temperature Range. Pin 2, MC, is connected to VS by a 5 kX resistorÐthis selects voltage mode control operation. Unless otherwise specified, TA e 25§ C, VS e 5V, RFS e 25 kX (FO e 500 kHz). Symbol Parameter Conditions Min Typ Max Units 1.230 1.217 1.242 1.254 1.266 V 0.01 0.03 %/V REFERENCE SECTION (Note 2) VREF Reference Voltage DVREF/DVS Line Regulation 4.5V s VS s 15V DVREF/DT Temperature Stability (Note 3) b 40§ C s TJ s a 125§ C 0.003 %/§ C ERROR AMPLIFIER SECTION AVOL Open Loop Voltage Gain IB Input Bias Current GBW Gain-Bandwidth Product FTEST e 100 kHz iM Phase Margin AV e 1 SR Slew Rate 75 90 b 1.0 b 2.0 b 0.5 4.5 dB mA 8 MHz 52 Deg 2.5 6 V/ms RT e 25 kX 450 425 500 550 575 kHz RT e 12.5 kX 0.88 0.85 1.0 1.12 1.15 MHz RT e 25 kX (FO e 500 kHz), RSC e 13 kX (Note 5) 120 187 260 kHz RT e 12.5 kX (FO e 1 MHz), RSC e 6.34 kX (Note 5) 210 335 470 kHz OSCILLATOR SECTION FO FSC Oscillator Frequency (Note 4) Oscillator Frequency in Output Short Circuit DFO/DT Temperature Stability (Note 3) DFO/DVS Line Stability 4.5V s VS s 15V 0.1 VSYNC Synch Signal Amplitude AC Coupled, Negative Edge Trigger (Note 6) 1.5 2 DICOMP/Dt Compensation Current Ramp Slope RT e 25 kX RMC e 5 kX (Note 7) 155 2 %/§ C 0.9 %/V VPP 208 260 mA/ms Electrical Characteristics Specifications with standard typeface are for TJ e 25§ C, and those in bold typeface apply over full Operating Temperature Range. Pin 2, MC is connected to VS by a 5 kX resistorÐthis selects voltage mode control operation. Unless otherwise specified, TA e 25§ C, VS e 5V, RFS e 25 kX (FO e 500 kHz). (Continued) Symbol Parameter Conditions Min Typ FO e 500 kHz 88 84 92 FO e 1 MHz 84 80 90 Max Units PULSE WIDTH MODULATOR SECTION DMAX DMIN Maximum Duty Cycle Minimum Duty Cycle (Note 8) FO e 500 kHz FO e 1 MHz tdCS Current Sense Time Delay % % 2.5 6 8 % 4 10 12 % 75 100 ns OUTPUT SECTION tR Rise Time CL e 100 pF 20 ns tF Fall Time CL e 100 pF 30 ns VOL Output Voltage IL e 4 mA Sinking FO e 100 kHz 1.3 VOH Output Voltage IL e 4 mA Sourcing FO e 100 kHz 3.6 3.4 3.8 1.4 1.6 V V OVER-VOLTAGE CROWBAR TRIGGER SECTION %VTHC Relative Trigger Threshold Relative to Nominal Feedback Pin Voltage (Note 10) 18 16 20 22 24 ICD Crowbar Driver Output Current RCD e 10X 170 240 mA tCD Crowbar Delay RCD e 10X, VCD e 1V 400 ns tC Minimum Trigger Pulse Width (Note 11) 400 ns % POWER-ON RESET FLAG SECTION %VTHP Relative POR Trigger Threshold Relative to Nominal Feedback Pin Voltage (Note 10) VPOR POR Output Voltage VSM tDR b6 b 6.5 b 4.5 b3 b 2.5 % VFB e 1.11V IPOR e 1.6 mA 0.2 0.5 V Minimum Supply Voltage (Note 12) VPOR s 0.5V IPOR e 1.6 mA 1 1.2 V Power-On Reset Delay CRD e 2 nF 65 50 120 185 265 ms (Note 13) 3.65 3.92 4.20 UNDER-VOLTAGE LOCKOUT SECTION VUV Start-Up Threshold VUVH Threshold Hysteresis 300 V mV SUPPLY SECTION IS ISFST Supply Current Soft-Start Current (Note 14) VS e 5V 11 16 20 mA 4.5V s VS s 15V 15 24 28 mA 19.5 20.5 mA VSFST e 0V 14.5 3 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The reference voltage is measured at the error amplifier’s output with the error amplifier connected as a non-inverting amplifier with a gain of one. Note 3: The temperature coefficients of VREF or FO are defined as the worst-case DVREF or DFO measured at Specified Temperatures divided by the total span of the Specified Temperture Range (see graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum of maximum deviation. Note 4: The frequency of the internal oscillator is set by connecting a resistor, RT, from pin 1 to ground. See detailed description of this feature in the Pin-by-Pin Description section or the Functional Description of this datasheet. Note 5: A resistor, RSC, is connected from pin 5 to the regulator’s output. See detailed description of this feature in the Pin-by-Pin Description section or the Functional Description section of this datasheet. Note 6: For this test, the frequency of synchronization, FSYNC, is 600 kHz, CSYNC is 220 pF, and RSYNC is 1 kX. The internal oscillator will synchronize to an AC signal that is 1.1 to 1.5 times the free running oscillator frequency, FO. See Functional Description section or Pin-by-Pin Description section for more detail on synchronization. Note 7: ICOMP is sourced from pin 6 (CMI). See Functional Description section or Pin-by-Pin Description section for more detail on current mode operation. Note 8: Minimum duty cycle is the smallest duty cycle that can be produced by the LM3101 in a given oscillator period. The controller can operate with effectively zero duty cycleÐit skips cycles if the regulation cannot be maintained with the minimum duty cycle. This means that the output voltage of the switching converter is regulated down to no load. Note 9: The current sense time delay is the time span between an input applied to the CMI pin (pin 6) and the change of state of VOUT (pin 8) due to the input. Note 10: Both these specifications, %VTHC and %VTHP, are relative to the nominal feedback voltage, VFB, by the factor: [(VTH –VFB)/VFB]. Note 11: An internal delay circuit prevents triggering of the overvoltage crowbar circuit, for pulse widths less than 400 ns, to ensure noise immunity. Note 12: This is the minimum supply voltage for which the power-on reset flag will continue to be valid (low). Note 13: For VS k VUV, the output is offÐit is in a high-impedance state. Note 14: A resistor/capacitor circuit is normally connected from the soft start circuit, pin 3, to ground. The circuit provides a slow or ‘‘soft’’ start of the IC by slowly ramping the reference voltage from a lower initial value set by the resistor to its normal operating value. See detailed description of this feature in the Pin-by-Pin Description section or the Functional Description section of this datasheet. Connection Diagram and Ordering Information 14-Lead Package Top View TL/H/11436 – 2 For Surface Mount Package Order Number LM3101M See NS Package Number M14B For DIP Package Order Number LM3101N See NS Package Number N14A 4 Typical Performance Characteristics For FO e 500 kHz, RT e 25 kX For FO e 1 MHz, RT e 12.5 kX Supply Current Supply Current vs Supply Voltage Oscillator Frequency Oscillator Frequency vs Supply Voltage Short Circuit Oscillator Frequency Reference Voltage Power On Reset Delay Minimum Over-Voltage Trigger Pulse Width Undervoltage Lockout Soft-Start Current Current Mode Input Limit Voltage Compensation Current Ramp Slope TL/H/11436 – 3 5 Typical Performance Characteristics (Continued) Error Amplifier Open Loop Frequency Response Error Amplifier Step Response TL/H/11436 – 4 Pin-by-Pin Description Pin Ý Symbol Function Description 1 RT Frequency Setting Resistor Connecting a resistor, RT, between this pin and ground programs the frequencyÐ from 50 kHz to 1 MHzÐby the following equation: [F, Hz, X]. RT e 0.25/(FO # 20 # 10b12) RT also sets the internal bias current, which affects the operation of several subcircuits within the IC. 2 MC Mode Control For voltage mode operation, connect a resistor, RMC, from this pin to the supply voltage. For current mode operation, this pin is tied to ground via resistor RMC. A current is sourced from the pin through the resistor such that it sets the slope of the compensating ramp, ICOMP, according to the equation: [mA/ms, X]. DICOMP/DT e 24 # 103/(RT # RMC) 3 SFST Soft-Start Control A series resistor-capacitor network tied from this pin to ground provides Soft-Start capability. The current charging the capacitor is: [A, V, X]. ISFST e 0.45/RT. Leave this pin open if it is not used. 4 SYNC Synchronization Signal Input An external negative pulse fed to this input will synchronize the internal oscillator. The frequency range of the external signal should be between 1.1 to 1.5 times the free-running frequency. Connect this pin to ground if it is not used. 5 RSC Short Circuit Frequency Shift Control A resistor, RSC, connected from this pin to the regulator output, determines the oscillator frequency during a short circuit by the formula: [F, Hz, X]. RSC e 0.09/[(0.267/RT) - FSC # 20 # b12] or, alternately, [F, Hz, X]. FSC e (1/20 # 10b12) # [(0.267/RT) - (0.09/RSC)] The recommended minimum ratio of short circuit frequency to oscillator frequency is one-third (nominal). 6 CMI Current Mode Input An analog voltage signal, proportional to the transformer primary current, fed to this input results in current mode operation. Connect this pin directly to ground if selecting voltage mode operation. 7 GND Ground Ground. 8 VOUT Output Output pin. It produces a PWM pulse train that is fed back to the primary side of the regulator, via a pulse transformer. 9 VS Supply Voltage Supply voltage. 10 CD Crowbar Output Driver This pin delivers a current when an overvoltage condition occurs on the output. It can be used to fire an external SCR to crowbar the output. Leave the pin open if not used. 6 Pin-by-Pin Description (Continued) Pin Ý Symbol 11 POR Power-On Reset Flag Function This open-collector output is driven low when either the supply voltage falls below the Undervoltage Lockout Threshold Voltage or the output voltage is less than the Poweron Reset Threshold Voltage. Leave the pin open if not used. Description 12 CRD Reset Delay Capacitor Adding a capacitor between this pin and ground sets the power-on reset flag delay time according to the following formula: [F, s, X]. CRD e TDR/60 # 103 Leave the pin open if not used. The POR flag will still operate if this function is not used. 13 FB Feedback Input A sample of the output voltage, via a resistor divider, is fed back into this pin, which is the inverting input of the error amplifier. 14 EAO Error Amplifier Output Error Amplifier Output. The output can source 1.5 mA typically and sink 300 mA typically. This pin is primarily used for loop compensation. Note: Pins 1, 2, 4, 5, and 10 are internally clamped by a 5.6V zener diode. Do not force a voltage larger than 5V on these pins without a resistor to limit the current to below 1 mA. All other pins are limited to the supply voltage. Test Circuit LM3101 specifications are measured using automated test equipment. This circuit is provided for the customer’s convenience when checking parameters. Due to possible variations in testing conditions, the measured values from these testing procedures may not match those of the factory. TL/H/11436 – 5 (typical). The maximum duty cycle of 92% typically can also be measured. Closing SW3 on pin RSC and putting SW7 (pin FB) in the open position will change the oscillator frequency to approximately 180 kHz. Switching the MC pin, SW1, to ground and opening SW4, the CMI pin, will put the device in current mode control. To measure the current sense time delay (typically 75 ns), close SW5 (connected to the CMI pin) and open SW6. This test circuit is for exercising the LM3101 functions and measuring its specifications. With the switch positions shown, the supply current should measure 15 mA (typical) for a supply voltage of 15V. Changing the supply voltage to 5V and opening SW6 on the VOUT pin should make the supply current 11 mA (typical). Changing SW7 to the supply voltage will shutdown the LM3101 output. To test the oscillator section, adjust the 5 kX potentiometer at the RT pin such that the oscillator frequency is approximately 500 kHz. Switch SW2 to obtain a 1 MHz frequency 7 Functional Description Oscillator/Synchronization Section The oscillator frequency should range from 67% to 90% of the synchronization frequency. In the above example, the oscillator frequency can be between 400 kHz and 540 kHz. The operating frequency is set by a single resistor connected from the RT pin (pin 1) to ground, according to the equation: [kHz, X]. FO e 0.25/(RT # 20 pF) Inserting a 25 kX for RT sets the oscillator frequency at 500 kHz. The oscillator is capable of synchronizing to an external source. To synchronize the oscillator, an external source is connected to the SYNC pin (pin 4) via a differentiator (see Figure 1 ). The external source delivers a pulse train to the differentiator, which converts this signal into an AC-coupled signal. The negative-edge of this signal, applied to the SYNC pin, will control the oscillator, and thus set the operating frequency. The recommended values for RSYNC and CSYNC are as follows: RSYNC e 1 kX (typical) and CSYNC # RSYNC l 1/(8 # FSYNC) [F, X, kHz]. To synchronize to a 600 kHz external source, and using a RSYNC of 1 kX, the CSYNC must be: CSYNC l 1/(8 # RSYNC # FSYNC) e 1/(8 # 1 kX # 600 kHz) e 208 pF & 220 pF. TL/H/11436 – 6 FIGURE 1. Simplified Version of the Synchronization Circuit TL/H/11436 – 7 FIGURE 2. Simplified Version of the Short Circuit Frequency Shift Circuit 8 Functional Description (Continued) Frequency-Shift Circuit If RSC2 is omitted, the frequency starts to shift when VOUT drops below VREF. The short circuit frequency equation then becomes: [kHz, X] FSC e (1/20 pF) # [(0.267/RT) b (0.09/RSC1)] The LM3101 has the ability to gradually reduce its operating frequency during an output short circuit. The amount that the frequency shifts and the output voltage threshold determining where the frequency starts to shift are both programmed by two external resistors, RSC1 and RSC2, connected to the pin RSC (pin 5). A simplified internal schematic of the Frequency Shift Circuit is shown in Figure 2 . The oscillator operates at its nominal frequency as long as the voltage at the emitter of the transistor Q2 is higher than the internal reference voltage, VREF. Q2 emitter voltage is the output voltage, VOUT, scaled down by the resistor divider: VRSC e VQ2E e VOUT # RSC2/(RSC1 a RSC2) [V, X] v [X, kHz]. RSC1 e 0.09/[(0.267/RT) b (FSC # 20 pF)] Selecting a short-circuit frequency that is greater than onethird the operating frequency or 188 kHz leads to a resistor value of: RSC1 e 0.09/[(0.267/25 kX) b (188 kHz # 20 pF)] e 13 kX. Mode Control The LM3101 can operate in voltage mode, current mode, or charge mode control. Two multi-function pins are involved in setting the operating mode, the Mode Control pin (MC - pin 2) and the Current Mode Input pin (CMI - pin 6). Figure 3 shows the simplified schematic diagram of the mode control circuit. To operate with voltage mode control, the MC pin is pulled high with a resistor (typically 3 kX), and the CMI pin is connected to ground. The mode comparator senses the MC pin voltage and sets the mode control multiplexer to voltage mode control. Notice that there is a 5.6V zener diode clamping the MC pin voltage. where VQ2 l VREF (1.24V) for normal operation. If VOUT drops, due to an overload, a current starts to flow through Q2. A cascoded current mirror causes one-tenth of this current to be subtracted from the timing capacitor charge current. Reducing the timing capacitor charge current results in decreasing the oscillator frequency. The breakpoint where the frequency-shift starts is programmed by the ratio of the two resistors: VOUT(SC) e 1.24V # [1 a (RSC1/RSC2)] [V, X]. The typical short circuit frequency is set by the following equations: FSC e [IOSC b 0.1 # À((1.24V b VOUT(SC))/RSC1) a [kHz, mA, V, X] (1.24V/RSC2)Ó] [1/(20 pF # 1.24V)] where IOSC e 0.25 # (1.24V/RT). For example, say 140 kX and 100 kX were selected for RSC1 and RSC2, respectively, with RT set to 25 kX. Then the output voltage level where the frequency starts to decay is: VOUT(CL) e 1.24V # [1 a (140 kX/100 kX)] j 3.0V, and the short circuit frequency is (IOSC e 12.4 mA and assuming VOUT is 0V during a short circuit): FSC e [12.4 mA b 0.1 # À(1.24V/140 kX) a (1.24V/100 kX) Ó] [1/(20 pF # 1.24V)] e 414.3 kHz j 415 kHz. TL/H/11436 – 8 FIGURE 3. Simplified Version of the Mode Control Circuit TL/H/11436 – 9 FIGURE 4. Current Mode Sense Circuit 9 Functional Description (Continued) The resistor RF together with the capacitor CF serves as an RC filter for the leading edge spike of the current sense waveform (the spike is caused by the output rectifier reverse recovery and/or the winding capacitance of the power transformer). To operate under current mode or charge mode control, insert a resistor, RMC, between the MC pin and ground, and connect the CMI pin to the Current Mode Sense Circuit (see Figure 4 ). At the MC pin, a voltage, proportional to the oscillator ramp voltage, develops (see Figure 3 ). The voltage ramp applied to RMC generates a current ramp, which is duplicated on the CMI pin due to the current mirror. The current ramp, which flows, out of the CMI pin to the resistor, RF, is the compensation ramp, needed to stabilize converters operating at duty cycles above 50%. The slope of the compensating ramp can be scaled by RF, which is connected between the CMI pin and the terminating resistor, RS, of the current sense transformer. In all practical cases, RF will be much greater than RS. For both control modes, the current ramp provides slope compensation according to the equation: [mA/ms, X]. DICOMP/Dt e 24 # 103/(RT # RMC) CHARGE MODE CONTROL Under charge mode control, the current sense transformer drives a capacitor, C1, that integrates the sensed switch current on a cycle-by-cycle basis. Figure 5 shows the integrating current sense circuitry and the simplified details of the associated internal circuitry of the LM3101. Transistor Q1 discharges the integrating capacitor C1 once every switch cycleÐduring the switch off-time (Q1 can provide up to 20 mA of discharge current). Charge mode control yields the fastest average current control loop. So, with RT equal 25 kX and RMC equal 6 kX, the compensation ramp slope is: DICOMP/Dt e 24 # 103/(25 kX # 6 kX) e 160 mA/ms. TL/H/11436 – 11 TL/H/11436 – 10 FIGURE 5. Charge Mode Operation 10 Functional Description (Continued) Soft-Start Section to its nominal value as CSFST charges up. When CSFST charges up completely, the reference voltage is at its nominal value, start-up is over and steady-state operation begins. The discharge time of CSFST is set by the RC network as: Soft-Start is accomplished by gradually increasing the reference voltage during start-up. The gradual increase is implemented by charging the Soft-Start capacitor, CSFST, on pin 3 (the SFST pin). The charging current is set according to the following equation: [A, X]. ISFST e 0.45/RT tDS e 5 # CSFST # R2. This is the time delay required to prepare the Soft-Start cycle after the LM3101 and the entire regulator has been turned off. R2 must be large enough so that the final value of VSFST is greater than the reference voltage: VSFST e ISFST # (R1 a R2) t 1.24V [V, A, X]. Power Supply Monitor Functions The LM3101 provides two monitor functions, a power-on reset flag with programmable delay, and a crowbar driver output for overvoltage conditions. POWER-ON RESET The power-on reset (POR) flag monitors the output voltage via the feedback pin (FB - pin 13). The POR flag will go low after the output voltage reaches 95% of its nominal value, and the subsequent programmed delay has passed. The POR flag pin (pin 11) is an open-collector pin which needs an external resistor to pull it up. This pin is valid with supply voltages as low as 1V while sinking 1.6 mA. To program the reset delay, connect an external capacitor to the CRD pin (pin 12). The practical range of delay is from 10 ms to 5 ms, and follows the equation: [s, F]. TRD e CRD # 60 # 103 For a power-on reset delay of 120 ms, the reset delay capacitor must be 0.002 mF. TL/H/11436 – 12 FIGURE 6. Soft-Start Block Diagram Typically, ISFST starts to flow when the supply voltage is raised above 3V. As shown in Figure 6 , at the beginning of start-up, CSFST is not charged up, and the SFST pin pulls down the reference voltage from its nominal value to: [V, A, X]. VSFSTO e ISFST # R1 CROWBAR DRIVER OUTPUT The second monitor function is a crowbar driver output (CD – pin 10). If the output voltage gets higher than 120% of its nominal value, the CD pin can supply more than 200 mA to an external SCR trigger input. The SCR will fire, shorting the regulator output and saving the load circuitry from excessive supply voltage. VSFSTO is designed to be 85% of the nominal reference voltage. The reference voltage rises smoothly from VSFSTO 11 Typical Applications CAUTION: HIGH VOLTAGE Handle with Extreme Care TL/H/11436 – 13 FIGURE 7. Offline Voltage Mode Flyback Regulator output ripple voltage to 50 mV. As shown in Figure 8 , the regulator can respond to a ‘‘step’’ change in load current from 1A to 10A in about 12 ms. The efficiency of the converter is approximately 80% at full load. This 500 kHz Offline Converter delivers 50W (5V @ 10A) from an input supply ranging from 90 VAC to 132 VAC (127 VDC to 185 VDC). The regulator achieves a line regulation of 0.06% and a load regulation of 0.05%. A 0.5 mH inductor and 100 mF capacitor form an LC filter that reduces the TL/H/11436 – 14 A: Output Voltage, 500 mV/div., AC Coupled B: Load Current, 5A/div. Horizontal Time Base: 20 ms/div. FIGURE 8. Load Step Response 12 Typical Applications (Continued) charged to a voltage of approximately 2.1V, the device will try to restart. If the overcurrent condition persists, the device will shut down again. The LM3101 provides the fault protection in case of an output short circuit. During normal operation, the operating frequency of this circuit is determined by a 25 kX resistor connected to pin 1 of the LM3101. However, during a short circuit condition on the output, the frequency of the LM3101 (and the entire circuit operating frequency) drops, yielding a very low duty cycle. This short-circuit frequency is set by the 13 kX resistor connected to pin 5. The LM3101 Mode Control and Current Mode Input pins (pins 2 and 6 respectively) are for current mode control operation. The MC pin determines which control mode is being usedÐthe resistor tied to the supply voltage means voltage mode control (the resistor tied to ground would indicate current mode control). POWER STAGE OPERATION The LM3001 Primary-Side PWM Driver sends a pulse-widthmodulated signal (via pin 8) to a power switch, which in turn, drives a power transformer. The power switch used in this case is an IRF840 Power MOSFET. It is an N-channel enhancement mode device that has a drain-to-source voltage (VDSS) rating of 500V and a pulsed drain current (IDM) rating of 32A. Even though the Power MOFSET has a high VDSS, snubber circuits are needed to limit the drain voltage. The power transformer has a primary inductance of 87 mH. The primary-to-secondary turns ratio is 8.5 to 1 and the secondary-to-tertiary turns ratio is 1 to 2.5. The tertiary winding delivers the LM3001 supply voltage (pins 7 and 12) to the primary-side driver. There is an internal Overvoltage Threshold circuit (pin 10) monitoring the input voltage via a resistor divider. The overvoltage trip point is 3.3V typically. With the resistor values shown, the maximum supply voltage is approximately 17.5V. The output rectifier, an SR1606, delivers the secondary current to the output. The SR1606 is specified for 16A forward current, 60V reverse breakdown voltage, and comes to a TO220-AB package. Since the SR1606 dissipates 7W to 8W at full load, it requires a heatsink. An RC snubber is placed in parallel to reduce the ringing voltage caused by the output rectifier turning off during the discontinous mode of operation. Two Cornell Dubilier type 226 470 mF, 25V high frequency capacitors, with low ESRs of 0.25X, are used as the output capacitors. START-UP OPERATION When power is initially applied to the regulator, the LM3001 Primary-Side PWM Driver receives its supply current through a 75 kX resistor connected to the input voltage (see Figure 7 ). Once the supply pin voltage reaches the threshold of 11.8V (typical), the LM3001 turns on, sending pulse signals (with an amplitude of approximately 10V) to the gate of the Power MOSFET. Because the output is driving Power MOSFETs, which need gate-to-source voltages greater than 10V for hard turn-on (low RDS(ON)), the threshold voltage of 11.8V was selected to insure sufficient output voltage. At the beginning of the start-up process, the secondary side of the regulator is still unbiasedÐhence the LM3001 does not receive a feedback signal from the secondary side (see the Start-up Sequence in Figure 9 ). Before the LM3101 Secondary-Side PWM Controller is controlling the circuit, the initial operating frequency of the gate drive is determined by the LM3001 internal oscillator. The oscillator uses an external capacitor and resistor, on pins 14 and 1 respectively. The initial operating frequency in this case is approximately 500 kHz. During this time, the regulator is operating in a ‘‘free-running’’ state. Also during the start-up, the LM3001 executes Soft-Start by using the Soft-Start capacitor on pin 4. The voltage across this capacitor is compared to the oscillator ramp on pin 14 (see the LM3001 block diagram). In the offline regulator, the Soft-Start time is 15 ms approximately. During this time, as the Soft-Start capacitor charges up, the duty cycle increases with each progressive cycle, until finally the duty cycle reaches its maximum value set by the Duty Cycle Limit circuit (RDL - pin 2) or the Current Limit circuit (CLIM - pin 6). The Soft-Start phase ends when the duty cycle is limited by the RDL circuit. A resistor at this pin connects to an internal current source which together will generate a voltage that will be compared to the oscillator ramp voltage. This comparison will determine the maximum duty cycle during this phase of the start-up cycle. For the circuit in Figure 7 , the duty cycle is limited to 63% by the RDL circuit. OUTPUT VOLTAGE CONTROL The output voltage is controlled by the LM3101 SecondarySide PWM Controller. The LM3101 uses its error amplifier to compare the scaled-down output voltage against the internal precision 1.24V reference voltage. The error amplifier provides compensation for the regulator frequency response, by way of an RC feedback network. The resulting error voltage is converted into a pulse-widthmodulated waveform at the system oscillator frequency of approximately 500 kHz. This waveform is then differentiated (using an external high-pass RC filter) into a series of positive and negative pulses representing the desired switch duty cycle. The pulses are transferred through a pulse transformer to the LM3001 Primary-Side Driver. The driver takes the feedback pulse signal and converts it into a PWM gate drive for the Power MOSFET. FAULT RECOVERY OPERATION A 0.167X resistor sets the peak primary current limits to 2.28A for the pulse-by-pulse limiting, and to 3.60A for the second-level limit. An RC network filters the current limit voltage to prevent the current limit (pin 6) from being activated by the reverse recovery spike of the output rectifier. When the second level current limit is triggered, the LM3001 shuts down and discharges the capacitor connected to pin 5 (the Shutdown Delay capacitor). After the capacitor is re- 13 Typical Applications (Continued) pulse train to the differentiator circuit on pin 8. The resulting PWM signals are fed back to the LM3001 via the pulse transformer. The first pulse signal to the LM3001 will cause it to disconnect its internal oscillator from its PWM and Output Driver circuits and trigger the Output Driver from the pulse feedback signals (of the LM3101). At this point, control of the frequency and the duty cycle changes from the LM3001 to the LM3101. The LM3101 also exercises Soft-Start capability (pin 3). An RC network connected to this pin allows the LM3101 to gradually increase the duty cycle to its nominal value (in the example, the secondary Soft-Start time delay is 500 ms approximately). The method of Soft-Start used by the LM3101 ensures that the error amplifier is in its linear region before the output voltage reaches its nominal value, thus yielding a smooth start-up of the output without any overshoot (see Figure 10 ). The duty cycle will reach the RDL limit for several cycles, letting energy build up in the transformerÐsee the drain current waveform in Figure 9 . When the residual energy builds up enough, the duty cycle starts to decrease because it is now determined by the CLIM circuit. A voltage of 0.38V or greater at this pin will toggle a pulse-by-pulse comparator on every cycle (see the LM3001 block diagram). In the application circuit, a 0.167X resistor will generate the current limit threshold voltage when a 2.28A (peak) current flows through it. With the CLIM circuit in control of the duty cycle, the duty cycle will decrease with each successive cycle. The duty cycle will continue to shrink until the pulse feedback from the LM3101 takes control. As the LM3001 switches the Power MOSFET on and off, the Power Transformer starts delivering power to the secondary side of the circuit. This action will cause the supply voltage of the LM3101 and the output voltage to gradually rise. When the supply voltage reaches the Undervoltage Lockout Threshold (of 3.9V), the LM3101 starts supplying a (Representative not to scale) FIGURE 9. Start-Up Timing Sequence 14 TL/H/11436 – 15 Typical Applications (Continued) MOSFET PARAMETERS The peak current through the primary inductance and the Power MOSFET is the average current when the switch is on plus one-half the primary inductance ripple current: IPRI(PK) e IIN(TON) a (DIP/2) e 1.77A a (0.81A/2) e 2.18A Assuming ideal conditions, the maximum voltage at the drain of the Power MOSFET when the switch is off is: VSW(OFF) e (VO a VF) (NP/NS) a VIN(MAX) e (5.7V) (8.5) a 185V e 233V x 250V. However, leakage inductance exists in the transformer, causing a voltage spike immediately after the switch turns off. This voltage spike will add to the rest of the drain voltages, making VSW(OFF) even greater. With a leakage inductance that is 2% of the transformer primary inductance and selecting a switch which has a fall time of 2% the total offtime, the added voltage will be: VLL e 2% # LP # IPRI(PK) # FO/[2% # (1 –D(MAX))]. TL/H/11436 – 16 Output Voltage, 1V/div. Horizontal Time Base: 500 ms/div. FIGURE 10. Output Voltage Start-up At the end of the start-up sequence, the circuit is in steadystate or normal PWM operation. Design Procedure For the Offline Voltage Mode Flyback Regulator (Figure 7 ), the specifications for the power transformer, MOSFET switch, the switch snubber, and the output rectifier can be calculated based on the system specifications: System specifications: VO e 5 VDC VI Range e 90 VAC–132 VAC IO Range e 0.5A–10A Efficiency (h) & 80% FO e 500 kHz. The maximum duty cycle of 28% is used for worst case purposes. Thus, the leakage inductance voltage spike is: VLL e 0.02 # 87 mH # 2.18A # 500 kHz/[0.02 # (1 – 0.28)] e 130V x 150V. This means the actual peak drain voltage is approximately 400V. When choosing the Power MOSFET, add some margin to this number. A 500V MOSFET was used in this application. SNUBBER DESIGN A ‘‘snubber’’ circuit, consisting of a 1N4937 fast recovery diode and a parallel RC network, is inserted around the transformer primary to clamp the voltage spike. This is to reduce the switch voltage stress when it is off. The ‘‘snubber’’ components are calculated in the following manner: CSN t 0.02 # LP # IP(PK)2/(VMAX2 b VSN2) e 0.02 # 87 mH # (2.18A)2/[(255V)2 b (250V)2] & 3.3 nF TRANSFORMER SPECIFICATIONS Manipulating the transfer function of a flyback regulator results in a calculation for the turns ratio of the power transformer, involving the minimum input voltage, the output voltage, and the maximum duty cycle (D): VO a VF e (VIN(MIN) – VSW(ON)) # (NS/NP) # (D(MAX)/(1– D(MAX))) v and RSN s [(VMAX a VSN b VIN)/2] 2 # [100/(FO # LP # IP(PK)2)] e [(255V a 250V b 185V)/2] 2 # [100/(500 kHz # 87 mH # (2.18A)2)] & 12 kX. In the Offline Flyback Regulator application, a 0.01 mF capacitor and a 10 kX resistor are used as the snubber components. VMAX is the selected maximum voltage at the drain of the MOSFET. Usually the RC values are selected so that VMAX is 5V to 10V higher than VSN. The power dissipation of the resistor is: P e [(VMAX a VSN b VIN)/2] 2/R e [(255V a 250V b 185V)/2] 2/10 kX e 2.56W. To add some margin, a 4W resistor is chosen. The fast recovery diode must have a reverse voltage rating greater than VMAX. The 1N4937 has a 600V rating. NS/NP e [(VO a VF)/(VIN(MIN) – VSW(ON))] # ((1 – D(MAX))/D(MAX)) Assume that the diode forward voltage (VF) is about 0.7V and the drain-to-source voltage when the switch is on (VSW(ON)) is approximately 0.9V. Selecting a 28% maximum duty cycle results in a turns ratio of: NS/NP e (5.7V/126.1V) # (1–0.28)/0.28 e 0.12 (NP/NS e 8.5/1). Assuming an efficiency (h) of 80%, the average input current (at the maximum load current and for the entire period) is: IIN e (VO) (IO)/ (VIN(MIN) # h) e (50W)/(127V # 0.80) e 0.49A. The average current when the switch is on is the average current over the entire period divided by the duty cycle: IIN(TON) e IIN/D e (0.49A)/(0.28) e 1.77A. OUTPUT DIODE PARAMETERS The peak secondary current can be calculated using the peak primary current and the turns ratio (this equation is for single output flyback regulators): ISEC(PK) e IPRI(PK) # (NP/NS) e 2.18A # 8.5 e 18.43A x 20A. Selecting the primary inductance ripple current (DIP) to be a certain percentage of IIN(TON), and combining that with the duty cycle, input voltage, and operating frequency, gives the primary inductance by the equation: LP e (VIN(MIN) – VSW(ON)) # D(MAX)/ (DIP # FO) Assuming the percentage to be 46% in the example, then: LP e 126.1V # 0.28/(0.81A # 500 kHz) j 87 mH. 15 Typical Applications (Continued) exceptions are the power transformer, in which the turns ratio and primary inductance has changed (due to the change in the input voltage range), and the Power MOSFET, which has a lower on-resistance and a lower breakdown voltage rating. The most significant difference in the circuit design is the change in the mode of operationÐfrom voltage mode to current mode. For current mode operation, the LM3101 Mode Control pin (MC – pin 2) is connected to ground by a 6 kX resistor, and the Control Mode pin (CMI – pin 6) is connected to the current sense transformer through a halfwave rectifier circuit and a low-pass filter. The filter is needed to remove the leading edge spike on the current waveform, caused by the rectifier recovery and interwinding capacitance of the power transformer. Smaller component differences include reducing the current sensing resistor in the primary side ground path (to allow for the larger primary current), and removing a primary side snubber circuit (due to smaller peak voltages at the drain). Also, the output rectifier and Power MOSFET snubbers are modified. The maximum average current through the secondary and the diode, when the switch is off, is the maximum load current divided by the inverse of the duty cycle: ISEC(OFF) e ILOAD/(1 – D(MAX)) e 10A/0.72 e 13.90A & 15A. The maximum average secondary current for the entire period is the maximum load current (10A). The maximum reverse-bias voltage on the output rectifier is: VRV e VIN(MAX) # (NS/NP) a VO a VF e (185V) (1/8.5) a 5.7V e 27.47V & 30V. A suitable diode for this circuit is the SR1606, which has a reverse voltage rating of 60V and an average current rating of 16A. Telecom Converter The schematic of a flyback regulator, used in Telecom applications, is shown in Figure 11 . The circuit has many of the component values that are in the offline converter. Notable TL/H/11436 – 17 FIGURE 11. Telecom Current Mode Flyback Regulator 16 Application Hints Pulse Feedback Section During steady-state operation, the LM3101 delivers pulsewidth modulated signals to the feedback circuit. The feedback circuit will convert that signal into a series of AC-coupled pulse signals and apply them to the LM3001 via the pulse transformer (the first positive-edged pulse from the LM3101 will cause the LM3001 to disconnect its internal oscillator from its PWM and Output Driver circuits). The feedback pulses will trigger the LM3001 Output Driver to apply PWM drive signals to the Power MOSFET gate. The timing diagram in Figure 12 demonstrates the feedback communication. Pulse Interface Circuit The pulse interface circuit provides isolation for the feedback circuit of the Offline Flyback Regulator. The differentiator circuit converts the PWM waveform into a pulse train. The differentiator delivers a train of 1VPK, 15 ns wide pulses to the pulse transformer. The core should have high permeability (typically 10,000) at the switching frequency to allow the transfer of energy with a very small transformer (size). This one-to-one transformer transfers the pulse train to the LM3001 via a 200X resistor, which is used mainly to filter noise from the system. TL/H/11436 – 18 FIGURE 12. Pulse Feedback Timing Diagram TL/H/11436 – 19 FIGURE 13. Pulse Interface Circuit 17 18 Physical Dimensions inches (millimeters) 14-Lead Package For Surface Mount Package Order Number LM3101M NS Package Number M14B 19 LM3101 Secondary-Side PWM Controller Physical Dimensions inches (millimeters) (Continued) For DIP Package Order Number LM3101N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.