DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com 12-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC7551-Q1 FEATURES DESCRIPTION • • • • • • • • • • • The DAC7551-Q1 is a single-channel, voltage-output digital-to-analog converter (DAC) with exceptional linearity and monotonicity, and a proprietary architecture that minimizes glitch energy. The low-power DAC7551-Q1 operates from a single 2.7V to 5.5V supply. The DAC7551-Q1 output amplifiers can drive a 2kΩ, 200pF load rail-to-rail with 5μs settling time; the output range is set using an external voltage reference. 1 234 • • • • Qualified for Automotive Applications Relative Accuracy (INL): ±0.35LSB Ultra-Low Glitch Energy: 0.1nV-s Low Power Operation: 100μA at 2.7V Power-On Reset to Zero Scale Power Supply: 2.7V to 5.5V Single Supply Power-Down: 0.05μA at 2.7V 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5μs (Max) SPI-Compatible Serial Interface with Schmitt-Trigger Input: Up to 50MHz Daisy-Chain Capability Asynchronous Hardware Clear to Zero Scale Specified Temperature Range: –40°C to +105°C Small, 2 x 3 mm, 12-Lead SON Package The 3-wire serial interface operates at clock rates up to 50MHz and is compatible with SPI™, QSPI™, Microwire™, and DSP interface standards. The parts incorporate a power-on-reset circuit to ensure that the DAC output powers up to 0V and remains there until a valid write cycle to the device takes place. The part contains a power-down feature that reduces the current consumption of the device to under 2μA. Small size and low-power operation make the DAC7551-Q1 ideally suited for battery-operated, portable applications. The power consumption is typically 0.5mW at 5V, 0.23mW at 3V, and reduces to 1μW in power-down mode. APPLICATIONS • • • • • Portable, Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The DAC7551-Q1 is available in a 12-lead SON package and is specified over –40°C to +105°C. FUNCTIONAL BLOCK DIAGRAM VDD IOVDD VREFH VFB SCLK _ SYNC Interface Logic Shift Register DAC Register String DAC + VOUT SDIN Power-On Reset SDO CLR Power-Down Logic GND VREFL 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR DAC7551-Q1 SON-12 DRN SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +105°C RAN For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). UNIT VDD , IOVDD to GND –0.3V to 6V Digital input voltage to GND –0.3V to VDD + 0.3V VOUT to GND –0.3V to VDD + 0.3V Operating temperature range –40°C to +105°C Storage temperature range –65°C to +150°C Junction temperature (TJ Max) Power dissipation (DRN) +150°C (TJ max – TA)/θJA Thermal impedance, θJA 79°C/W Thermal impedance, θJC 48.57°C/W (1) 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS all specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = GND, RL = 2kΩ to GND, and CL = 200pF to GND (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ±0.35 ±1 LSB ±0.08 ±0.5 LSB ±12 mV STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design Bits Offset error Zero-scale error ±12 All zeroes loaded to DAC register Gain error Full-scale error Zero-scale error drift Gain temperature coefficient PSRR VDD = 5V mV ±0.15 %FSR ±0.5 %FSR 7 μV/°C 3 ppm of FSR/°C 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 2 x VREFL RL = 2kΩ, 0pF < CL < 200pF Slew rate Capacitive load stability Digital-to-analog glitch impulse VREFH V 5 μs 1.8 RL = ∞ V/μs 470 RL = 2kΩ pF 1000 1 LSB change around major carry 0.1 Digital feedthrough nV-s 0.1 nV-s Output noise density 10kHz offset frequency 120 nV/√Hz Total harmonic distortion fOUT = 1kHz, fS = 1MSPS, BW = 20kHz –85 dB 1 Ω DC output impedance Short-circuit current Power-up time VDD = 5V 50 VDD = 3V 20 Coming out of power-down mode, VDD = 5V 15 Coming out of power-down mode, VDD = 3V 15 mA μs REFERENCE INPUT VREFH Input range VREFL Input range 0 VREFL < VREFH 0 Reference input impedance Reference current VDD GND VDD 100 V V kΩ VREF = VDD = 5V 50 100 VREF = VDD = 3V 30 60 μA LOGIC INPUTS (2) Input current VIN_L, Input low voltage IOVDD ≥ 2.7V VIN_H, Input high voltage IOVDD ≥ 2.7V Pin capacitance (1) (2) ±1 μA 0.3 IOVDD V 3 pF 0.7 IOVDD V Linearity tested using a reduced code range of 30 to 4065; output unloaded. Specified by design and characterization; not production tested. For 1.8V < IOVDD < 2.7V, it is recommended that VIH ≥ 0.8 IOVDD, and VIL ≤ 0.2 IOVDD. Copyright © 2011, Texas Instruments Incorporated 3 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) all specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = GND, RL = 2kΩ to GND, and CL = 200pF to GND (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD IOVDD IDD (3) (4) Normal operation (DAC active and excluding load current) All power-down modes 2.7 5.5 V 1.8 VDD V VDD = 3.6V to 5.5V, VIH = IOVDD, VIL = GND 150 200 VDD = 2.7V to 3.6V, VIH = IOVDD, VIL = GND 100 150 VDD = 3.6V to 5.5V, VIH = IOVDD, VIL = GND 0.2 2 VDD = 2.7V to 3.6V, VIH = IOVDD, VIL = GND 0.05 2 μA μA POWER EFFICIENCY IOUT/IDD ILOAD = 2mA, VDD = 5V 93 % TEMPERATURE RANGE Specified performance (3) (4) 4 –40 +105 °C IOVDD operates down to 1.8V with slightly degraded timing, as long as VIH ≥ 0.8 IOVDD and VIL ≤ 0.2 IOVDD. IDD tested with digital input code = 0032. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com PIN CONFIGURATION VDD 1 12 IOVDD VREFH 2 11 SDO VREFL 3 10 SDIN 9 SCLK 8 SYNC 7 CLR DAC7751 VFB 4 VOUT 5 GND 6 Thermal Pad(1) Pin Descriptions PIN NO. (1) NAME DESCRIPTION 1 VDD Analog voltage supply input 2 VREFH Positive reference voltage input 3 VREFL Negative reference voltage input 4 VFB DAC amplifier sense input. 5 VOUT Analog output voltage from DAC 6 GND (1) Ground. 7 CLR Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000h and the output voltage to 0V. 8 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7551-Q1. 9 SCLK Serial clock input 10 SDIN Serial data input 11 SDO Serial data output 12 IOVDD I/O voltage supply input Thermal pad should be connected to GND. Copyright © 2011, Texas Instruments Incorporated 5 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com SERIAL WRITE OPERATION t1 SCLK t8 t2 t3 t4 t7 SYNC t5 SDIN t6 D15 D14 D13 D12 D11 D1 D0 Input Word n D15 D0 t9 SDO Input Word n+1 D15 D0 D14 Input Word n Undefined t10 CLR Figure 1. Serial Write Operation Timing Diagram TIMING CHARACTERISTICS (1) (2) All specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, and RL = 2kΩ to GND (unless otherwise noted). PARAMETER t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 SCLK falling edge to SDO valid t10 CLR pulse width low (1) (2) (3) (4) 6 TEST CONDITIONS MIN VDD = 2.7V to 3.6V 20 VDD = 3.6V to 5.5V 20 VDD = 2.7V to 3.6V 6.5 VDD = 3.6V to 5.5V 6.5 VDD = 2.7V to 3.6V 6.5 VDD = 3.6V to 5.5V 6.5 VDD = 2.7V to 3.6V 4 VDD = 3.6V to 5.5V 4 VDD = 2.7V to 3.6V 3 VDD = 3.6V to 5.5V 3 VDD = 2.7V to 3.6V 3 VDD = 3.6V to 5.5V 3 VDD = 2.7V to 3.6V 0 VDD = 3.6V to 5.5V 0 VDD = 2.7V to 3.6V 20 VDD = 3.6V to 5.5V 20 VDD = 2.7V to 3.6V 10 VDD = 3.6V to 5.5V 10 VDD = 2.7V to 3.6V 10 VDD = 3.6V to 5.5V 10 TYP MAX UNITS ns ns ns ns ns ns t1 – 10ns (4) t1 – 10ns (4) ns ns ns ns All input signals are specified with tR = tF = 1ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1, Serial Write Operation timing diagram. Maximum SCLK frequency is 50MHz at VDD = 2.7V to 5.5V. SCLK falling edge to SYNC rising edge time shold not exceed (t1 – 10ns) in order to latch the correct data. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 VDD = 5V, VREFH = 4.096V, VREFL = GND 0.5 LE (LSB) LE (LSB) 1.0 0 0 -0.5 -1.0 -1.0 0.50 0.50 0.25 0.25 DLE (LSB) DLE (LSB) -0.5 VDD = 2.7V, VREFH = 2.5V, VREFL = GND 0.5 0 -0.25 -0.50 0 -0.25 -0.50 0 512 1024 1536 2048 2560 3072 3584 0 4096 512 1024 2560 3072 Figure 3. ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 3584 4096 1.00 VDD = 5V VREFH = 4.096V VREFL = GND Zero-Scale Error (mV) Zero-Scale Error (mV) 2048 Figure 2. 1.00 0.75 1536 Digital Input Code Digital Input Code 0.50 0.25 0 0.75 VDD = 2.7V VREFH = 2.5V VREFL = GND 0.50 0.25 0 -40 -10 20 50 Free-Air Temperature (°C) Figure 4. Copyright © 2011, Texas Instruments Incorporated 80 105 -40 -10 20 50 80 105 Free-Air Temperature (°C) Figure 5. 7 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE ERROR vs FREE-AIR TEMPERATURE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0 0 Full-Scale Error (mV) Full-Scale Error (mV) VDD = 2.7V VREFH = 2.5V VREFL = GND -0.25 -0.50 -0.75 VDD = 5V VREFH = 4.096V VREFL = GND -1.00 -0.25 -0.50 -0.75 -1.00 -40 20 -10 50 80 105 -40 20 -10 Free-Air Temperature (°C) 50 80 105 Free-Air Temperature (°C) Figure 6. Figure 7. SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 5.5 0.20 VDD = VREFH = 5.5V 0.15 Output Voltage, VO (V) Output Voltage, VO (V) Typical VDD = 2.7V VREFH = 2.5V VREFL = GND 0.10 VDD = 5.5V VREFH = 4.096V VREFL = GND 0.05 VREFL = GND 5.4 5.3 DAC Loaded with FFFFh DAC Loaded with 0000h 5.2 0 0 5 10 0 15 5 10 Figure 8. Figure 9. SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 250 VDD = VREFH = 2.7V VDD = 5.5V VREFH = 4.096V VREFL = GND 200 VREFL = GND 2.6 IDD (mA) Output Voltage, VO (V) 2.7 150 VDD = 2.7V VREFH = 2.5V VREFL = GND 100 2.5 50 Powered, No Load DAC Loaded with FFFFh 0 2.4 0 5 10 ISOURCE (mA) Figure 10. 8 15 ISOURCE (mA) ISINK (mA) 15 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 11. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs FREE-AIR TEMPERATURE 200 110 VDD = 5.5V VREFH = 4.096V VREFL = GND 150 VDD = 2.7V VREFH = 2.5V VREFL = GND 125 DAC Powered, No Load VREFH = 2.5V VREFL = GND 105 IDD (mA) 175 IDD (mA) SUPPLY CURRENT vs SUPPLY VOLTAGE 100 95 Powered, No Load 100 90 -40 -10 20 50 80 110 3.1 2.7 3.5 Free-Air Temperature (°C) 5.1 5.5 HISTOGRAM OF CURRENT CONSUMPTION - 5.5V 2000 1600 TA = +25°C SCLK Input All Other Input = GND 1200 1500 VDD = 5.5V VREFH = 4.096V VREFL = GND 800 Frequency (Hz) IDD (mA) 4.7 Figure 13. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE VDD = 2.7V VREFH = 2.5V VREFL = GND 400 Digital Input Code = 2048 VDD = 5.5V VREFH = 4.096V VREFL = GND 1000 500 0 0 0 1 2 3 4 128 5 VLOGIC (V) 136 144 152 160 168 176 Current Consumption (mA) Figure 14. 184 192 3584 4096 Figure 15. HISTOGRAM OF CURRENT CONSUMPTION - 2.7V TOTAL ERROR - 5V 4 2000 Digital Input Code = 2048 VDD = 2.7V VREFH = 2.5V VREFL = GND VDD = 5V VREFH = 4.096V VREFL = GND TA = +25°C 2 Total Error (mV) Frequency (Hz) 4.3 VDD (V) Figure 12. 1500 3.9 1000 500 0 -2 0 -4 117 124 131 138 145 152 159 Current Consumption (mA) Figure 16. Copyright © 2011, Texas Instruments Incorporated 166 173 0 512 1024 1536 2048 2560 Digital Input Code 3072 Figure 17. 9 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. TOTAL ERROR - 2.7V EXITING POWER-DOWN MODE 5 4 VDD = 2.7V VREFH = 2.5V VREFL = GND TA = +25°C 4 Output Voltage (V) Total Error (mV) 2 0 -2 VDD = 5V VREFH = 4.096V VREFL = GND Power-Up Code = 4000 3 2 1 0 -4 0 512 1024 1536 2048 2560 3072 3584 Time (4ms/div) 4096 Digital Input Code Figure 18. Figure 19. LARGE-SIGNAL SETTLING TIME - 5V Output Loaded with 200pF to GND Code 0041 to 4055 4 3 VDD = 5V VREFH = 4.096V VREFL = GND 2 1 0 Output Loaded with 200pF to GND Code 0041 to 4055 2 VDD = 2.7V VREFH = 2.5V VREFL = GND 1 0 Time (5ms/div) Figure 20. Figure 21. MIDSCALE GLITCH WORST-CASE GLITCH VO (5mV/div) VO (5mV/div) Time (5ms/div) Trigger Pulse Trigger Pulse Time (400ns/div) Figure 22. 10 LARGE-SIGNAL SETTLING TIME - 2.7V 3 Output Voltage, VO (V) Output Voltage, VO (V) 5 Time (400ns/div) Figure 23. Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY DIGITAL FEEDTHROUGH ERROR -40 VDD = 5.5V VREFH = 4.096V VREFL = GND fS = 1MSPS -1dB FSR Digital Input Measurement Bandwidth = 20kHz VO (5mV/div) -50 THD (dB) -60 -70 THD -80 2nd Harmonic -90 3rd Harmonic Trigger Pulse Time (400ns/div) Figure 24. Copyright © 2011, Texas Instruments Incorporated -100 0 1 2 3 4 5 6 7 Output Frequency, Tone (kHz) 8 9 10 Figure 25. 11 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER VREFH The architecture of the DAC7551-Q1 consists of a string DAC followed by an output buffer amplifier. Figure 26 shows a generalized block diagram of the DAC architecture. VREFH 100kW 100kW RDIVIDER VREFH - VREFL 2 R VFB 50kW DAC Register REF(+) Resistor String REF(-) VOUT R To Output Amplifier (2x Gain) VREFL Figure 26. Typical DAC Architecture The input coding to the DAC7551-Q1 is unsigned binary, which gives the ideal output voltage as: VOUT = 2 x VREFL + (VREFH – VREFL) x D/4096 Where D = decimal equivalent of the binary code that is loaded to the DAC register, which ranges from 0 to 4095. R R RESISTOR STRING The resistor string section is shown in Figure 27. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. It is specified monotonic because it is a string of resistors. 12 VREFL Figure 27. Typical Resistor String Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com OUTPUT BUFFER AMPLIFIERS Power-On Reset The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to VDD. It is capable of driving a load of 2kΩ in parallel with up to 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1.8V/μs with a half-scale settling time of 3μs with the output unloaded. On power up, all registers are cleared and the DAC channel is updated with zero-scale voltage. The DAC output remains in this state until valid data are written. This setup is particularly useful in applications where it is important to know the state of the DAC output while the device is powering up. In order to not turn on ESD protection devices, VDD and IOVDD should be applied before any other pin (such as VREFH) is brought high. The power-up sequence of VDD and IOVDD is irrelevant. Therefore, IOVDD can be brought up before VDD, or vice-versa. DAC External Reference Input The DAC7551-Q1 contains VREFH and VREFL reference inputs, which are unbuffered. The VREFH reference voltage can be as low as 0.25V, and as high as VDD because there is no restriction of headroom and footroom from any reference amplifier. Power Down It is recommended to use a buffered reference in the external circuit (for example, the REF3140). The input impedance is typically 100kΩ. The DAC7551-Q1 has a flexible power-down capability. During a power-down condition, the user has flexibility to select the output impedance of the DAC. During power-down operation, the DAC can have either 1kΩ, 100kΩ, or Hi-Z output impedance to ground. Amplifier Sense Input Asynchronous Clear The DAC7551-Q1 contains an amplifier feedback input pin, VFB. For voltage output operation, VFB must be externally connected to VOUT. For better DC accuracy, this connection should be made at load points. The VFB pin is also useful for a variety of applications, including digitally-controlled current sources. The feedback input pin is internally connected to the DAC amplifier negative input terminal through a 100kΩ resistor. The amplifier negative input terminal internally connects to ground through another 100kΩ resistor (Figure 26). These connections form a gain-of-two, noninverting, amplifier configuration. Overall gain remains one because the resistor string has a divide-by-two configuration. The resistance seen at the VFB pin is approximately 200kΩ to ground. The DAC7551-Q1 output is asynchronously set to zero-scale voltage immediately after the CLR pin is brought low. The CLR signal resets all internal registers and therefore behaves like the Power-On Reset. The DAC7551-Q1 updates at the first rising edge of the SYNC signal that occurs after the CLR pin is brought back to high. Copyright © 2011, Texas Instruments Incorporated IOVDD and Level Shifters The DAC7551-Q1 can be used with different logic families that require a wide range of supply voltages. To enable this useful feature, the IOVDD pin must be connected to the logic supply voltage of the system. All DAC7551-Q1 digital input and output pins are equipped with level-shifter circuits. Level shifters at the input pins ensure that external logic-high voltages are translated to the internal logic-high voltage, with no additional power dissipation. Similarly, the level shifter for the SDO pin translates the internal logic-high voltage (VDD) to the external logic-high level (IOVDD). For single-supply operation, the IOVDD pin can be tied to the VDD pin. 13 DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com SERIAL INTERFACE The DAC7551-Q1 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. 16-Bit Word and Input Shift Register The input shift register is 16 bits wide. DAC data are loaded into the device as a 16-bit word under the control of a serial clock input, SCLK, as shown in Figure 1, the Serial Write Operation timing diagram. The 16-bit word, illustrated in Table 1, consists of four control bits followed by 12 bits of DAC data. The data format is straight binary with all zeroes corresponding to 0V output and all ones corresponding to full-scale output (VREF – 1LSB). Data are loaded MSB first (bit 15) where the first two bits (DB15 and DB14) are don't care bits. Bit 13 and bit 12 (DB13 and DB12) determine either normal mode operation or power-down mode (see Table 1). The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data is shifted into the device input shift register on the falling edges of SCLK for 16 clock pulses. The SPI interface is enabled after SYNC becomes low and the data are continuously shifted into the shift register at each falling edge of SCLK. When SYNC is brought high, the last 16 bits stored in the shift register are latched into the DAC register, and the DAC updates. Daisy-Chain Operation Daisy-chain operation is used for updating serially-connected devices on the rising edge of SYNC. As long as SYNC is high, the SDO pin is in a high-impedance state. When SYNC is brought low the output of the internal shift register is tied to the SDO pin. As long as SYNC is low, SDO duplicates the SDIN signal with a 16-cycle delay. To support multiple devices in a daisy chain, SCLK and SYNC signals are shared across all devices, and SDO of one DAC7551-Q1 should be tied to the SDIN of the next DAC7551-Q1. For n devices in such a daisy chain, 16n SCLK cycles are required to shift the entire input data stream. After 16n SCLK falling edges are received, following a falling SYNC, the data stream becomes complete and SYNC can be brought high to update n devices simultaneously. SDO operation is specified at a maximum SCLK speed of 10MHz. In daisy-chain mode, the use of a weak pull-down resistor on the SDO output pin, which provides the SDIN data for the next device in the chain, is recommended. For standalone operation, the maximum clock speed is 50MHz. For daisy-chain operation, the maximum clock speed is 10MHz. INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7551-Q1 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within ±0.35LSBs, and differential linearity error is typically within ±0.08LSBs. GLITCH ENERGY The DAC7551-Q1 uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches are so low that they are usually buried within the wide-band noise and cannot be easily detected. The DAC7551-Q1 glitch is typically well under 0.1nV-s. Such low glitch energy provides more than a ten-time improvement over industry alternatives. Table 1. Serial Interface Programming CONTROL 14 DATA BITS DB15 DB14 DB13 (PD1) DB12 (PD0) DB11–DB0 X X 0 0 data Normal mode X X 0 1 X Powerdown 1kΩ X X 1 0 X Powerdown 100kΩ X X 1 1 X Powerdown Hi-Z FUNCTION Copyright © 2011, Texas Instruments Incorporated DAC7551-Q1 SLAS767 – JUNE 2011 www.ti.com APPLICATION INFORMATION WAVEFORM GENERATION As a result of the exceptional linearity and low glitch of the DAC7551-Q1, the device is well-suited for waveform generation (from DC to 10kHz). The DAC7551-Q1 large-signal settling time is 5μs, supporting an update rate of 200kSPS. However, the update rates can exceed 1MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, REF3140 (4.096V) or REF02 (5.0V) are recommended for reference voltage generation. GENERATING ±5V, ±10V, AND ±12V OUTPUTS FOR PRECISION INDUSTRIAL CONTROL Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. 1MSPS (small-signal) maximum data update rate, DAC7551-Q1 can support high-speed control loops. Ultralow glitch energy of the DAC7551-Q1 significantly improves loop stability and loop settling time. GENERATING INDUSTRIAL VOLTAGE RANGES For control loop applications, DAC gain and offset errors are not important parameters. This consideration could be exploited to lower trim and calibration costs in a high-voltage control circuit design. Using a quad operational amplifier (OPA4130), and a voltage reference (REF3140), the DAC7551-Q1 can generate the wide voltage swings required by the control loop. Vtail DAC7551 R1 REF3140 Loop Accuracy DAC offset, gain, and the integral linearity errors are not factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step determines the minimum incremental change the loop can generate. A DNL error less than –1LSB (non-monotonicity) can create loop instability. A DNL error greater than +1LSB implies unnecessarily large voltage steps and missed voltage targets. With high DNL errors, the loop loses its stability, resolution, and accuracy. Offering 12-bit ensured monotonicity and ±0.08LSB typical DNL error, DAC755x devices are great choices for precision control loops. Loop Speed Many factors determine the control loop speed, such as ADC conversion time, MCU speed, and DAC settling time. Typically, the ADC conversion time, and the MCU computation time are the two major factors that dominate the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop down only during the start-up. Once the loop reaches its steady-state operation, these errors do not affect loop speed any further. Depending on the ringing characteristics of the loop transfer function, DAC glitches can also slow the loop down. With its R2 VREF VREFH DAC7551 _ Vdac + VOUT OPA4130 Figure 28. Low-cost, Wide-swing Voltage Generator for Control Loop Applications The output voltage of the configuration is given by: ǒ Ǔ ǒ Ǔ V OUT + V REF R2 ) 1 SDIN *V tail R2 4096 R1 R1 (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a single DAC7551-Q1 could be used to set the required offset voltages. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated. One DAC7551-Q1 can provide the Vtail voltages, while four additional DAC7551-Q1 devices can provide Vdac voltages to generate four high-voltage outputs. A single SPI interface is sufficient to control all five DAC7551-Q1 devices in a daisy-chain configuration. For ±5V operation: R1 = 10kΩ, R2 = 15kΩ, Vtail = 3.33V, VREF = 4.096V For ±10V operation: R1 = 10kΩ, R2 = 39kΩ, Vtail = 2.56V, VREF = 4.096V For ±12V operation: R1 = 10kΩ, R2 = 49kΩ, Vtail = 2.45V, VREF = 4.096V Copyright © 2011, Texas Instruments Incorporated 15 PACKAGE OPTION ADDENDUM www.ti.com 27-Jun-2011 PACKAGING INFORMATION Orderable Device DAC7551TDRNRQ1 Status (1) Package Type Package Drawing ACTIVE USON DRN Pins Package Qty 12 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF DAC7551-Q1 : • Catalog: DAC7551 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC7551TDRNRQ1 Package Package Pins Type Drawing USON DRN 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 2.3 B0 (mm) K0 (mm) P1 (mm) 3.3 0.85 4.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7551TDRNRQ1 USON DRN 12 3000 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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