INTEGRATED CIRCUITS 74LVC544A Octal D-type registered transceiver, inverting (3-State) Product specification 1998 Jul 29 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) FEATURES 74LVC544A DESCRIPTION • Wide supply voltage range of 1.2V to 3.6V • In accordance with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • Combines 74LVC640 and 74LVC533 type functions in one chip • Octal transceiver with D-type latch • Back-to-back registers for storage • Separate controls for data flow in each direction • 3-State inverting outputs for bus oriented applications • 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic The 74LVC544A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of the data flow. The ‘544A’ contains eight D-type latches with separate inputs and controls for each set. For data flow from A to B, for example, the A-to-B enable (EAB) input must be LOW in order to enter data from A0–A7 or take data from B0–B7, as indicated in the function table. With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and display the data present at the outputs of the A latches. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL CL = 50pF VCC = 3.3V UNIT tPHL/tPLH Propagation delay An to Bn CI Input capacitance 5.0 pF CI/O Input/output capacitance 10 pF CPD Power dissipation capacitance per latch 30 pF 4 Notes 1, 2 ns NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi Σ (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 24-Pin Plastic SO –40°C to +85°C 74LVC544A D 74LVC544A D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74LVC544A DB 74LVC544A DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC544A PW 7LVC544APW DH SOT355-1 PACKAGES 1998 Jul 29 2 853-2107 19804 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) PIN DESCRIPTION 74LVC544A PIN CONFIGURATION PIN NUMBER SYMBOL FUNCTION 1 LEBA ‘B’ to ‘A’ latch enable input (active LOW) LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 A2 5 20 B2 A3 6 19 B3 18 B4 2 OEBA ‘B’ to ‘A’ output enable input (active LOW) 3, 4, 5, 6, 7, 8, 9, 10 A0–A7 ‘A’ data inputs/outputs 11 EBA ‘B’ to ‘A’ enable input (active LOW) A4 7 12 GND Ground (0V) A5 8 17 B5 A6 9 16 B6 22, 21, 20, 19, 18, 17, 16, 15 B0–B7 ‘B’ data inputs/outputs A7 10 13 OEAB ‘A’ to ‘B’ output enable input (active LOW) 14 LEAB ‘A’ to ‘B’ latch enable input (active LOW) 23 EAB ‘A’ to ‘B’ enable input (active LOW) 24 VCC Positive supply voltage 15 B7 EAB 11 14 LEAB GND 12 13 OEAB SV00733 FUNCTION TABLE INPUTS OUTPUTS STATUS X Z Disabled X Z Disabled L L h l Z Z Disabled + Latch L L ↑ ↑ h l L H Latch + Display L L L L L L H L L H Transparent L L H X NC Hold OEXX XX H L h l X ↑ NC Z EXX LEXX DATA H X X X H X L L ↑ ↑ L L = AB for A-to-B direction, BA for B-to-A direction = HIGH voltage level = LOW voltage level = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA = Don’t care = LOW–to–HIGH level transition = No change = High impedance OFF-state 1998 Jul 29 3 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) LOGIC SYMBOL 74LVC544A LOGIC SYMBOL (IEEE/IEC) 2 23 A0 B0 22 4 A1 B1 21 13 5 A2 B2 20 11 14 3 6 A3 B3 19 7 A4 B4 18 8 A5 B5 17 9 A6 B6 16 A7 B7 15 10 1 3 4 1EN3 G1 1C5 2EN4 G2 2C6 ∇3 5D 6D 4∇ 22 21 5 20 6 19 7 18 8 17 9 16 10 15 2 OEBA 13 OEAB 11 EAB 23 EBA 14 LEAB 1 LEBA SV00735 SV00734 LOGIC DIAGRAM OEBA EBA LEBA OEAB EAB LEAB LE D Bn An LE D 8 IDENTICAL CHANNELS TO 7 OTHER CHANNELS 1998 Jul 29 4 SV00736 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) 74LVC544A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V DC input voltage range 0 5.5 DC output voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI t0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA DC output voltage; output HIGH or LOW Note 2 –0.5 to VCC +0.5 V DC output voltage; output 3-State Note 2 –0.5 to 6.5 V DC output source or sink current VO = 0 to VCC "50 mA "100 mA –65 to +150 °C VO IO IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K 500 above +60°C derate linearly with 5.5 mW/K 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jul 29 5 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) 74LVC544A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*0.8 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA II V 0.55 "0.1 "5 µA VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND 0.1 "5 µA Power off leakage current VCC = 0.0V; VI = 5.5V; VO = 5.5V 0.1 "10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA Input leakage current VCC = 3.6V; VI = 5.5V or GND IOZ 3-State output OFF-state current IOFF ICC ∆ICC UNIT MAX NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V MIN TYP1 MAX MIN MAX UNIT tPHL/tPLH Propagation delay An to Bn, Bn to An Figures 1, 5 1.5 4 6.5 1.5 7.5 ns tPHL/tPLH Propagation delay LEBA to An, LEAB to Bn Figures 2, 5 1.5 4.3 7.5 1.5 8.5 ns tPZH/tPZL 3-State output enable time OEBA to An, OEAB to Bn Figures 3, 5 1.5 4.5 8.5 1.5 9.5 ns tPHZ/tPLZ 3-State output disable time OEBA to An, OEAB to Bn Figures 3, 5 1.5 3.9 6.5 1.5 7.5 ns tPZH/tPZL 3-State output enable time EBA to An, EAB to Bn Figures 3, 5 1.5 4.7 8.9 1.5 9.9 ns tPHZ/tPLZ 3-State output disable time EBA to An, EAB to Bn Figures 3, 5 1.5 3.9 6.9 1.5 7.9 ns tW LEXX pulse width HIGH Figure 2 2.0 – – 2.0 – ns tsu Set-up time An/Bn to LEXX, An/Bn to EXX Figure 4 2.0 – – 2.0 – ns th Hold time An/Bn to LEXX, An/Bn to EXX Figure 4 4.0 – – 1.0 – ns NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jul 29 6 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) 74LVC544A ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ AC WAVEFORMS VM = 1.5V at VCC 2.7V VM = 0.5V * VCC at VCC 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH – 0.3V at VCC 2.7V VY = VOH – 0.1VCC at VCC < 2.7V VI An, Bn INPUT VM GND th th tSU tSU VI LEXX, EXX INPUT VM GND VI An, Bn INPUT NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM SV00739 GND tPHL VOH tPLH Bn, An OUTPUT Figure 4. Data set-up and hold times for the (An, Bn) input to the LEXX and EXX inputs VM TEST CIRCUIT VOL SV00737 PULSE GENERATOR VI LEXX INPUT VM VM S1 VCC Figure 1. Input (An, Bn) to output (Bn, An) propagation delays. VI 2 x VCC Open GND 500Ω VO D.U.T. RT VM 50pF CL 500Ω GND tw tPHL Test tPLH VOH An, Bn OUTPUT VM VM VOL S1 VCC VI tPLH/tPHL Open 2.7V VCC tPLZ/tPZL 2 x VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND SY00003 SV00738 Figure 5. Load circuitry for switching times Figure 2. Latch enable input (LEXX) pulse width, the latch enable input to output (An, Bn) propagation delays. VI OEXX, EXX INPUT VM GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled outputs disabled outputs enabled SW00210 Figure 3. 3-State enable and disable times 1998 Jul 29 7 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Jul 29 8 74LVC544A SOT137-1 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Jul 29 9 74LVC544A SOT340-1 Philips Semiconductors Product specification Octal D-type registered transceiver, inverting (3-State) 74LVC544A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 08-98 9397-750-04512