3D6701 MONOLITHIC CLOCK SYNCHRONIZER (SERIES 3D6701) FEATURES PINOUT Synchronizes free-running clock to external gate signal Input frequency range: 30MHz through 100MHz Phase resolution: 200ps typical Output frequency: Programmable from FIN to FIN/256 Output period jitter: Equal to jitter of clock source All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) VDD 1 16 VDD FOUT 2 15 SEL D0 3 14 D1 D2 4 13 D3 D4 5 12 D5 D6 6 11 D7 GIN 7 10 FIN GND 8 9 GND 3D6701 DIP-16 3D6701R SOIC-16 For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS One major drawback to using a crystal oscillator for frequency generation is that the phase of the generated clock signal cannot be synchronized to an external timing event. A delay-line oscillator (eg, the 3D7701), while supporting this feature, cannot provide the stability and jitter performance of a crystal. The 3D6701 clock synchronizer provides the best of both worlds. The device accepts two inputs – a stable frequency source and a gate signal – and matches the phase of the clock to the gate. It also provides 8 bits of frequency scaling at the device output. The 3D6701 can be operated at 5V or 3.3V, and is offered in both a 16-pin DIP and a space-saving 16-pin SOIC package. FIN Clock Input GIN Gate Input D0-D7 Divisor Inputs SEL VDD Select Input FOUT Sync Oscillator Out VDD +3.3 or +5 Volts GND Ground FIN (Async) GIN DINH TRES OUT (D=0) OUT (D=1) OUT (D=2) Figure 1: Timing Diagram 2014 Data Delay Devices Doc #14015 6/9/2014 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D6701 THEORY OF OPERATION The 3D6701 clock synchronizer architecture is shown in Figure 2. The FIN input is assumed to come from a stable clock source, such as a crystal oscillator. A rising edge on the GIN input initiates the phase detection process. Once the phase of the clock with respect to the gate has been resolved, a delay line is adjusted to match the phases of the two signals. There is a finite resolution to the phase detection process (typically under 500ps), so that, from one gate trigger to the next, there will remain some residual gate-to-output jitter. However, for a given gate, the jitter from one clock cycle to the next is equal to the jitter of the reference clock itself. The 3D6701 also contains a programmable divider that reduces the output frequency by an amount given by the D7:0 inputs. FOUT is given by FIN / (D+1), so that the output frequency may range from FIN (D=0) to FIN / 256 (D=255). When GIN returns low, the output returns to a low level and remains there until the next rising edge of GIN. The performance of CMOS integrated circuits is strongly dependent on power supply stability. It is essential that the power supply pins be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. When operating at 3.3V, tie the SEL input to GND. When operating at 5.0V, tie the SEL input to VDD. GIN Phase Resolver Programmable Delay Line FIN 8-Bit Divider FOUT D7:0 Figure 2: 3D6701 Functional Block Diagram DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature Doc #14015 6/9/2014 SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D6701 DEVICE SPECIFICATIONS (Cont’d) TABLE 2: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current SYMBOL IDD VIH VIL IIH IIL IOH IOL MIN TYP 20.0 MAX UNITS mA V V A A mA mA 2.0 4.0 -35.0 15.0 0.8 1.0 1.0 -4.0 NOTES VIH = VDD VIL = 0V VDD=4.75V, VOH=2.4V VDD=4.75V, VOL=0.4V *IDD will vary slightly for different input clock frequencies TABLE 3: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Input Frequency Duty Cycle Gate Frequency Gate Inactive (Low) Gate-to-Out Delay SYMBOL FIN DC(FIN) GIN GIN,LOW DINH Gate-to-Out Delay Jitter ΔDINH FOUT Period Jitter Reset Time MIN 30 40 TYP MAX 80 60 1 200 157 136 120 420 460 780 50 TRES 10 UNITS MHz % MHz ns ns ns ns ps ps ps ps ns NOTES FIN=50MHz FIN=62MHz FIN=80MHz FIN=50MHz FIN=62MHz FIN=80MHz TABLE 4: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Input Frequency Duty Cycle Gate Frequency Gate Inactive (Low) Gate-to-Out Delay SYMBOL FIN DC(FIN) GIN GIN,LOW DINH Gate-to-Out Delay Jitter ΔDINH FOUT Period Jitter Reset Time Doc #14015 6/9/2014 MIN 50 40 TYP MAX 100 60 2 125 138 118 106 640 700 520 50 TRES 10 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 UNITS MHz % MHz ns ns ns ns ps ps ps ps ns NOTES FIN=50MHz FIN=62MHz FIN=80MHz FIN=50MHz FIN=62MHz FIN=80MHz 3 3D6701 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: o o Ambient Temperature: 25 C 3 C Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6 and 2.4V) OUTPUT: Rload: Cload: Threshold: Device Under Test 10K 10% 5pf 10% 1.5V (Rising & Falling) Digital Scope 10K 5pf 470 NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR GIN FIN OUT TRIG DEVICE UNDER TEST (DUT) FOUT IN TRIG FREQUENCY/ TIME INTERVAL COUNTER FREQ SOURCE Figure 3: Test Setup TRISE TFALL VIH 2.4V 1.5V 0.6V GIN 1/FOSC DINH FOUT 2.4V 1.5V 0.6V 1.5V VIL TRES 1.5V 1.5V Figure 4: Timing Diagram Doc #14015 6/9/2014 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4