3D3250

3D3250
FIXED PULSE-WIDTH 10-TAP
MILLISECOND TIMER
(SERIES 3D3250)
FEATURES
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PINOUT
All-silicon, low-power CMOS technology
CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Timer range: 160ns through 16.0ms
Output Pulse Width: Equal to one clock period
Temperature/Vdd stability: Equal to that of reference clock
Minimum input pulse width: 10.0ns
For mechanical dimensions, click here.
For package marking details, click here.
VDD
1
16
VDDA
T1
2
15
T2
T3
3
14
T4
T5
4
13
T6
T7
5
12
T8
T9
6
11
T10
CK
7
10
TRG
GND
8
9
3D3250-xx
3D3250R-xx
GNDA
DIP-16
SOIC-16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3250 10-tap timer is designed for use in applications that require long
yet very precise time intervals. Upon receipt of a trigger, the device generates
10 pulse outputs, spaced equally in time. The output-to-output time spacing is
equal to the product of the input clock period and the device dash number.
The stability of the timer is thus limited only by the stability of the reference
clock. Each output consists of a pulse whose width is equal to one period of
the reference clock. The 3D3250 is offered in a standard 16-pin autoinsertable DIP and a space saving surface mount 16-pin SOIC package.
TRG
CK
T1-T10
VDD
VDDA
GND
GNDA
Trigger Input
Clock Input
Timer Outputs
+3.3 Volts
+3.3 Volts
Ground
Ground
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3250-5
3D3250-10
3D3250-20
3D3250-25
3D3250-50
3D3250-100
3D3250-200
3D3250-250
3D3250-500
3D3250-1K
3D3250-2K
3D3250-2.5K
3D3250-5K
3D3250-10K
3D3250-20K
3D3250-25K
3D3250-50K
REF CLK =
31.25 MHz
0.160
0.320
0.640
0.800
1.600
3.200
6.400
8.000
16.00
32.00
64.00
80.00
160.0
320.0
640.0
800.0
1600.0
OUTPUT-TO-OUTPUT SPACING (us)
REF CLK =
REF CLK =
REF CLK =
40.00 MHz
50.00 MHz
62.50 MHz
0.250
0.500
0.625
1.250
2.500
5.000
6.250
12.50
25.00
50.00
62.50
125.0
250.0
500.0
625.0
1250.0
0.200
0.400
0.500
1.000
2.000
4.000
5.000
10.00
20.00
40.00
50.00
100.0
200.0
400.0
500.0
1000.0
0.320
0.400
0.800
1.600
3.200
4.000
8.000
16.00
32.00
40.00
80.00
160.0
320.0
400.0
800.0
REF CLK =
80.00 MHz
0.2500
0.3125
0.6250
1.2500
2.5000
3.1250
6.2500
12.500
25.000
31.250
62.500
125.00
250.00
312.50
625.00
NOTE: Any dash number between 5 and 50K not shown is also available as standard.
2014 Data Delay Devices
Doc #14017
6/10/2014
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3250
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3250 timer waveforms are shown in
Figure 1. The device is composed of a number of
timers connected in series. Each timer produces
at its output a signal with a fixed pulse width
(equal to one period of the reference clock),
shifted in time. The timers are matched and
share the same compensation signals, which
minimize output-to-output deviations over
temperature and supply voltage variations.
INPUT TRIGGER CHARACTERISTICS
The period of the input signal (TRG) must be, at a
minimum, 200ns greater than the total time of the
particular device. This determines the highest
input frequency for guaranteed reliable device
operation. The input pulse width must also be
greater or equal to 10ns.
INPUT CLOCK CHARACTERISTICS
The input reference clock frequency determines
the device timing specifications and provides a
very stable reference to the compensation
circuitry to mitigate power supply and
temperature timing variations. The 3D3250
operates with an input reference clock that can
range from 31.25 MHz to 80 MHz. The clock
may run asynchronously with respect to the
trigger input. Table 1 tabulates total delays only at
preselected clock frequencies.
The device total time and the output-to-output
(incremental) times are multiples of the input
clock period as per the following equations:
TI = TCK * DashNumber
TTOTAL = TI * 10
For example, a 3D3250D-250, when operated
with a 40MHz (25ns period) reference clock, will
have an increment of 6.25us (25ns x 250) and a
total time of 62.5us.
CONSIDERATIONS
The device timing accuracy and stability stem
from the frequency source driving the 3D3250
delay line. Therefore, the input clock signal must
have excellent frequency accuracy through power
supply and temperature excursion. More
importantly, a frequency source with the minimum
possible short and long term jitter specifications
should be selected.
The device has two power (VDD & VDDA) and
two ground (GND & GNDA) pins. The VDD and
GND pins power the digital circuitry while the
VDDA and GNDA pins power the analog circuitry
within the device. Bypass of the power pins is
highly recommended, especially the VDDA pin.
High frequency lay-out techniques are
encouraged to be employed.
TTW
TRG
TINC1
TOW
TOTR
T1
TINC
T2
TINC
T3
T10
Figure 1: Timing Diagram
Doc #14017
6/10/2014
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D3250
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
VDD+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
MIN
Low Level Output Current
IOL
4.0
Output Rise & Fall Time
TYP
20
MAX
35
-15.0
0.8
1.0
1.0
-4.0
2.0
TR & TF
15.0
2.0
UNITS
mA
V
V
A
A
mA
mA
2.5
ns
NOTES
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Input Reference Clock
Reference Clock Duty Cycle
Trigger Pulse Width
Output-to-Output Time Delay
Input-to-Output1 Time Delay
Output Pulse Width
Output to Trigger Recovery Time
Output Rise & Fall Time
Doc #14017
6/10/2014
SYMBOL
fCK
DC(fCK)
TTW
TINC
TINC1
TOW
TOTR
TR & TF
MIN
31.25
40
10
TI-1
TI-40
TYP
MAX
80
60
TI+1
TI+40
1
200
2.0
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
2.5
UNITS
MHz
%
ns
ns
ns
TCK
ns
ns
3
3D3250
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
o
o
Ambient Temperature: 25 C  3 C
Supply Voltage (Vcc): 3.3V  0.1V
Input Pulse:
High = 3.0V  0.1V
Low = 0.0V  0.1V
Source Impedance:
50 Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW IN = 1.25 x Total Delay
Period:
PERIN = 2.5 x Total Delay
OUTPUT:
Rload:
Cload:
Threshold:
10K  10%
5pf  10%
1.5V (Rising & Falling)
Device
Under
Test
Digital
Scope
10K
5pf
470
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
PULSE
GENERATOR
TRG
OUT
TRIG
DEVICE UNDER
TEST (DUT)
CK
FREQUENCY
SOURCE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
REF
IN
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
PERIN
PW IN
tRISE
INPUT
SIGNAL
tFALL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
tPLH
OUTPUT
SIGNAL
VIL
tPHL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #14017
6/10/2014
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
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