3D7323 - Data Delay Devices, Inc.

3D7323
MONOLITHIC TRIPLE
FIXED DELAY LINE
(SERIES 3D7323)
FEATURES
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PACKAGES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range: 6 through 6000ns
Delay tolerance: 2% or 1.0ns
Temperature stability: ±3% typ (-40C to 85C)
Vdd stability: ±1% typical (4.75V to 5.25V)
Minimum input pulse width: 20% of total delay
I1
I2
I3
GND
1
2
3
4
8
7
6
5
VDD
O1
O2
O3
3D7323Z SOIC
(150 Mil)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7323 Triple Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains three matched,
independent delay lines. Delay values can range from 6ns through
6000ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D7323
is TTL- and CMOS-compatible, capable of driving ten 74LS-type
loads, and features both rising- and falling-edge accuracy.
I1
I2
I3
O1
O2
O3
VDD
GND
N/C
The all-CMOS 3D7323 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a space saving surface mount 8-pin SOIC.
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
+5 Volts
Ground
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
3D7323Z-6
3D7323Z-8
3D7323Z-10
3D7323Z-15
3D7323Z-20
3D7323Z-25
3D7323Z-30
3D7323Z-40
3D7323Z-50
3D7323Z-100
3D7323Z-200
3D7323Z-500
3D7323Z-1000
3D7323Z-2000
3D7323Z-5000
3D7323Z-6000
DELAY
PER LINE
(ns)
6 ± 1.0
8 ± 1.0
10 ± 1.0
15 ± 1.0
20 ± 1.0
25 ± 1.0
30 ± 1.0
40 ± 1.0
50 ± 1.0
100 ± 2.0
200 ± 4.0
500 ± 10.0
1000 ± 20
2000 ± 40
5000 ± 100
6000 ± 120
Max Operating
Frequency
55.5 MHz
41.6 MHz
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
0.67 MHz
0.33 MHz
0.17 MHz
0.07 MHz
0.05 MHz
INPUT RESTRICTIONS
Absolute Max
Min Operating
Oper. Freq.
Pulse Width
125.0 MHz
9.0 ns
111.0 MHz
12.0 ns
100.0 MHz
15.0 ns
100.0 MHz
22.5 ns
100.0 MHz
30.0 ns
83.3 MHz
37.5 ns
71.4 MHz
45.0 ns
62.5 MHz
60.0 ns
50.0 MHz
75.0 ns
25.0 MHz
150.0 ns
12.5 MHz
300.0 ns
5.00 MHz
750.0 ns
2.50 MHz
1500.0 ns
1.25 MHz
3000.0 ns
0.50 MHz
7500.0 ns
0.42 MHz
9000.0 ns
NOTE: Any delay between 10 and 6000 ns not shown is also available.
Doc #06015
6/25/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
Absolute Min
Oper. P.W.
4.0 ns
4.5 ns
5.0 ns
5.0 ns
5.0 ns
6.0 ns
7.0 ns
8.0 ns
10.0 ns
20.0 ns
40.0 ns
100.0 ns
200.0 ns
400.0 ns
1000.0 ns
1200.0 ns
2007 Data Delay Devices
1
3D7323
APPLICATION NOTES
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7323 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATIONAL DESCRIPTION
The 3D7323 triple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
OPERATING FREQUENCY
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7323 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
VDD
Temp & VDD
Compensation
GND
O1
O2
O3
Delay
Line
Delay
Line
Delay
Line
I1
I2
I3
Figure 1: 3D7323 Functional Diagram
Doc #06015
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7323
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7323 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 300
PPM/C, which is equivalent to a variation , over
the -40C to 85C operating range, of ±3% from
the room-temperature delay settings and/or
1.0ns, whichever is greater. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to ±1% of the delay settings at
the nominal 5.0VDC power supply and/or 2.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
VDD+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
MIN
Low Level Output Current
IOL
4.0
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = 3 * CLD * VDD * F
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
Doc #06015
6/25/2007
MAX
5
2.0
-1
-1
0.8
1
1
-4.0
UNITS
mA
V
V
µA
µA
mA
mA
2
ns
NOTES
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7323
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.25 x Total Delay
Period:
PERIN = 2.5 x Total Delay
OUTPUT:
Rload:
Cload:
Threshold:
10KΩ ± 10%
5pf ± 10%
1.5V (Rising & Falling)
Device
Under
Test
Digital
Scope
10KΩ
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
TRIG
IN
OUT1
OUT2
OUT3
IN1 DEVICE UNDER
TEST (DUT)
IN2
IN3
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
PERIN
PW IN
tRISE
INPUT
SIGNAL
tFALL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
tPLH
OUTPUT
SIGNAL
VIL
tPHL
1.5V
VOH
1.5V
VOL
Figure 3: Timing Diagram
Doc #06015
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4