74LVC573A OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS A Pin Assignments The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features Supply Voltage Range from 1.65V to 3.6V Sinks or Sources 24mA at VCC = 3V CMOS Low Power Consumption IOFF Supports Partial-Power Down Operation Inputs or Outputs Accept Up to 5.5V Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications Schmitt Trigger Action at All Inputs Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V with VCC = 3.3V and TA = +25°C Typical VOHV (Quiet Output Dynamic VOH) Greater than 2.0V with VCC = 3.3V and TA = +25°C Vcc D1 2 19 Q1 D2 3 18 Q2 D3 4 17 Q3 D4 5 16 Q4 D4 D5 6 15 Q5 7 14 Q6 D7 8 13 Q7 D8 9 12 Q8 10 11 LE GND TSSOP-20 2 19 Q1 D2 D3 3 18 Q2 4 17 Q3 5 16 Q4 D5 6 15 Q5 D6 7 14 Q6 D7 8 13 Q7 D8 9 12 Q8 11 D6 D1 OE 20 Vcc 1 1 OE 20 (Top Transparent View ) terminal index 1 area 10 These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. The device is designed for operation with a power supply range of 1.65V to 3.6V. (Top View ) LE The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. GND NEW PRODUCT Description V-QFN4525-20 Applications General Purpose Logic Bus Driving Power Down Signal Isolation Wide Array of Products such as: PCs, Notebooks, Netbooks, Ultrabooks Networking Computer Peripherals, Hard Drives, CD/DVD ROM TV, DVD, DVR, Set Top Box ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115) Exceeds 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101) Latch-Up Exceeds 250mA per JESD 78, Class I All devices are: Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free, "Green" and Lead-Free. 3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. 74LVC573A Document number: DS35897 Rev. 2 - 2 1 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A A Ordering Information 74 LVC NEW PRODUCT Logic Device 74 : Logic Prefix LVC : Low Voltage CMOS 573A : Octal Transparent DType Latch with 3-State Outputs Package Packing T20 : TSSOP-20 Q20 : V-QFN4525-20 -13 : 13” Tape & Reel 13” Tape and Reel Quantity Part Number Suffix Package Size Package Code Package (Notes 4 & 5) 74LVC573AT20-13 T20 TSSOP-20 74LVC573AQ20-13 Q20 V-QFN4525-20 6.4mm X 6.5mm X 1.2mm 0.65mm Lead Pitch 2.5mm X 4.5mm X 0.95mm 0.50mm Lead Pitch 2500/Tape & Reel -13 2500/Tape & Reel -13 4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 5. V-QFN4525-20 is a JEDEC recognized naming convention that specifies the package thickness category as V and the number 4525 describes the package as 4.5mm X 2.5mm. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 XXX -13 Function Part Number Notes: 573A Pin Name OE D1 D2 D3 D4 D5 D6 D7 D8 GND LE Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 VCC Description Output Enable Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Ground Latch Enable Latch Output Latch Output Latch Output Latch Output Latch Output Latch Output Latch Output Latch Output Supply Voltage Logic Diagram 1 OE LE D1 Function Table (Each Latch) INPUTS 2 D Q 19 Q1 C D2 3 D Q 18 Q2 C D3 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z 11 4 D Q 17 Q3 C D4 5 D Q 16 Q4 C D5 6 D Q 15 Q5 C D6 7 D Q 14 Q6 C D7 8 D Q 13 Q7 C D8 9 D Q 12 Q8 C 74LVC573A Document number: DS35897 Rev. 2 - 2 2 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A Absolute Maximum Ratings (Notes 6 & 7) Symbol ESD HBM ESD CDM ESD MM NEW PRODUCT VCC A Description Human Body Model ESD Protection Charged Device Model ESD Protection Machine Model ESD Protection Rating 2 1 200 Unit kV kV V Supply Voltage Range -0.5 to +7.0 V -0.5 to +7.0 V -20 mA VI Input Voltage Range IIK Input Clamp Current VI < 0V IOK Output Clamp Current VO < 0V -50 mA IO Continuous Output Current -0.5V < VO VCC +0.5V ±50 mA ICC Continuous Current Through VCC 100 mA IGND Continuous Current Through GND -100 mA Operating Junction Temperature -40 to +150 °C TSTG Storage Temperature -65 to +150 °C PTOT Total Power Dissipation 500 mW TJ Notes: 6. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be within recommend values. 7. Forcing the maximum allowed voltage could cause a condition exceeding the maximum current or conversely forcing the maximum current could cause a condition exceeding the maximum voltage. The ratings of both current and voltage must be maintained within the controlled range. Recommended Operating Conditions (Note 8) Symbol VI Input Voltage Conditions Operating Data Retention Only — 0 5.5 V VO Output Voltage — 0 VCC V VCC = 1.65V — -4 VCC = 2.3V — -8 VCC = 2.7V — -12 VCC = 3.0V — -24 VCC = 1.65V — 4 VCC = 2.3V — 8 VCC = 2.7V — 12 VCC = 3.0V — — — 24 VCC IOH IOL Parameter Supply Voltage High-Level Output Current Low-Level Output Current Δt/ΔV Input Transition Rise or Fall Rate TA Operating Free-Air Temperature Note: Min 1.65 1.5 Max 3.6 — Unit V V mA mA — 10 ns/V -40 +125 °C 8. Unused inputs should be held at VCC or Ground. 74LVC573A Document number: DS35897 Rev. 2 - 2 3 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A Electrical Characteristics NEW PRODUCT Symbol Parameter — — VCC X 0.35 0.7 0.8 VCC-0.2 — VCC-0.3 — 1.2 — 1.05 — 2.3V 1.7 — 1.65 — 2.7V 3.0V 2.2 2.4 — — 2.05 2.48 — — IOH = -24mA 3.0V 2.3 — 2.0 — IOL = 100μA 1.65V to 3.6V — 0.2 — 0.3 IOL = 4mA Low-Level Output IOL = 8mA Voltage IOL = 12mA 1.65V — 0.45 — 0.65 2.3V — 0.60 — 0.80 2.7V — 0.40 — 0.60 IOL = 24mA 3.0V — 0.55 — 0.80 IOFF 0V — ±10 — 20 μA II VI = GND or 5.5V 0 to 3.6V — ±5 — ±20 μA IOZ VI = GND or 5.5V VO = 0 to 5.5V 3.6V — ±5 — ±20 µA ICC 3.6V — 10 — 40 μA ∆ICC 2.7V to 3.6V — 500 — 5000 μA CI High-Level Output Voltage Power Down Leakage Current Input Current Control Pins Z-State Current Including Input Current I/O Pins — 2.3V to 2.7V 3.0V to 3.6V VCC X 0.65 1.7 2 — — — 1.65V to 1.95V — — — 2.3V to 2.7V 3.0V to 3.6V — — IOH = -50μA 1.65V to 3.6V IOH = -4mA 1.65V IOH = -8mA IOH = -12mA Unit — Low-Level Input Voltage 1.65V to 1.95V TA = -40°C to +125°C Min Max VCC X 0.35 0.7 0.8 VIL — TA = -40°C to +85°C Min Max — High-Level Input Voltage VOL VCC VCC X 0.65 1.7 2 VIH VOH Test Conditions A VI or VO = 0 or 5.5V Supply Current VI = GND or VCC, IO = 0 Additional Supply One Input at VCC -0.6V IO = 0A Current Control Pins Input VI = GND or VCC Capacitance I/O Pins 74LVC573A Document number: DS35897 Rev. 2 - 2 0V to 3.6V 4 of 11 www.diodes.com — — 4.0 Typical 5.5 Typical — — 4.0 Typical 5.5 Typical V V V V pF May 2015 © Diodes Incorporated 74LVC573A Switching Characteristics NEW PRODUCT Symbol Parameter Test Conditions tW Pulse Width LE Figure 1 tSU Set-up Time DN to LE Figure 1 tH Hold Time DN to LE Figure 1 tPD Propagation Delay DN to QN Figure 1 tPD Propagation Delay LE to QN Figure 1 tEN Enable Time to QN OE Figure 1 tDIS Disable Time to QN OE Figure 1 tDIS Disable Time to QN OE Figure 1 tsk(0) A — Output Skew Time 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 1.8V ± 0.15V 2.5V ± 0.2V 2.7V 3.3V ± 0.3V 3.3V ± 0.3V TA = -40°C to +85°C TA = +25°C VCC Min 5.0 4.0 3.0 3.0 4.0 3.0 2.0 2.0 3.0 2.0 1.5 1.5 1 1 1 1.5 1 1 1 1.5 1 1 1 1.7 1 1 1 1.7 1 1 1 1.7 — Typ 2.5 2.0 1.7 1.5 2.0 1.5 1.0 1.0 1.5 1.0 1.0 1.0 6 3.9 4.2 3.8 7 4.5 5.4 4.4 7.8 4 4.4 4.1 7.8 4 4.4 4.1 7.8 4 4.4 4.1 — Max — — — — — — — — — — — — 12.2 7.8 7.8 6.8 14.8 10 8.2 7.2 16.5 9 8.3 7.3 16.5 9 8.3 7.3 16.5 9 8.3 7.3 1.0 Min 5.0 4.0 3.0 3.0 4.0 3.0 2.0 2.0 3.0 2.0 1.5 1.5 1 1 1 1.5 1 1 1 1.5 1 1 1 1.7 1 1 1 1.7 1 1 1 1.7 — Max — — — — — — — — — — — — 12.7 8.3 8.1 7.4 15.3 10.5 9.5 8.5 17 9.5 8.5 7.5 17 9.5 8.5 7.5 17 9.5 8.5 7.5 — TA = -40°C to +125°C Min 5.5 4.5 3.5 3.5 4.5 3.5 2.5 2.5 3.5 2.5 2.0 2.0 1 1 1 1.5 1 1 1 1.5 1 1 1 1.7 1 1 1 1.7 1 1 1 1.7 — Unit Max — — — — — — — — — — — — 16.9 8.7 9.5 8 22.5 12.4 12 11 18.7 10.3 9.5 9 18.4 10.5 9.1 9 18.4 10.5 9.1 9 1.5 ns ns ns ns ns ns ns ns ns Operating Characteristics TA = +25°C Symbol CPD Parameter Power Dissipation Capacitance per Gate 74LVC573A Document number: DS35897 Rev. 2 - 2 Test Conditions f = 10MHz Outputs Enabled 5 of 11 www.diodes.com VCC Typ Unit 1.8V ± 0.15V 2.5V ± 0.2V 3.3V ± 0.3V 9.9 10.2 10.6 pF May 2015 © Diodes Incorporated 74LVC573A A Package Characteristics Symbol θJA NEW PRODUCT θJC θJA θJC Note: Parameter Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case Package Test Conditions Min Typ Max Unit TSSOP-20 (Note 9) — 74 — °C/W TSSOP-20 (Note 9) — 15 — °C/W V-QFN4525-20 (Note 9) — 67 — °C/W V-QFN4525-20 (Note 9) — 20 — °C/W 9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout per JESD 51-7. 74LVC573A Document number: DS35897 Rev. 2 - 2 6 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A A Parameter Measurement Information RL NEW PRODUCT From Output Under Test CL S1 VLOAD Open GND RL (see Note A) Inputs VCC 1.8V ± 0.15V TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND VM VLOAD CL RL V∆ ≤2ns VCC/2 2 x VCC 30pF 1KΩ 0.15V VI tr/tf VCC 2.5V ± 0.2V VCC ≤2ns VCC/2 2 x VCC 30pF 500Ω 0.15V 2.7V 2.7V ≤2.5ns 1.5V 6V 50pF 500Ω 0.3V 3.3V ± 0.3V 2.7V ≤2.5ns 1.5V 6V 50pF 500Ω 0.3V tW Vl Input VM VM 0V Voltage Waveform Pulse Duration Output Waveform 1 S1 at VLOAD (see Note B) Vl Input VM VM Output Waveform 2 S1 at GND (see Note B) 0V tPLH tPHL VOH Output VM Vl Output Control VM VM 0V tPZL tPLZ VLOAD/2 VM VOL + V VOL tPHZ tPZH VM VOH - V VOH ≈ 0V VM VOL tPHL Voltage Waveform Enable and Disable Times Low and High Level Enabling tPLH VOH Output VM VM VOL Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10MHz. C. Inputs are measured separately one transition per measurement. D. tPLZ and tPHZ are the same as tDIS. E. tPZL and tPZH are the same as tEN0 F. tPLH and tPHL are the same as tPD. Figure 1 Load Circuit and Voltage Waveforms 74LVC573A Document number: DS35897 Rev. 2 - 2 7 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A Marking Information (1) A TSSOP-20 ( Top View ) NEW PRODUCT 14 20 11 8 YY : Year : 08, 09,10~ WW : Week : 01~52; 52 Logo 74LVC573A Part Number represents 52 and 53 week X X : Internal Codes YY WW X X 1 7 10 7 Part Number 74LVC573AT20 (2) Package TSSOP-20 V-QFN4525-20 ( Top View ) YY : Year : 08, 09,10~ WW : Week : 01~52; 52 Logo Part Number 74LVC573A represents 52 and 53 week X X : Internal Codes YY WW X X terminal 1 index area Part Number 74LVC573AQ20 74LVC573A Document number: DS35897 Rev. 2 - 2 Package V-QFN4525-20 8 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A Package Outline Dimensions A Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version. (1) Package Type: TSSOP-20 NEW PRODUCT D E1 E 0.25 Gauge Plane PIN 1 ID MARK Seating Plane e L DETAIL L1 A2 b (2) A TSSOP-20 Dim Min Max Typ A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 6.50 E 6.20 6.60 6.40 E1 4.30 4.50 4.40 e 0.65 BSC L 0.45 0.75 0.60 L1 1.0 REF θ1 0° 8° θ2 10° 14° 12° θ3 10° 14° 12° All Dimensions in mm A1 Package Type: V-QFN4525-20 A1 A A3 Seating Plane (Pin #1 ID) D e Z1 E E2 D2 L Z 74LVC573A Document number: DS35897 Rev. 2 - 2 V-QFN4525-20 Dim Min Max Typ A 0.75 0.85 0.80 A1 0.00 0.05 0.02 A3 0.15 b 0.18 0.30 0.23 D 4.45 4.55 4.50 D2 2.85 3.15 3.00 E 2.45 2.55 2.50 E2 0.85 1.15 1.00 e 0.50BSC L 0.30 0.50 0.40 Z 0.385 Z1 0.885 All Dimensions in mm b 9 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A Suggested Pad Layout A Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version. (1) Package Type: TSSOP-20 X (20x) NEW PRODUCT C Y1 Dimensions C X X1 Y Y1 Y2 Y2 Y (20x) Value (in mm) 0.650 0.420 6.270 1.780 4.160 7.720 X1 (2) Package Type: V-QFN4525-20 X4 X3 X1 X2 Y3 Y1 Y2 Y X 74LVC573A Document number: DS35897 Rev. 2 - 2 Dimensions C X X1 X2 X3 X4 Y Y1 Y2 Y3 Value (in mm) 0.500 0.330 0.600 3.200 3.830 4.800 0.600 1.200 0.830 2.800 C 10 of 11 www.diodes.com May 2015 © Diodes Incorporated 74LVC573A IMPORTANT NOTICE A NEW PRODUCT DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. 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