A Product Line of
Diodes Incorporated
AP3595
DUAL PHASE SYNCHRONOUS RECTIFIED BUCK CONTROLLER
Description
Pin Assignments
The AP3595 is a compact dual phase synchronous rectified buck
controller specifically designed to deliver high quality output voltage.
This device operates at adjustable operation frequency and is
capable of delivering up to 60A output current.
(Top View)
BOOT2
HG2
PHASE2
LG2
The AP3595 features configurable gate driving voltage for maximum
efficiency and optimal performance. The built-in bootstrap diode
simplifies the circuit design and reduces external part count and PCB
space. The output voltage is precisely regulated to the reference input
that is dynamically adjustable by external voltage divider.
VID
This controller integrates internal MOSFET drivers that support
12V+12V bootstrapped voltage for high efficiency power conversion.
The bootstrap diode is built-in to simplify the circuit design and
minimize external part count.
RSET
Pin 1 Mark
24
23
22
21
20
19
REFIN
1
18
VREF
2
17 PVCC
RT/EN
3
IOFS
4
COMP
FB
16
LG1
15
PHASE1
5
14
HG1
6
13 BOOT1
EP
Other features include adjustable soft start, adjustable operation
frequency, and quick response to step-load transient. With aforementioned functions, the IC provides customers a compact, high
efficiency, well-protected and cost-effective solution.
7
8
9
10
11
12
FBRTN
EAP
SS
CSN
CSP
PSI
This IC is available in U-QFN4040-24 package.
U-QFN4040-24 (FN Package)
Features
Applications
Operate with Single Supply Voltage
Simple Single Loop Voltage Mode Control
12V+12V Bootstrapped Drivers with Internal Bootstrap Diode
Adjustable Over Current Protection by DCR
Current Sensing
Adjustable Current Balancing by RDS(ON) Current Sensing
Adjustable Operation Frequency from 50kHz to 1MHz Per Phase
External Compensation
Dynamic Output Voltage Adjustment
Adjustable Soft Start
U-QFN4040-24 Package
RoHS Compliant and 100% Lead (Pb)-free
Totally Lead-free & Fully RoHS Compliant (Note1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
VCC
Middle-High End GPU Core Power
High End Desktop PC Memory Core Power
Low Output Voltage, High Power Density
DC-DC Converters
Voltage Regulator Modules
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
AP3595
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AP3595
Typical Applications Circuit
VIN
18
PHASE2
17
PHASE1
11
VOUT
PVCC
VCC
BOOT1
CSP
HG1
10
12
4
2
CSN
13
14
PHASE1 15
VOUT
PSI
LG1 16
IOFS
BOOT2 22
VREF
HG2 21
1
24
FBRTN
9
8
23
3
REFIN
RSET
AP3595
PHASE2
20
LG2 19
SS
EAP
FBRTN
7
VID
RT/EN
FB
COMP
6
5
GND
AP3595
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AP3595
Pin Descriptions
Pin Number
Pin Name
Function
External Reference Input. This is the input pin of external reference voltage. Connect a voltage
divider from VREF to REFIN and FBRTN to set the reference voltage
Output for Reference Voltage. This is the output pin of high precision 2V reference voltage.
Bypass this pin with a 1F ceramic capacitor to FBRTN
Operation Frequency Setting. Connecting a resistor between this pin and GND to set the
operation frequency. Pull this pin to ground to shut down the AP3595
Current Balance Adjustment. Connect a resistor from this pin to VREF or GND to adjust the
current sharing
Error Amplifier Output. This is the output of the error amplifier (EA) and the non-inverting input
of the PWM comparators. Use this pin in combination with the FB pin to compensate the
voltage control feedback loop of the converter
Feedback Voltage. This pin is the inverting input to the error amplifier. Use this pin in
combination with the COMP pin to compensate the voltage control feedback loop of the
converter
1
REFIN
2
VREF
3
RT/EN
4
IOFS
5
COMP
6
FB
7
FBRTN
8
EAP
9
SS
10
CSN
Negative Input for Current Sensing Amplifier
11
CSP
Positive Input for Current Sensing Amplifier
12
PSI
13
BOOT1
14
HG1
15
PHASE1
16
LG1
17
PVCC
18
VCC
19
LG2
20
PHASE2
21
HG2
22
BOOT2
23
VID
24
RSET
Exposed Pad
GND
AP3595
Document number: DS36749 Rev. 1 - 2
Feedback Return. Connect this pin to the ground where the output voltage is to be regulated
Non-inverting Input of Error Amplifier. Connect a resistor from this pin to SS pin to set the
droop slope
Soft Start Output. Connect a capacitor to FBRTN to set the soft start interval
Power Saving Mode. Connect this pin to VREF for always two phase operation. Short this pin
to ground for always single phase operation
Bootstrap Supply for the Floating Upper Gate Driver of Channel 1. Connect a bootstrap
capacitor between BOOT1 pin and the PHASE1 pin to form a bootstrap circuit
Upper Gate Driver Output for Channel 1. Connect this pin to the gate of upper MOSFET. This
pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper
MOSFET has turned off
Switch Node for Channel 1. Connect this pin to the source of the upper MOSFET and the drain
of the lower MOSFET. This pin is used as the sink for the Upper GATE driver. It is also
monitored by the adaptive shoot-through protection circuitry to determine when the upper
MOSFET has turned off
Lower Gate Driver Output for Channel 1. Connect this pin to the gate of lower MOSFET. This
pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET has turned off
Supply Voltage for Gate Driver. This pin is the output of internal 9V LDO. This pin provides
current for gate drivers. Bypass this pin with a minimum 1F ceramic capacitor
Supply Voltage. This pin provides current for internal control circuit and 9V LDO. Bypass this
pin with a minimum 1F ceramic capacitor next to the IC
Lower Gate Driver Output for Channel 2. Connect this pin to the gate of lower MOSFET. This
pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET has turned off
Switch Node for Channel 2. Connect this pin to the source of the upper MOSFET and the drain
of the lower MOSFET. This pin is used as the sink for the HG2 driver. It is also monitored by
the adaptive shoot-through protection circuitry to determine when the upper MOSFET has
turned off
Upper Gate Driver Output for Channel 2. Connect this pin to the gate of upper MOSFET. This
pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper
MOSFET has turned off
Bootstrap Supply for the Floating Upper Gate Driver of Channel 2. Connect a bootstrap
capacitor between BOOT2 pin and the PHASE2 pin to form a bootstrap circuit
VID Input. This pin is used to adjust the reference voltage. Logic high enables the internal
MOSFET connected to RSET pin
Reference Voltage Setting. This pin is an open drain output that is pulled low when VID sets to
high. Connect a resistor from this pin to REFIN pin to set the reference voltage
Power Ground. Tie this pin to the ground island/plane through the lowest available impedance
connection
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AP3595
Functional Block Diagram
VCC IOFS
18
VREF
RSET
VID
FBRTN
REFIN
SS
EAP
FB
COMP
Reference
Voltage
2
17
Internal
Regulator
POR
13
14
Gate
Control
Logic
7
PHASE1
Current
Balance
1
15
PHASE2
16
9
8
6
+
-
DUAL PHASE
Control
+
Error
Amplifier
PWM
-
22
HG1
PHASE1
LG1
BOOT2
5
21
10
11
-
SS
+
Gate
Control
Logic
OCP
OVP
UVP
20
19
PSI
BOOT1
24
23
FB
CSN
CSP
PVCC
4
12
HG2
PHASE2
LG2
Oscillator
Power Saving
Setting
3
RT/EN
Absolute Maximum Ratings(Note 4)
Symbol
VCC
VPHASE
Parameter
HG to PHASE Voltage
VLG
LG to GND Voltage
VBOOT
-0.3 to 15
-5 to 30
DC
-0.3 to VBOOT-PHASE+0.3
-5 to VBOOT-PHASE+5
DC
-0.3 to VCC+0.3
<200ns
-5 to VCC+5
15
BOOT to GND Voltage
JA
Thermal Resistance (Junction to Ambient)
Storage Temperature Range
Junction Temperature
V
V
V
-0.3 to VPHASE+15
-0.3 to 42
<200ns
Power Dissipation
V
<200ns
DC
Input, Output or I/O Voltage
TJ
V
DC
<200ns
BOOT to PHASE Voltage
PD
TSTG
Unit
-0.3 to 15
PHASE to GND Voltage
VHG
–
Rating
Supply Input Voltage
V
-0.3 to 6
V
2.5
W
40
°C/W
-65 to +150
+150
ºC
ºC
TLEAD
Lead Temperature (Soldering, 10sec)
+260
ºC
VHBM
ESD (Human Body Model)
2000
V
VMM
ESD (Machine Model)
200
V
Note 4: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied.
Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.
AP3595
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AP3595
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Unit
Supply Input Voltage
10.8
13.2
V
TA
Operating Ambient Temperature
-40
+85
°C
TJ
Operating Junction Temperature
-40
+125
°C
VCC
Electrical Characteristics
Symbol
(@VCC=12V, TA=+25C, unless otherwise specified.)
Parameter
Conditions
Min
Typ
Max
Unit
–
SUPPLY INPUT
VCC
Supply Input Voltage
ICC
Supply Current
HG and LG Open, VCC=12V,
Switching
IQ
10.8
–
13.2
V
–
5
–
mA
Quiescent Current
No Switching, IPCC=0mA
–
4
–
mA
VPCC
Regulated Supply Voltage
RT/EN=0V, IPCC=0mA
8
9
10
V
VRTH
POR Threshold
–
8
9
10
V
VHYS
POR Hysteresis
–
–
1
–
V
100
150
200
A
–
1
–
V
CHIP ENABLE/FREQUENCY SETTING
IRT/EN
RT/EN Sourcing Current
VRT/EN=GND
VRT/EN
RT/EN Voltage
RRT=33kΩ
–
–
50
–
1000
kHz
RRT=33kΩ
270
300
330
kHz
fOSC=200kHz to 500kHz
-15
–
15
%
Switching Frequency Setting Range
fOSC
Free Run Switching Frequency
△ fOSC
Switching Frequency Accuracy
OSCILLATOR
–
Maximum Duty Cycle
–
–
40
–
%
–
Minimum Duty Cycle
–
–
0
–
%
VCC=12V
–
3.5
–
V
VPSI rising
1.2
–
–
V
VPSI falling
–
–
0.4
V
Reference Voltage Accuracy
IREF=100A
1.98
2.0
2.02
V
Reference Voltage Load Regulation
IREF=0 to 2mA
-5
–
5
mV
Output Voltage Accuracy
|VREFIN-VFB|, VCC=12V, No Load,
RDRP=0, VREFIN=0.8V to 1.6V
–
–
5
mV
Open Loop DC Gain
Guaranteed by design
70
80
–
dB
GBW
Gain Bandwidth Product
CLOAD=5pF, Guaranteed by design
–
20
–
MHz
SR
Slew Rate
Guaranteed by design
15
20
–
V/s
Maximum Current (Sink and Source)
VCOMP=1.6V
1.5
2.0
–
mA
VOSC
Ramp Amplitude
POWER SAVING MODE
VPSI_H
VPSI_L
Threshold Voltage for Entering Dual
Phase
Threshold Voltage for Entering
Single Phase
REFERENCE VOLTAGE
VREF
△ VREF
△ VFB
ERROR AMPLIFIER
AO
ICOMP
AP3595
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AP3595
Electrical Characteristics
Symbol
(Cont.) (@VCC=12V, TA=+25C, unless otherwise specified.)
Parameter
Conditions
Min
Typ
Max
Unit
SOFT START
ISS
ISS_CC
Soft Start Current
During soft start
–
22
–
A
Supply Current
After soft start end
–
200
–
A
TOTAL CURRENT SENSE
ICSN_MAX
Maximum Sourcing Current
–
100
–
–
A
–
GM Amplifier Offset Voltage
–
-5
0
5
mV
ICSN_OCP
Over Current Protection Threshold
–
–
60
–
A
IDRP/ICSN
Droop Accuracy
–
90
100
110
%
IPSI/ICSN
PSI Accuracy
–
90
100
110
%
–
mS
PHASE CURRENT SENSE
–
VOFS
–
1.0
–
100kfrom IOFS to VREF
–
1.5
–
100kfrom IOFS to GND
–
0.5
–
Trans-conductance
IOFS Voltage
V
VID CONTROL INPUT
VIH
Logic High Threshold Level
–
1.2
–
–
V
VIL
Logic Low Threshold Level
–
–
–
0.4
V
RRSET
On Resistance of RSET MOSFET
VID=High
–
20
–
IRSET
Leakage Current of RSET Pin
VRSET=2V, VID=0V
–
–
0.1
A
IHG_SRC
Upper Gate Sourcing Current
VBOOT-VPHASE=6V
–
1.2
–
A
RHG_SNK
Upper Gate Sinking Resistance
IHG=100mA sinking
–
1.5
3
ILG_SRC
Lower Gate Sourcing Current
VPCC-VLG=6V
–
1.2
–
A
RLG_SNK
Lower Gate Sinking Resistance
ILG=100mA sinking
–
1
2
50
–
ns
GATE DRIVER
Dead Time
–
–
VFB-VSS
Over Voltage Protection
–
–
300
–
mV
VFB-VSS
Under Voltage Protection
–
–
-300
–
mV
–
Over Temperature Protection
–
–
+150
–
°C
–
Over Temperature Hysteresis
–
–
+20
–
°C
tDT
PROTECTION
AP3595
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AP3595
Performance Characteristics
VREF Line Regulation
VREF Load Regulation
2.000
2.000
1.998
1.998
1.996
1.996
1.994
1.994
ILOAD=0mA
ILOAD=2mA
1.990
1.992
VREF (V)
VREF (V)
1.992
1.988
1.990
1.988
1.986
1.986
1.984
1.984
1.982
1.982
1.980
4
6
8
10
12
14
1.980
0
5
VCC (V)
10
15
20
ILOAD (mA)
VPCC Load Regulation
VPCC Line Regulation
9.10
9
9.05
8
VPCC (V)
VPCC (V)
ILOAD=0mA
ILOAD=10mA
7
9.00
8.95
6
5
8.90
4
8.85
0
20
40
60
80
3
100
4
6
ILOAD (mA)
8
10
12
14
VIN (V)
ICC vs.VIN
fOSC vs.VIN
310
6.4
308
6.2
306
6.0
304
5.8
fOSC (kHz)
ICC (mA)
302
5.6
5.4
5.2
300
298
296
5.0
294
4.8
292
4.6
9
10
11
12
13
14
290
9
VIN (V)
AP3595
Document number: DS36749 Rev. 1 - 2
10
11
12
13
14
VIN (V)
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AP3595
Performance Characteristics (Cont.)
fOSC vs. RRT
VPCC vs. Temperature
1000
9.10
9.08
9.04
VPCC (V)
fOSC (kHz)
9.06
100
9.02
ILOAD=0mA
ILOAD=10mA
9.00
8.98
10
10
8.96
-40
100
-20
0
20
RRT (k)
1.998
308
1.996
306
1.994
304
1.992
302
fOSC (kHz)
VREF (V)
310
1.990
1.988
1.984
294
1.982
292
40
60
80
100
120
140
290
-40
o
-20
0
20
40
60
80
100
120
140
Temperature ( C)
Power On Waveforms
Power Off Waveforms
VPHASE1
10V/div
VPHASE1
10V/div
VRT/EN
1V/div
VOUT
1V/div
VSS
1V/div
VRT/EN
1V/div
VOUT
1V/div
VSS
1V/div
Time 4ms/div
Document number: DS36749 Rev. 1 - 2
140
o
Temperature ( C)
AP3595
120
298
296
20
100
300
1.986
0
80
fOSC vs. Temperature
2.000
-20
60
o
VREF vs. Temperature
1.980
-40
40
Temperature ( C)
Time 200s/div
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AP3595
Performance Characteristics (Cont.)
EN On Waveform
EN Off Waveform
VPHASE1
10V/div
VRT/EN
1V/div
VPHASE1
10V/div
VRT/EN
1V/div
VOUT
1V/div
VOUT
1V/div
VSS
500mV/div
VSS
500mV/div
VHG
5V/div
VPHASE
5V/div
VLG
5V/div
Time 1ms/div
Time 200s/div
Dead Time 1
Dead Time 2
VHG
VHG
VPHASE
VLG
VHG
5V/div
VPHASE
5V/div
VLG
5V/div
Time 40ns/div
PSI Function
VFB
1V/div
VPSI
2V/div
VHG1
5V/div
VPHASE1
10V/div
VLG1
5V/div
VPHASE2
10V/div
Time 4s/div
Document number: DS36749 Rev. 1 - 2
VPHASE
Time 40ns/div
OVP Function
AP3595
VLG
Time 2ms/div
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AP3595
Performance Characteristics (Cont.)
VID Change
VID
5V/div
VOUT
200mV/div
Time 2ms/div
Application Information
1. Overview
AP3595 is a dual-phase synchronous-rectified buck controller designed to deliver high quality output voltage for high power applications. It is
capable of delivering up to 60A output current with embedded bootstrapped drivers that support 12V+12V driver capability. The built-in bootstrap
diode simplifies the circuit design and reduces external part count and PCB space.
The output voltage is precisely regulated to the reference input that is dynamically adjustable by external voltage divider. The adjustable current
balance is achieved by RDS(ON) current sensing technique.
AP3595 features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage
protection and over temperature protection.
Other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. With aforementioned
functions, the IC provides customer a compact, high efficiency, well-protected and cost effective solution.
2. Power on Reset
A Power On Reset (POR) circuitry continuously monitors the supply voltage at VCC. Once the rising POR threshold is exceeded, the AP3595 sets
itself to active state and is ready to accept chip enable command. The rising POR threshold is typically 9V.
3. Soft Start
The AP3595 initiates its soft start cycle when the RT/EN pin is released from ground once the POR is granted as shown in Figure 1.
Figure 1. Soft Start Cycle (RDRP=0)
AP3595
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Application Information (Cont.)
As mentioned in the above section, the slew rate of voltage transition at SS pin and VOUT during soft start and VREFIN jumping is controlled by the
capacitor connected to the SS pin. This reduces inrush current to charge/discharge the large output capacitors during soft start and VID changing,
and prevents OCP, OVP/UVP false trigger. The SS buffer sinking/sourcing capability is limited to 22A during soft start and 200A after soft start
end. Therefore, the slew rate of voltage ramping up/down at SS, EAP and FB pin during soft start or VID changing is calculated as:
During Soft Start
After Soft Start
dVSS dVEAP dVFB 22 A
dt
dt
dt
C SS
dVSS dVEAP dVFB 200 A
dt
dt
dt
C SS
4. Pre-Bias Function
AP3595 features pre-bias start-up capability. If the output voltage is pre-biased with a voltage VBIAS, that accordingly makes VFB higher than
reference voltage ramping VEAP. The error amplifier keeps VCOMP lower than the valley of the saw tooth waveform and makes PWM comparators
output low until the ramping VEAP catches up the feedback voltage. The IC keeps both upper and lower MOSFETs off until the first pulse takes
place.
5. Chip Oscillator Frequency Programming
A resistor RFS connected to RT/EN pin programs the oscillator frequency as:
f OSC
10000
(kHz)
RFS (k)
Figure 2 shows the relationship between oscillation frequency and RFS.
RFS (k)
Figure 2. Switching Frequency vs. RFS
When released, the RT/EN pin voltage is regulated at 1V. Pulling the RT/EN pin to ground shuts down the IC.
6. Current Balance
AP3595 extracts phase currents for current balance by parasitic on-resistance of the lower switches when turned on as shown in Figure 3.
_
PHASE
Sample
&Hold
+
ICS1
Current
Balance
ICS2
+
_
Reference
Voltage
Figure 3. RDS(ON) Current Sensing Scheme
The GM amplifier senses the voltage drop across the lower switch and converts it into current signal when it turns on. The sampled and held
current is expressed as:
I CSX I LX R DS( ON) 10 3 12A
AP3595
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AP3595
Application Information (Cont.)
Where ILX is the phase x current in Ampere, RDS(ON) is the on-resistance of low side MOSFET, 12A is a constant current to compensate the
offset voltage of the current sensing circuit.
AP3595 tunes the duty cycle of each channel for current balance according to the sensed inductor current signals as shown in Figure 4. If the
current of channel 1 is smaller than the current of channel 2, the IC increases the duty cycle of the corresponding phase to increase its phase
current accordingly, vice versa.
RAMP1
COMP
+
_
PWM1
+
_
PWM2
RAMP2
ICS2
+
ICS1
_
+
Figure 4. Current Balance Scheme of AP3595
7. Power Saving Interface (PSI)
The AP3595 supports dual phase or single phase which is controlled by VPSI. If VPSI>1.2V, AP3595 will operate in dual phase mode. If VPSI<0.4V,
AP3595 will operate in single phase mode. There is 2ms delay at the transient from dual phase to single phase, and no delay time from single
phase to dual phase.
8. Current Sense by DCR
PHASE1
PHASE2
AP3595
RCSP
L
L
RCSP
CSP
RDC
RDC
GM
Amplifier
+
-
CCS
IDRP IPSI IOCP
CSN
VOUT
RCSN
ICSN
Figure 5. Output Current Sensing Block
The above figure shows the output current sensing block of AP3595. The voltage VCS across the current sensing capacitor CCS can be expressed
as
VCS IOUT RDC / 2 ,
If the following condition is true:
2 L / RDC RCSP CCS
Where L is the output inductor of the buck converter, RDC is the parasitic resistance of the inductor, RCSP and CCS are the external RC network for
current sensing.
The GM amplifier will source a current ICSN to the CSN pin to let its inputs virtually short circuit.
ICSN RCSN VCS
Therefore the output current signal ICSN can be expressed as:
I CSN
I OUT RDC
2 RCSN
The output current signal ICSN is used to droop tuning and output over current protection.
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9. Short Circuit Protection (SCP)
The AP3595 has over current protection (OCP) and output under voltage protection (UVP) functions.
9.1 OCP Function
The sensed current signals are monitored for over current protection. If ICSN is higher than 60A, the over current protection OCP is activated.
Take the above case for example, the OCP level is calculated as:
I OCP
2 60 A 2k
120 A
2m
The OCP is of latch-off type and can be reset by toggling RT/EN or VCC POR.
9.2 UVP Function
The output feedback voltage VFB is also monitored for under voltage protection after soft start. The UV threshold is set as VFB-VSS<-0.3V. The
under voltage protection has 30s triggered delay. When UVP is triggered, both high side and low side are shutdown immediately.
OCP and UVP are latched functions. The IC can power off, and then power on or use RT/EN reset to restart again.
10. Over Voltage Protection (OVP)
The output voltage VFB is continuously monitored for over voltage protection. When it is 300mV higher than setting, the OVP function is triggered.
The over voltage protection has 30s triggered delay. When OVP is triggered, the LGATE will go high and the HGATE will go low to discharge the
output capacitor.
11. Droop Setting
In some high current applications, a requirement on precisely controlled output impedance is imposed. This dependence of output voltage on load
current is often termed droop regulation. The droop control block generates a voltage through external resistor RDRP (Which is between SS and
EAP) and then sets the droop voltage. The droop voltage, VDRP, is proportional to the total current in two channels (For more information about the
ICSN and IDRP, please refer to the current sense section). As shown in the following equation:
VFB VSS I DRP RDRP
Where IDRP is the droop current which is mirrored from ICSN. The output voltage also can be described as:
VFB VSS I DRP RDRP VSS
I OUT DCR1 RDRP
2 RCSN
12. Offset Current Setting
The AP3595 integrated IOFS allows the offset current to adjust phase current. The IOFS pin voltage is nominal 0.5V when connecting a resistor to
GND and 1.5V when connecting a resistor to VREF. Connecting a resistor from IOFS pin to GND generates a current source as:
I OFS 0.5V / RI OFS
This current is added to phase1 current signal I SEN1 for current balance. Consequently, phase2 will share more percentage of output current.
Connecting a resistor from IOFS pin to VREF pin generates a current source as:
I OFS (2V 1.5V ) / RI OFS
This current is added to phase2 current signal ISEN2 for current balance. Consequently, phase1 will share more percentage of output current.
13. PWM Compensation
The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase
shift in the control loop. A compensation network among COMP, FB, and VOUT should be added. The compensation network is shown in Figure 9.
The output LC filters consist of the output inductors and output capacitors. For two-phase convertor, when assuming that VIN1=VIN2=VIN, L1=L2=L,
the transfer function of the LC filter is given by:
GainLC
1 s RESR COUT
s (1 / 2) L COUT s RESR COUT 1
2
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The poles and zero of the transfer functions are:
f LC
1
2 (1/ 2) L COUT
f ESR
1
2 RESR COUT
The fLC is the double-pole frequency of the two-phase LC filters, and fESR is the frequency of the zero introduced by the ESR of the output
capacitors.
VPHASE1
VPHASE2
L1=L
VOUT
L2=L
COUT
RESR
Figure 6. The Output LC Filter
Figure 7. .Frequency Response of the LC Filters
The PWM modulator is shown in Figure 8. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of
the PWM modulator is given by:
GainPW M
VIN
VOSC
VIN
Driver
OSC
PWM
Comparator
-
ΔVOSC
PHASE
+
Output of Error
Amplifier
Driver
Figure 8.The PWM Modulator
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The compensation network is shown in Figure 9. It provides a close loop transfer function with the highest zero cross over frequency and sufficient
phase margin. The transfer function of error amplifier is given by:
1
1
//( R 2
)
VCOMP sC1
sC 2
Gain AMP
1
VOUT
R1 //( R3
)
sC 3
1
1
(s
) {s
}
R1 R3
R2 C 2
( R1 R3) C 3
1
R1 R3 C1 s ( s C1 C 2 ) ( s
)
R 2 C1 C 2
R3 C 3
The pole and zero frequencies of the transfer function are:
f Z1
1
2 R2 C 2
fZ 2
1
2 ( R1 R3) C 3
f P1
1
fP2
2 R2 (
C1 C 2
)
C1 C 2
1
2 R3 C 3
C1
R3
C3
R2
C2
VOUT
R1
FB
+
VCOMP
VREF
Figure 9.Compensation Network
The closed loop gain of the converter can be written as:
GainLC GainPW M GainAMP
Figure 10 shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network.
Using the below guidelines will give a compensation similar to the curve plotted. A stable closed loop has a-20dB/decade slope and a phase
margin greater than 45 degree.
1. Choose a value for R1, usually between 1k and 5k.
2. Select the desired zero crossover frequency.
fO (1/ 5 ~ 1/ 10) f SW
Use the following equation to calculate R2:
R2
VOSC f O
R1
VIN
f LC
3. Place the first zero fZ1 before the output LC filter double pole frequency fLC.
f Z 1 0.75 f LC
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Calculate the C2 by the equation:
C2
1
2 R 2 f LC 0.75
4. Set the pole at the ESR zero frequency fESR:
f P1 f ESR
Calculate the C1 by the following equation:
C1
C2
2 R 2 C 2 f ESR 1
5. Set the second pole fP2 at the half of the switching frequency and also set the second zero fZ2 at the output LC filter double pole fLC. The
compensation gain should not exceed the error amplifier open loop gain. Check the compensation gain at fP2 with the capabilities of the error
amplifier.
f P 2 0.5 f SW
f Z 2 f LC
Combine the two equations will get the following component calculations:
R3
R1
f SW
1
2 f LC
C3
1
R3 f SW
Figure 10.Converter Gain and Frequency
14. Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as:
D VOUT / VIN
For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple current, ΔI P-P, and affects the load transient
response. Higher inductor value reduces the output capacitors’ ripple current and induces lower output ripple voltage. The ripple current can be
approximated by:
I P P
VIN 2VOUT VOUT
f SW L
VIN
Where fSW is the switching frequency of the regulator.
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Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s
ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the
expense of higher ripple current. Increasing the switching frequency (f SW ) also reduces the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A
good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been
chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially
core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage.
15. Output Capacitor Selection
Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting output capacitors.
Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR
capacitors is recommended for switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the
output voltage ripple includes the capacitance voltage drop ΔVCOUT and ESR voltage drop ΔVESR caused by the AC peak-to-peak sum of the
inductor’s current. The ripple voltage of output capacitors can be represented by:
VCOUT
I P P
8 COUT f SW
VESR I P P RESR
These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled
to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors are
needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. As mall decoupling capacitor in parallel for by
passing the noise is also recommended, and the voltage rating of the output capacitors must be considered too.
To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load
step change.
For getting same load transient response, the output capacitance of two-phase converter only needs to be around half of output capacitance of
single-phase converter.
Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current
specified on the capacitors in order to prevent the capacitor from overheating.
16. Input Capacitor Selection
Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET
turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of lowside MOSFET.
The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk
capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For twophase converter, the RMS current of the bulk input capacitor is roughly calculated as the following equation:
I RMS
I OUT
2 D (1 2 D )
2
For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tantalum capacitors can be used, but
caution must be exercised with regard to the capacitor surge current rating.
17. MOSFET Selection
The AP3595 requires two N-Channel power MOSFETs on each phase. These should be selected based upon RDS(ON), gate supply requirements
and thermal management requirements.
In high current applications, the MOSFET power dissipation, package selection, and heat sink are the dominant design factors. The power
dissipation includes two loss components: conduction loss and switching loss.
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The conduction losses are the largest component of power dissipation for both the high-side and the low-side MOSFETs. These losses are
distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since
the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous
rectifier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due to the reverse-recovery
of the low-side MOSFET body diode. The gate-charge losses are dissipated by AP3595 and don’t heat the MOSFETs. However, large gatecharge increases the switching interval tSW, which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their
maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance
specifications. A separate heat sink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
For the high-side and low-side MOSFETs, the losses are approximately given by the following equations:
PHIGH-SIDE=IOUT2×(1+TC) ×RDS(ON)×D+0.5×IOUT×VIN×tSW×fSW
PLOW-SIDE=IOUT2×(1+TC)×(RDS(ON))×(1-D)
Where IOUT is the load current, TC is the temperature dependency of RDS(ON), fSW is the switching frequency, tSW is the switching interval, D is the
duty cycle.
Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, tSW, is
the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET.
18. Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance
and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is
carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The
best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less
noise. Noisy traces beneath the IC are not recommended. Figure 11 illustrates the layout, with bold lines indicating high current paths; these
traces must be short and wide. Components along the bold lines should be placed close together. Below is a checklist for your layout:
1. Keep the switching nodes (HGx, LGx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast moving signals.
Therefore keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any
layer.
2. The signals going through theses traces have both high dv/dt and high dI/dt with high peak charging and discharging current. The traces from
the gate drivers to the MOSFETs (HGx and LGx) should be short and wide.
3. Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide
layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs
(VIN and PHASEx nodes) can get better heat sinking.
4. For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid
the noise interference, the current sensing trace should be away from the noisy switching nodes.
5. Decoupling capacitors, the resistor-divider, and the boot capacitor should be close to their pins. (For example, place the decoupling ceramic
capacitor as close as possible to the drain of the high-side MOSFET).The input bulk capacitors should be close to the drain of the high-side
MOSFET, and the output bulk capacitors should be close to the loads.
6. The input capacitor’s ground should be close to the grounds of the output capacitors and the low-side MOSFET.
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7. Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching
signal traces (HGx, LGx, BOOTx, and PHASEx).
HG1
HG2
Figure 11.The Layout of AP3595
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Ordering Information
AP3595 XX XX - XX
Product Name
Package
FN: U-QFN4040-24
Packing
RoHS/Green
TR : Tape & Reel
G1 : Green
Diodes IC’s Pb-free products with "G1" suffix in the part number, are RoHS compliant and green.
Package
Temperature Range
U-QFN4040-24
-40°C to +85°C
Part Number
AP3595FNTR-G1
Marking ID
B3D
Packing
5000/Tape & Reel
Marking Information
First Line: Logo and Marking ID
Second and Third Lines: Date Code
Y: Year
WW: Work Week of Molding
M: Assembly House Code
XX: 7th and 8th Digits of Batch No.
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Package Outline Dimensions (All dimensions in mm(inch).)
(1)
Package Type: U-QFN4040-24
0.200(0.008)
0.500(0.020)
MIN
BSC
3.900(0. 154)
4.100(0.161)
N24
N19
PIN # 1 IDENTIFICATION
See DETAIL A
N1
Pin 1 Mark
3.900(0. 154)
4.100(0. 161)
D
N13
N7
0.300(0.012)
0.500(0.020)
0.180(0. 007)
E
0.300(0. 012)
0.000(0.000)
0.050(0.002)
DETAIL A
A3
A
22
23
24
22
23
24
22
23
24
1
1
1
2
2
2
3
3
3
Pin 1 Options
D=E
Symbol
A3
A
min(mm) max(mm) min(inch) max(inch) min(mm) max(mm) min(inch) max(inch) min(mm) max(mm) min(inch) max(inch)
Option1
2.600
2.800 0.102
0.110
0.700
.
0.850 0.028
0.033
0.153
0.253 0.006
0.010
0.253 0.006
0.010
0.175 0.005
0.007
Option2
2.350
2.550 0.093
0.100
0.700
0.850 0.028
0.033
0.153
Option3
2.600
2.800 0.102
0.110
0.550
0.650 0.022
0.026
0.125
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Suggested Pad Layout
(1)
Package Type: U-QFN4040-24
E
Y1
E
Y
Y3
Y2
X3
X2
X1
X
Dimensions
X=Y
(mm)/(inch)
X1=Y2
(mm)/(inch)
Y1=X2
(mm)/(inch)
X3=Y3
(mm)/(inch)
E
(mm)/(inch)
Value
4.400/0.173
0.300/0.012
0.650/0.026
2.800/0.110
0.500/0.020
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IMPORTANT NOTICE
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
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Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
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This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
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Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
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representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2013, Diodes Incorporated
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