CYPRESS CY62157ESL

CY62157ESL MoBL®
8-Mbit (512K x 16) Static RAM
Features
■
Very high speed: 45 ns
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (IO0 through IO15) are
placed in a high impedance state when:
■
Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■
Deselected (CE HIGH)
■
Ultra low standby power
❐ Typical Standby current: 2 μA
❐ Maximum Standby current: 8 μA
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-pin TSOP II package
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A18).
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SENSE AMPS
DATA IN DRIVERS
512K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
Cypress Semiconductor Corporation
Document #: 001-43141 Rev. **
•
A17
A18
A15
198 Champion Court
A16
A14
BLE
A12
A13
BHE
A11
CE
Power Down
Circuit
•
BHE
WE
CE
OE
BLE
San Jose, CA 95134-1709
•
408-943-2600
Revised January 04, 2008
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CY62157ESL MoBL®
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
A8
A9
A10
A11
A12
A13
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V) [1]
Speed
(ns)
Operating ICC, (mA)
f = 1MHz
Typ
CY62157ESL
Industrial
2.2V–3.6V and 4.5V–5.5V
45
[2]
1.8
f = fmax
Standby, ISB2
(μA)
Max
Typ [2]
Max
Typ [2]
Max
3
18
25
2
8
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA = 25°C.
Document #: 001-43141 Rev. **
Page 2 of 12
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CY62157ESL MoBL®
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential..................–0.5V to 6.0V
Device
Range
Ambient
Temperature
VCC[5]
DC Voltage Applied to Outputs
in High-Z State[3, 4] ...........................................–0.5V to 6.0V
CY62157ESL
Industrial
–40°C to +85°C
2.2V–3.6V,
and
4.5V–5.5V
DC Input Voltage[3, 4] ........................................–0.5V to 6.0V
Electrical Characteristics
Over the Operating Range
45 ns
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
2.4
Max
IOH = –1.0 mA
IOL = 0.1 mA
0.4
2.7 < VCC < 3.6
IOL = 2.1mA
0.4
4.5 < VCC < 5.5
IOL = 2.1mA
0.4
2.2 < VCC < 2.7
1.8
VCC + 0.3
2.7 < VCC < 3.6
2.2
VCC + 0.3
4.5 < VCC < 5.5
2.2
VCC + 0.5
2.2 < VCC < 2.7
–0.3
0.6
2.7 < VCC < 3.6
–0.3
0.8
4.5 < VCC < 5.5
–0.5
0.8
Input Leakage Current
Output Leakage Current GND < VO < VCC, Output Disabled
GND < VI < VCC
ICC
VCC Operating Supply
Current
f = fmax = 1/tRC
f = 1 MHz
Unit
V
4.5 < VCC < 5.5
IIX
ISB2
Typ [2]
2.2 < VCC < 2.7
IOZ
ISB1
Min
V
V
V
–1
+1
μA
–1
+1
μA
mA
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
Automatic CE Power
CE > VCC − 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
down Current — CMOS f = fmax (Address and Data Only),
Inputs
f = 0 (OE, BHE, BLE and WE), VCC = VCC(max)
Automatic CE Power
CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
down Current — CMOS f = 0, VCC = VCC(max)
Inputs
18
25
1.8
3
2
8
μA
2
8
μA
Notes
3. VIL(min) = –2.0V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
TSOP II
Unit
77
°C/W
13
°C/W
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
10%
GND
R2 Rise Time = 1 V/ns
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5V
3.0V
5.0V
Unit
R1
16667
1103
1800
Ω
R2
15385
1554
990
Ω
RTH
8000
645
639
Ω
VTH
1.20
1.75
1.77
V
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
[6]
Conditions
Min
Max
1.5
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
2
5
VCC = 2.0V
2
8
Operation Recovery Time
Unit
V
VCC = 1.5V
Chip Deselect to Data
Retention Time
tR [7]
Typ[2]
μA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
CE or
BHE.BLE
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
[8]
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Switching Characteristics
Over the Operating Range [9]
Parameter
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
45
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
18
ns
LOW-Z[10]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[10, 11]
tLZCE
CE LOW to Low-Z[10]
ns
45
10
ns
5
ns
10
High-Z[10, 11]
ns
ns
tHZCE
CE HIGH to
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
45
ns
tDBE
BLE/BHE LOW to Data Valid
45
ns
tLZBE
tHZBE
BLE/BHE LOW to
Low-Z[10, 12]
BLE/BHE HIGH to
HIGH-Z[10, 11]
18
0
ns
ns
5
ns
18
ns
Write Cycle[13]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[10, 11]
[10]
WE HIGH to Low-Z
18
10
ns
ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. If both byte enables are toggled together, this value is 10 ns.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Switching Waveforms
Figure 2. Read Cycle No.1: Address Transition Controlled. [14, 15]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle No. 2: OE Controlled [15, 16]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
Notes
14. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
15. WE is HIGH for read cycle.
16. Address valid before or similar to CE, BHE, BLE transition LOW.
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 4. Write Cycle No 1: WE Controlled [13, 17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 19
tHD
DATAIN
tHZOE
Figure 5. Write Cycle 2: CE Controlled [13, 17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 19
tHZOE
Notes
17. Data IO is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
19. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-43141 Rev. **
Page 8 of 12
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CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle 3: WE controlled, OE LOW [18]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA IO
NOTE 19
tHD
DATAIN
tLZWE
tHZWE
Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [18]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 19
tSD
tHD
DATAIN
tLZWE
Document #: 001-43141 Rev. **
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CY62157ESL MoBL®
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Inputs/Outputs
Deselect/Power down
Mode
Standby (ISB)
Power
X
X
X
H
H
High-Z
Deselect/Power down
Standby (ISB)
L
H
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
Ordering Code
CY62157ESL-45ZSXI
Document #: 001-43141 Rev. **
Package
Diagram
Package Type
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Operating
Range
Industrial
Page 10 of 12
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CY62157ESL MoBL®
Package Diagrams
Figure 8. 44-Pin TSOP II, 51-85087
51-85087-*A
Document #: 001-43141 Rev. **
Page 11 of 12
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CY62157ESL MoBL®
Document History Page
Document Title: CY62157ESL MoBL® 8-Mbit (512K x 16) Static RAM
Document Number: 001-43141
REV.
ECN NO.
Issue Date
**
1875228
See ECN
Orig. of
Change
Description of Change
VKN/AESA New Data Sheet
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43141 Rev. **
Revised January 04, 2008
Page 12 of 12
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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